JPH09120674A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which read operation can be performed reliably without destructing cell information. SOLUTION: A local data bus LDB and a bar LDB are connected with a global data bus GDB and a bar GDB through a switch circuit 14. Cell information read out from a memory cell C is amplified through a sense amplifier SA and rewritten in the memory cell C thus performing the read operation of cell information. The data bus LDB and bar LDB are connected with a first precharge circuit 15 being inactivated upon conduction of a switch circuit 14 and activated when the switch circuit 14 is not conducting at the time of reading and writing operations of cell information to precharge the data bus LDB and bar LDB with the intermediate level of power supply, and a second precharge circuit 16 being activated when the switch circuit 14 is not conducting at the time of reading and writing operations to operate the sense amplifier SA stably.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device for writing and reading cell information and having a global data bus and a local data bus.

In recent years, semiconductor memory devices have become increasingly large in capacity and highly integrated. In such a semiconductor memory device, a data bus is divided into a global data bus and a local data bus for high integration, and there is a DRAM which requires a refresh operation of cell information.
Then, the refresh cycle may be changed depending on the usage status. In a DRAM provided with a global data bus and a local data bus, it is necessary to surely perform the refresh operation even if the refresh cycle is changed.

[0003]

2. Description of the Related Art A data bus is a global data bus,
FIG. 5 shows a conventional example of a DRAM composed of a local data bus.

A large number of storage cells C are connected to each of a plurality of pairs of bit lines BL and BL, and each storage cell C is connected to a word line WL. Each bit line BL,
The bar BL is connected to the sense amplifier SA, and the local data bus LD is connected via the transfer gate Tg.
B, connected to LDB. For example, two pairs of the local data buses LDB and LDB are laid out for each block of the memory cell array.

The local data bus LDB, bar LD
A precharge circuit 1 is connected to each B. In the precharge circuit 1, the precharge voltage VPR is input to the drains of the N-channel MOS transistors Tr1 and Tr2 whose control signal φ1 is input to the gates, and the sources are connected to the local data buses LDB and LDB, respectively.

Therefore, when the control signal φ1 goes high, the local data buses LDB and LDB are reset to the precharge voltage VPR. Precharge voltage VPR
As a result, 1/2 Vcc is supplied.

The local data bus LDB, bar LD
B is connected to one of a plurality of pairs of global data buses GDB and GDB via the switch circuit 2, respectively. A control signal φ2 and an inverted signal thereof are input to each switch circuit 2, and when the control signal φ2 becomes L level, the switch circuit 2 becomes conductive and the local data buses LDB and LDB are connected to the global data buses GDB and GDB. It

The global data bus GDB and bar G
DB is a local data bus LDB of a plurality of blocks,
It is connected to the bar LDB via the switch circuit 2, and is connected to any one of a pair of local data buses LDB and bar LDB under the control of the switch circuit 2.

The global data bus GDB and bar G
The DB is connected to an input / output buffer circuit (not shown) and the current load circuit 3 is connected to each. When the current load circuit 3 supplies a constant current to the global data buses GDB and GDB during a cell information read operation, the switch circuit 2 becomes non-conductive, and write data is not input from the input / output buffer circuit. Resets the global data buses GDB and GDB to the same potential.

As shown in FIG. 6, the sense amplifier SA has a normal flip-flop structure, and cell lines are supplied to the bit lines BL and BL under the condition that the high potential side power source VP and the low potential side power source VN are supplied. When the information is read and a slight potential difference occurs, the potential difference is amplified and output.

In the DRAM thus constructed, the control signal φ2 is at H level during the standby operation.
The switch circuit 2 is turned off, the control signal φ1 goes high, and the precharge circuit 1 is activated. Therefore, the local data buses LDB and LDB are reset to 1/2 Vcc.

At the time of reading cell information, a specific memory cell is selected in each selected block based on an address signal input from the outside, and read data is output to the local data buses LDB and LDB. A pair of local data buses LDB, LDB are connected to the respective pairs of global data buses GDB, GDB by the switch circuit 2, and read data read out to the local data buses LDB, LDB, It is output as output data from the input / output terminal via each global data bus GDB, bar GDB and the output buffer circuit.

In the write operation, the write data input from the input / output terminal is output to the global data buses GDB and GDB via the input buffer circuit and the write amplifier, and the write data is the selected local data. Bus LDB, bar LDB, sense amplifier SA of selected column and bit line BL, bar B
It is written into the memory cell C via L.

During the cell information refresh operation, the word line W selected based on the row address signal.
The cell information of the memory cell C connected to L is refreshed. The control signal φ1 goes to H level, the control signal φ2 goes to L level, the precharge circuit 1 is activated, and the switch circuit 2 is turned on to make the local data bus LDB, the bar LDB and the global data bus GD.
B and bar GDB are precharged. In this state, a specific memory cell C is selected, cell information read from the memory cell C is amplified by the sense amplifier SA, and written in the memory cell C.

[0015]

DRAM as described above
Then, depending on the usage mode, for example, in a storage capacity of 16 Mbits, a refresh cycle in which a refresh operation of all memory cells completes a cycle by 4K refresh operations, or a refresh cycle of all memory cells completes a cycle in 1K refresh operations. It may be used after changing to a cycle.

To change the refresh cycle as described above, by fixing the upper 2 bits of the row address, the number of blocks simultaneously performing the refresh operation is quadrupled and the number of memory cells simultaneously refreshed is quadrupled. Done by.

Due to such a change in the refresh cycle, in the read mode, the read operation of the cell information is performed in the state where the precharge circuit 1 is inactivated and the switch circuit 2 is conductive in accordance with the control signals φ1 and φ2. In a block in which the precharge circuit 1 is activated, the precharge circuit 1 is activated, and the switch circuit 2 is non-conductive, the cell information read from the selected memory cell is output to the local data buses LDB and LDB. That is, that is, a block in which an operation corresponding to the refresh operation is performed.

FIG. 7 shows a read operation when the precharge circuit 1 is inactivated and the switch circuit 2 is conductive.
Shown in That is, the potential of the bit lines BL and BL is 1
When the specific word line WL rises to the H level based on the row address signal from the state of being reset to / 2Vcc, cell information is transferred from the memory cell C connected to the word line WL to the bit lines BL and BL. After being read, a slight potential difference is generated between the bit line BL and the bar BL.

Then, when the high potential side power source VP and the low potential side power source VN are supplied to the sense amplifier SA, the sense amplifier SA is activated and the potential difference between the bit lines BL and bar BL is enlarged.

Next, when the column selection signal CL becomes H level and the column is selected, 1/2 Vcc is applied.
Local data bus LDB, which is precharged to
Although the bar LDB becomes a load of the sense amplifier SA, the potential difference between the bit lines BL and BL is slightly reduced, but the constant current supplied from the current load circuit 3 is the potential of the high potential side output terminal of the sense amplifier SA. , So that the potential of the low potential side output terminal is lowered.

Therefore, the potential difference between the bit lines BL and BL is enlarged, and the refresh operation of the selected memory cell C is performed based on the bit line potential. However,
The precharge circuit 1 is activated and the switch circuit 2
When the read operation (refresh operation) is performed in a state in which the column selection signal CL is at the H level and the column is selected, the precharge circuit 1 is turned on as shown in FIG. Are activated, the potentials of the bit lines BL and bar BL both approach 1/2 Vcc, and the potentials of the bit lines BL and bar BL are easily inverted.

At this time, if noise is mixed in the high-potential-side power source VP and the low-potential-side power source VN of the sense amplifier SA based on the rising of the column selection signal CL, the bit line B
The potentials of L and bar BL may be inverted. Therefore,
The read operation (refresh operation) may destroy the cell information of the selected memory cell C.

An object of the present invention is a semiconductor capable of surely performing a read operation without destroying cell information even if a read operation is performed in a state where a local data bus is not connected to a global data bus. A storage device is provided.

[0024]

FIG. 1 is an explanatory view of the principle of claim 1. That is, the word line WL and the bit lines BL and BL are connected to a large number of memory cells C,
A sense amplifier SA that amplifies cell information is connected to the bit lines BL and BL. The bit lines BL and bar BL are connected to local data buses LDB and bar L via a transfer gate Tg which is opened / closed based on a column selection signal CL.
A global data bus GDB and a bar GDB are connected to the local data bus LDB and the bar LDB via a switch circuit 14 respectively. Cell information is read from the memory cell C selected on the basis of the row address signal to the bit lines BL and BL, the cell information is amplified by the sense amplifier SA, and the memory cell C is rewritten. By doing so, the read operation of the cell information is performed. The local data buses LDB and LDB are deactivated when the switch circuit 14 is conducting and activated when the switch circuit 14 is non-conducting.
First precharge circuit 15 for precharging B and bar LDB to an intermediate level between the high potential side power source and the low potential side power source
And a second precharge circuit 16 which is activated when the switch circuit 14 becomes non-conductive during the write and read operations and operates to stably operate the sense amplifier SA.

In the second aspect, the second precharge circuit precharges the local data bus to the high-potential-side power supply voltage. In claim 3, the second precharge circuit supplies a constant current to the local data bus.

(Operation) According to the first aspect, when the switch circuit 14 becomes non-conductive at the time of writing and reading the cell information, the operation of the second precharge circuit 16 causes
The potentials of the local data buses LDB and LDB are maintained at a potential at which the sense amplifier SA operates stably.

In the second aspect, the second precharge circuit precharges the local data bus to the power supply voltage on the high potential side, and the sense amplifier operates stably. In the third aspect, a constant current is supplied to the local data bus by the second precharge circuit, and the sense amplifier operates stably.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a D embodying the present invention.
A memory cell array of RAM is shown. The memory cell array is composed of a large number of blocks 11a to 11d, and the word lines of the blocks 11a to 11d are row decoders 12 respectively.
It is selected from a to 12b. In addition, each block 11a-1
The 1d bit line is a common bit line selected by the common column decoder 13.

Each block 11a-11d has two
Local data bus LDBa, bar LDBa for each pair ~
LDBd and bar LDBd are laid out. Two pairs of local data buses LDB in the block 11a
a and bar LDBa are global data buses GDB1,
The bar GDB1, the GDB2, and the bar GDB2 are respectively connected via a switch circuit 14.

The two pairs of local data buses LDBb and LDBb of the block 11b are global data buses GDB3 and GDB3 and GDB4 and GDB.
4 are connected via switch circuits 14, respectively.

The two pairs of local data buses LDBc and LDBc of the block 11c are global data buses GDB1 and GDB1 and GDB2 and GDB2.
2 is connected to each of the two via a switch circuit 14.

The two pairs of local data buses LDBd and LDBd of the block 11d are global data buses GDB3 and GDB3 and GDB4 and GDB4.
4 are connected via switch circuits 14, respectively.

Local data buses LDBa, bars LDBa to LDBd, and bars L of the blocks 11a to 11d are provided.
A first precharge circuit 15 and a second precharge circuit 16 are connected to DBd, respectively.

The memory cell array thus constructed has the same structure as that of the conventional example except for the second precharge circuit 16. For example, the refresh operation of all memory cells is completed by 4K refresh operations. In the cycle, when the blocks 11a and 11b are refreshed, the blocks 11c and 11d are not refreshed.

When the blocks 11c and 11d are read out, the blocks 11a and 11b are not read out. Then, the first and second precharge circuits 15 and 16 of the block to be read out are turned off, the switch circuit 14 is turned on, and the local data bus is connected to the global data bus.

The first precharge circuit 15 of the block which is not read out is turned on, the second precharge circuit 16 is turned off, the switch circuit 14 becomes non-conductive, and the local data bus and the global data bus are connected. Is not connected.

In the refresh cycle in which the refresh operation of all memory cells is completed by the refresh operation of 1K times, the blocks 11a to 11d are simultaneously refreshed.

When performing the read operation, the blocks 11a,
In 11b, the switch circuit 14 is turned on and the first and second precharge circuits 15 and 16 are deactivated, and in the blocks 11c and 11d, the switch circuit 14 is turned off and the second precharge circuit 16 is turned off. Only are activated.

FIG. 3 shows a concrete structure of each of the blocks 11a to 11d. In the figure, except for the second precharge circuit 16, the configuration is the same as the conventional example. The second precharge circuit 16 includes a local data bus LD
The sources of N-channel MOS transistors Tr11 and Tr12 are connected to B and LDB respectively, and the drains of the transistors Tr11 and Tr12 are connected to the power supply Vcc.

A control signal φ3 is input to the gates of the transistors Tr11 and Tr12. The control signal φ3 is at L level during normal write and read operations in which the switch circuit 14 is conductive, and is also at L level in the refresh operation when the control signal φ2 is at L level and the switch circuit 14 is conductive. Become.

When the control signal φ2 goes high and the switch circuit 14 becomes non-conductive, the control signal φ3 goes high.
The level of the control signal φ1 is controlled so that it becomes L level.

Each of the control signals φ1 to φ3 is generated based on the row address signal, the column address signal and the refresh mode signal. When the cell information read operation is performed in the DRAM configured as described above, the control signal φ2 becomes L level, and the switch circuit 1
When 4 becomes conductive, the control signals .phi.1 and .phi.3 become L level, and the first and second precharge circuits 15 and 16 are both deactivated.

Therefore, like the conventional example, the current load circuit 3 is connected to the local data buses LDB and LDB via the global data buses GDB and GDB, and is selected by the sense amplifier SA. The cell information of the stored memory cell C is refreshed.

Further, the control signal φ2 becomes H level,
When the switch circuit 14 becomes non-conductive, the control signal φ1
Goes to the L level to deactivate the first precharge circuit 15, and the control signal φ3 goes to the H level to activate the second precharge circuit 16.

Then, the local data buses LDB and LDB are precharged to the power supply Vcc level, and in this state, the column selection signal CL rises to H level, and the bit lines BL and bar BL of the selected column are changed to the local data bus. It is connected to LDB and LDB.

Then, by the operation of the second precharge circuit 16, the potentials of the bit lines BL and BL to which the potential obtained by amplifying the cell information is output rises toward the power supply Vcc level, but the bit line BL. , BL is close to the power supply Vcc level, it is out of the threshold value of the sense amplifier SA, so that the potentials of the bit lines BL, BL are not easily inverted.

At this time, even if noise is mixed in the high-potential-side power source VP and the low-potential-side power source VN of the sense amplifier SA based on the rise of the column selection signal CL, the bit line B
The potentials of L and BL are not easily inverted.

Therefore, the cell information of the selected memory cell C is not destroyed by the read operation (refresh operation). As described above, in this DRAM, the global data bus GDB,
Local data bus LDB not connected to the bar GDB,
Since the bar LDB is precharged to the power supply Vcc level by the second precharge circuit 16, even if the sense amplifier SA performing the read operation (refresh operation) is connected to the local data bus LDB and bar LDB, It is possible to prevent the destruction of.

FIG. 4 shows the second precharge circuit 16 described above.
Another example will be shown. This precharge circuit 16a has a power source V
N-channel MOS transistors Tr13 and Tr14 are connected in series between cc and the ground GND, and the same transistor T
Local data buses LDB and LDB are connected to the connection points of r13 and Tr14, respectively. The transistor Tr13
Is set to have a larger current supply capacity than the transistor Tr14. The control signal φ is applied to the gates of the transistors Tr13 and Tr14.
3 is input.

Precharge circuit 1 configured as described above
6a supplies a constant current to the local data buses LDB and LDB when the control signal .phi.3 becomes H level and is activated, and operates similarly to the current load circuit 3.

Therefore, during writing and reading operations,
Even if the read operation (refresh operation) is performed in a state where the local data buses LDB and LDB are not connected to the global data buses GDB and GDB, the cells are similarly to those when they are connected to the global data buses GDB and bar GDB. The refresh operation can be performed without destroying information.

The technical ideas other than the claims that can be understood from the above-described embodiment will be described below along with their effects. (1) In the second precharge circuit according to claim 2, the drain is supplied with a high-potential-side power supply, the source is connected to a local data bus, and the gate is turned off by the switch circuit during a read operation. At this time, an N channel MOS transistor to which an H level control signal is input is used. The second precharge circuit that supplies the precharge voltage that enables the sense amplifier to operate stably based on the control signal can be configured by a simple circuit.

(2) In claim 3, the second precharge circuit is the same circuit as the current load circuit connected to the global data bus, and is at H level when the switch circuit becomes non-conductive during a read operation. It is configured to be activated by the control signal. A second precharge circuit that operates in the same way as the current load circuit based on the control signal.
The sense amplifier can be operated stably.

[0054]

As described above in detail, according to the present invention, even if the read operation is performed in the state where the local data bus is not connected to the global data bus, the read operation can be surely performed without destroying the cell information. It is possible to provide a semiconductor memory device that can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a schematic diagram showing a memory cell array according to one embodiment.

FIG. 3 is a circuit diagram showing an embodiment.

FIG. 4 is a circuit diagram showing another example of a second precharge circuit.

FIG. 5 is a circuit diagram showing a conventional example.

FIG. 6 is a circuit diagram showing a sense amplifier.

FIG. 7 is a waveform diagram showing a read operation of a conventional example.

FIG. 8 is a waveform diagram showing a read operation of a conventional example.

[Description of Reference Signs] 14 switch circuit 15 first precharge circuit 16 second precharge circuit C storage cell WL word line BL, bar BL bit line CL column selection signal SA sense amplifier Tg transfer gate LDB, bar LDB local data Bus GDB, Bar GDB Global data bus

Claims (3)

[Claims] 1. A transfer in which a word line and a bit line are respectively connected to a large number of storage cells, a sense amplifier for amplifying cell information is connected to the bit line, and the bit line is opened / closed based on a column selection signal. A local data bus is connected via a gate, a global data bus is connected to the local data bus via a switch circuit, and cell information is read from a memory cell selected based on a row address signal to the bit line, A semiconductor memory device for performing a read operation of cell information by amplifying the cell information by the sense amplifier and rewriting the memory cell, wherein the local data bus is connected to the switch circuit when the switch circuit is turned on. It is deactivated and activated when the switch circuit is non-conducting to bring the local data bus to high voltage. A first precharge circuit for precharging to an intermediate level between the side power supply and the low potential side power supply, and activated when the switch circuit becomes non-conducting during the writing and reading operations of the cell information, thereby turning on the sense amplifier. A semiconductor memory device connected to a second precharge circuit which operates so as to operate stably. 2. The semiconductor memory device according to claim 1, wherein the second precharge circuit precharges the local data bus to a high-potential-side power supply voltage. 3. The semiconductor memory device according to claim 1, wherein the second precharge circuit supplies a constant current to the local data bus.