KR100557571B1 - Data Bus Line Precharge Device for Semiconductor Memory Devices - Google Patents

Abstract

The present invention relates to a data bus line precharge device of a semiconductor memory device, and more particularly, to a local data bus line after a write operation by providing a local data bus line precharge device in addition to the existing global data bus line precharge device. The present invention relates to a data busline precharge device of a semiconductor memory device for rapidly precharging a circuit to realize a high speed memory operation. A local data bus line precharge generating means for outputting; And connection means for precharging the pair of local data bus lines by operating on the local data bus line precharge signal during a precharge operation.

Description

Data Bus Line Precharge Device for Semiconductor Memory Devices

The present invention relates to a data busline precharge device of a semiconductor memory device. More particularly, the present invention relates to a data busline precharge device, which includes a local data busline precharge device that operates at a column address in addition to a conventional global data busline precharge device. The present invention relates to a data bus line precharge device of a semiconductor memory device for rapidly precharging a global data bus line and a local data bus line after operation to realize a high speed memory operation.

1 is a diagram illustrating a layout relationship of a conventional memory cell array and a data bus line. The local data bus lines LDB and / LDB write data to a bit line sense amplifier when a column line is enabled. Or, it receives data from the bit line sense amplifier and delivers the data to the global data bus lines GDB and / GDB.

Here, the global data bus lines GDBi and / GDBi and the local data bus lines LDBi and / LDBi are represented by one line for a concise representation with a compensation structure.

The memory cell array is arranged globally with a word line in the row direction and a column line in the column direction starting at the column decoder.

In addition, the present invention includes a write driver and a read amplifier involved in precharging the global data bus lines GDBi and / GDBi, and a data input / output buffer for data input / output.

Here, precharging of the global data bus lines GDBi and / GDBi is performed by a device provided in the write driver, and precharging of the local data bus lines LDBi and / LDBi is performed by a block selection signal of a specific memory block. BlkSel is made high and the MOS transistor is turned on to be performed by the global data bus lines GDBi and / GDBi.

First, when a write command is input during the write operation, the write driver activates the global data bus line GDB to the power supply potential level Vdd and / GDB to the ground potential level Vss or vice versa.

At this time, the column line selected by the column address is enabled to write data to the bit line sense amplifier, and the global data bus lines GDBi and GDBi and the local data bus lines LDBi and LDBi are specified for the next operation. Precharged to level.

If the read command comes in at the next clock, the weak signal of the bit line sense amplifier should drive the low data bus lines (LDBi, / LDBi) with heavy loads.The low data bus lines (LDBi, / LDBi) If the precharge speed is slow and not precharged, a read error may occur due to collision with data driven by the actual bit line sense amplifier.

The root cause of this error is that the driving force of the bit line sense amplifier is weak and the load of the local data bus lines (LDBi, / LDBi) is relatively high, so the difference between the pairs of local data bus lines (LDBi, / LDBi) during the read operation. Is limited to about a few hundred kilowatts.

Therefore, if the low-local data busline pairs LDBi and / LDBi are not equalized to the same level before the read operation, the amount of read data may be reduced or destroyed. The shorter the precharge time of (GDBi, / GDBi), the more serious it is.

The present invention was devised to solve the above-described problems of the prior art, and after the write operation, the global data busline pair is precharged to the power potential level by a conventional light driver, and the low-local data busline pair LDBi, / LDBi) includes a local data bus line precharge generator which inserts an equalizing transistor between the local data bus line pairs LDBi and / LDBi and generates a local data bus line precharge signal by a column address. The data bus line of the semiconductor memory device improves the operating speed of the memory chip by equalizing the low data bus line precharge signal while having a logic low and simultaneously precharging it to a power supply potential level by a global data bus line pair. The purpose is to provide a precharge device.

The present invention for achieving the above object is a plurality of memory cell array;

A bit line sense amplifier configured to sense the cell data;

A pair of local data buslines coupled to said bitline sense amplifiers via predetermined means;

A read / write operation is performed by a pair of global data bus lines connected to a write driver and a read amplifier and commonly exchange data in a memory cell block, and precharged by a precharge device existing in the write driver during a precharge operation. In a semiconductor memory device,

Local data bus line precharge generating means for outputting a local data bus line precharge signal during a precharge operation in response to a column address;

And a connection means for precharging the pair of local data bus lines by operating on the local data bus line precharge signal during a precharge operation.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a data bus line precharge device according to an embodiment of the present invention, wherein a local data busline precharge signal is enabled by logic low after a predetermined time delay of a column address input to an existing precharge device. An equalization transistor connected between the local data bus line precharge generator 100 generating (/ LDBpcg) and the local data bus line pair and turned on the local data bus line precharge signal (/ LDBpcg). In addition, the precharge speed of the data bus line is improved by adding 200, where the equalization transistor 200 may use an NMOS transistor instead of a PMOS transistor, and at this time, a low-calorie data bus line precharge signal ( / LDBpcg) will operate at logic high.

Hereinafter will be described in detail the operation relationship for the present invention having the above configuration.

First, in order to write data to or read data from a DRAM cell, a row address must be specified. When the row address is input to the row decoder, cell arrays in the corresponding row direction are activated.

Herein, the activation means a series of steps in which a word line is enabled, cell data is loaded on a bit line, and amplified by a bit line sense amplifier as in the conventional DRAM operation.

Thereafter, the block selection signal BlkSel is enabled to connect the low data bus lines LDBi and / LDBi and the global data bus lines GDBi and / GDBi.

Next, when the sensing operation of the data on the bit line is performed and a command written in the memory chip is input from the outside, the data passing through the data input buffer is transferred to each memory cell array through the global data bus lines GDBi and GDBi.

In the case of a write operation, the write driver operates to transfer data on the global data bus lines GDBi and GDBi to a specific block.

At this time, the column line selected by the column address input to the column decoder is enabled to write data to the block which is already activated.

The data loaded on the global data bus lines GDBi and / GDBi driven by the write driver are transferred to the local data bus lines LDBi and / LDBi and write data to the cell designated by the selected column line.

Immediately after writing the data to the cell, the local data bus lines LDBi and / LDBi and the global data bus lines GDBi and / GDBi must be reset to the precharge level before the write operation.

The reason is that when the read operation comes in the next cycle, the read data must be loaded on the local data bus lines (LDBi, / LDBi) and the global data bus lines (GDBi, / GDBi), and the data read from the cell is very weak. Because it is a signal.

In the case of the read operation, the column line is enabled and data latched to the sense amplifier of the activated block is loaded on the local data bus lines LDBi and / LDBi, and then read through the global data bus lines GDBi and GDBi. It is input to the amplifier (Read Amp.) And then amplified and sent to the data output buffer.

The reason why the precharge time after the write operation takes a considerable time and the amount of data develop during the read operation is small is that the load of the local data bus line pairs LDBi and / LDBi is very large.

As mentioned above, the write and read operation of the chip is similarly applied to general DRAM and synchronous DRAM. Synchronous DRAM is designed for high speed operation, and the maximum operating frequency is used to perform read operation in the next cycle immediately after the write operation. It is determined in the case of operation.

For example, the global data bus lines (GDBi, / GDBi) are precharged to a power supply potential (actually, the global data bus lines are precharged to Vdd or Vdd / 2) and the local data bus lines (LDBi, / If LDBi is also precharged to the power supply potential by the block selection signal BlkSel of the memory cell array, when entering the write operation in this state, the write driver drives the global data bus line pairs GDBi and / GDBi.

When data of "1" is written to the selected cell, GDB is driven to the power potential and / GDB is driven to the ground potential.

The column line is then enabled to write data to the selected cell and free the global data busline pairs (GDBi, / GDBi) and local data busline pairs (LDBi, / LDBi) with power potential before the next command is entered. Should occupy

Otherwise, if a read command is entered in the next cycle, the data from the cell is read by a global data busline pair (GDBi, / GDBi) or local data busline pair (LDBi), which is spread to the power or ground potential by a write operation. , / LDBi), because the cell data is latched to the sense amplifier by the sensing operation of the bit line sense amplifier during the read operation, and the driving capability of the sense amplifier is weak. Since the development difference between LDBi and / LDBi) is about 300㎷ and there is a time difference to be delivered to the global data busline pair (GDBi, / GDBi) connected by the NMOS transistor, the signal transmitted to the actual lead amplifier is weak. Because it is.

That is, after the write operation, the precharge of the global data bus line pairs GDBi and / GDBi and the local data bus line pairs LDBi and / LDBi should be such that there is little potential difference between the pairs.

If the operating frequency is low, there is no problem because there is enough time to precharge the global data busline pair (GDBi, / GDBi) until the next cycle after the write operation, but the operating frequency is increased to 100 MHz, 133 MHz, and 143 MHz. In the trend of increasing operating frequency, such as 166 MHz, the time to precharge the data busline is gradually decreasing.

In the present invention, as shown in the accompanying drawings, implemented at an operating frequency of 166 MHz, as shown in FIG. The Curl data busline / LDBi is driven to ground potential and the column line is enabled.

In the precharge operation immediately after the write operation, the column line becomes logic low and the local data bus line precharge signal (/ LDBpcg) output from the local data bus line precharge generator 100 is about 2 to logic low from logic high. Enabled during equalization to equalize the pair of local data buslines.

At the same time, the global data busline pairs GDBi and / GDBi are also precharged to the power potential while being equalized by the global data busline precharge signal / GDBpcg generated by the precharge device in the write driver.

Next, before the read operation, the global data busline precharge signal (/ GDBpcg) and the local data busline precharge signal (/ LDBpcg) are logic high disabled and the new column line is enabled so that the read data is local data. It is loaded on bus data pairs (LDBi, / LDBi) and global data bus line pairs (GDBi, / GDBi).

4 shows a global data busline precharge circuit, in which global data busline pairs GDBi and GDBi are formed by PMOS transistor P43 turned on by a low pulse global data busline precharge signal (/ GDBpcg). The equalized and simultaneously turned on PMOS transistors P41 and P42 show that the global data bus line pairs GDBi and / GDBi are precharged to a power supply potential.

As described above, the present invention provides a light operation by separately providing a device capable of precharging a pair of local data bus lines in addition to a precharge device provided in a conventional light driver for smooth precharging of a data bus line after a write operation. Since the precharge operation is smoothly performed before the read command is input, the operating frequency of the DRAM is increased to improve the competitiveness of the product.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1 is a layout view of a data busline precharge device having a memory cell array and a data busline according to the prior art.

2 is a structural diagram of a data busline precharge device having a memory cell array and a data busline according to an exemplary embodiment of the present invention.

3 is an operation timing diagram of FIG. 2.

4 is a typical global data busline precharge circuit diagram.

<Description of the code | symbol about the principal part of drawing>

100: local data bus line precharge generation unit

200: equalize transistor

LDBi, / LDBi: Local Data Busline

GDBi, / GDBi: Global Data Busline

BlkSel: Block Selection Signal

/ LDBpcg: Local Data Busline Precharge Signal

/ GDBpcg: Global Data Busline Precharge Signals

Claims (2)

A plurality of memory cell arrays storing cell data; A bit line sense amplifier configured to sense the cell data; A pair of local data buslines coupled to said bitline sense amplifiers via predetermined means; A read / write operation is performed by a pair of global data bus lines connected to a write driver and a read amplifier and commonly exchange data in a memory cell block, and precharged by a precharge device existing in the write driver during a precharge operation. In a semiconductor memory device, A local data bus line precharge generating means for outputting a local data bus line precharge signal enabled to a logic low after a predetermined time delay of the column address in the precharge operation; And coupling means for equalizing the pair of local data bus lines before the read command is input by operating while the local data bus line precharge signal has a logic low level during the precharge operation. Busline precharge device. 2. The data bus line of claim 1, wherein the connection means comprises a PMOS transistor connected between the pair of local data bus lines to which the local data bus line precharge signal is applied through a gate terminal. Precharge device.