JPH11249958A - Memory control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory control system which improves the processing efficiency of a CPU by reducing the number of times of access of the CPU in writing a data string larger than the bus width of the CPU in a memory. SOLUTION: A memory 22 used in a CPU 21 whose bus width is n bits includes plural n-bit registers 27, plural m-bit (m>n) registers 29 corresponding to these registers 27, respectively, a shared register 24 where a data part common to plural data strings is written, and a control circuit 23 which writes data transferred from the CPU 21 in registers 27 in response to a data write command to registers 27 from the CPU 21 and writes data in registers 29 corresponding to registers 27 together with the data part written in the shared data register 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control system which is advantageous when a data string larger than the bus width of a CPU is handled.
The present invention relates to a memory control system which is convenient if it is used when a GB image data string is handled by a CPU having a bus width of 16 bits.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram schematically showing a main part of a conventional memory control system. In the figure, reference numeral 2 denotes a memory. The memory 2 is a data storage area composed of a plurality of n-bit registers 5, that is, a register group 4, data writing to the register group 4, and data from the register group 4. And a control circuit 3 for controlling the reading of the data. The control circuit 3 is connected to a register group 4 via a control bus 10.

The CPU 1 having a bus width of n bits is:
An address bus 6 for designating an address (hereinafter also referred to as an address) of the register 5, a control bus 7 for transmitting a WR (write) signal, and a control bus 8 for transmitting an RD (read) signal. The CPU 1 and the register group 4 are connected via a data bus 9 to the control circuit 3.

Next, a case where the CPU 1 writes data in the memory 2 will be described. First, the CPU 1 outputs to the address bus 6 an address designating which address of the register 5 to write data to, and also outputs data to be written to the data bus 9. Then, the CPU 1 sets the WR
By outputting the signal, data can be written to a target memory address.

Next, the case where the CPU 1 reads data from the memory 2 will be described. First, from CPU1,
An address designating the address of the register 5 from which the data is to be read is output to the address bus 6 and the RD signal is output, so that the data can be read from the target memory address. In the memory 2, the control circuit 3 controls writing and reading based on a signal from the CPU 1.

[0006]

The processing of the CPU 1 when writing a data string larger than the bus width of the CPU 1 to the memory 2 using the above-mentioned conventional memory control system will be described. Here, a case will be described where the bus width of the CPU 1 and the data width of the register 5 are 16 bits, and an 18-bit RGB image data string is written in the memory 2 as a data string larger than the bus width of the CPU 1. The RGB image data string includes R (red) information, G
Each of the (green) information and the B (blue) information is composed of 6 bits.

FIG. 8 shows 5 (= N) image data strings 11
a to 11e, and FIG. 9 shows these image data strings 11a.
11e are the addresses A _{0 of the} register group 4 (register 5)
Shows a state in which written in to A _9. FIG.
Are processes 1 to 10 when the image data strings 11a to 11e are written to the memory 2, and show the addresses output by the CPU 1 to the address bus 6 and the data output to the data bus 9.

As is apparent from FIG. 10, since the image data strings 11a to 11e are larger than the bus width of the CPU 1,
The CPU 1 needs to access (process) the memory 2 twice, and has 5 (= N) image data strings 11a to 11e.
To write everything in the memory 2, the image data sequence 11
10 (= N × 2) accesses corresponding to twice the number of a to 11e are required. Here, for the sake of simplicity, the case where the number of image data strings is five is described. However, in practice, the number of the image data strings is very large, and the number of accesses is twice or three times the number. As a result, the processing efficiency of the CPU 1 is significantly reduced.

Further, as is apparent from FIG.
When reading a data string of 18 bits from the CPU 1, the CPU 1 first reads data of 16 bits and then data of 2 bits.
Must be taken in, and data manipulation must be performed in the CPU 1 while being aware of data breaks.
The processing efficiency of U1 was reduced. As will be described later in detail, in the present invention, for example, CPU (CPU) by reading data of 12 bits (R information, G information) first, and then reading data of 6 bits (B information) To prevent the processing efficiency from being lowered.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and reduces the number of accesses by a CPU when writing a data string larger than the bus width of the CPU to a memory.
It is an object of the present invention to provide a memory control system capable of improving the processing efficiency of the above and a memory control system capable of reading a data string from a memory with good separation.

[0011]

Means for Solving the Problems and Effects The present inventor has proposed the above-mentioned object by utilizing common data between a plurality of data strings as common data of the respective data strings. Can be achieved.

Generally, in an image data sequence, data rarely changes greatly for each data sequence, and data of a similar pattern is formed to some extent.
For example, an RGB image data string 11a as shown in FIG.
In the case of .about.11e, since data common to the image data strings 11a to 11e exists, for example, data of upper two bits can be used as common data. By using the upper two bits of data as the common data, the remaining lower data can be transferred to a 16-bit bus having a bus width of 16 bits.
The processing can be performed at once by the PU.

That is, a memory control system (1) according to the present invention comprises a CPU having a bus width of n bits,
A memory control system comprising: a memory means used for a U-type memory;
And a plurality of m (> n) -bit second registers respectively corresponding to the plurality of first registers;
A shared register in which data common to a plurality of data strings is written; and a data write command to the first register is issued by the CPU to write data transferred from the CPU to the first register; And a first control unit that controls so that the combined data of the data and the data written in the shared register is written in the second register corresponding to the first register. It is characterized by being constituted.

According to the memory control system (1),
Q common to a plurality of p (m ≧ p> n) bit data strings
(N ≧ q ≧ p−n) bits of data, that is, common data is written in the common register, and the remaining data of r (= p−q) bits excluding the common data from the data string is written. By writing to the first register, data combining the common data and the remaining data, that is, the data string can be written to the second register.

For example, the bus width of the CPU, the first register, and the second register are 16 bits, 16 bits, and 18 bits, respectively, and are 5 (= N) as shown in FIG. Image data strings 11a to 11e of books
Is written in the memory means, the upper two bits of data [10] used as common data are written in the shared register, and the remaining lower 16 bits of data [0111010011001101] or [0100010100001101] are written in the first register. 1 by writing to the first register, the data [10011101] combining the common data and the remaining data.
[0011001101] or [100100010100001101], that is, the image data strings 11a and 11b can be written in the second register.

Therefore, conventionally, in order to write 5 (= N) image data strings 11a to 11e into the memory, 10 (N × 2) accesses corresponding to twice the number of data strings are required. However, by employing the memory control system (1), the number of accesses can be reduced to 6 (N + 1) times, and the processing efficiency of the CPU can be improved.

Further, the memory control system (2) according to the present invention comprises a CPU having a bus width of n bits,
A memory control system comprising: a plurality of n-bit first registers; and a plurality of m (> n) bits corresponding to the plurality of first registers, respectively. A second register, a switching register in which a value written by the CPU is changed, and a data read command from the first register, which corresponds to the first register. And second control means for controlling the data written in the second register to be selected and written to the first register in accordance with the value of the switching register. Features.

According to the memory control system (2),
By changing the value written to the switching register, the data written to the second register can be selected and written to the first register.

For example, the bus width of the CPU, the first register, and the second register are each composed of 16 bits, 16 bits, and 18 bits, and
Of the image data string 11a as shown in FIG.
When [100111010011001101] is written, if the value of the switching register is “0”, the upper 12 bits [10
0111010011] (R information [100111], G information [010011])
Is selected and written to the first register, while
If the value of the switching register is "1", the lower 6 bits [001101] (B information) are selected and written to the first register. Therefore, it is possible to read out the R information, the G information, and the B information from the memory means with good separation, thereby improving the processing efficiency of the CPU.

Further, in the memory control system (3) according to the present invention, in the memory control system (1), the memory means may include: a switching register for changing a value written by the CPU; When a data read command from the first register is issued by the CPU, the data written in the second register corresponding to the first register is selected according to the value of the switching register to select the data. And second control means for controlling writing to one register.

According to the memory control system (3),
The number of accesses by the CPU when writing a data string larger than the bus width of the CPU to the memory can be greatly reduced, and the data string written to the memory can be read with good separation. The processing efficiency of the CPU can be greatly improved.

[0022]

Embodiments of a memory control system according to the present invention will be described below with reference to the drawings. FIG.
FIG. 1 is a block diagram schematically showing a main part of a memory control system (1) according to an embodiment. In the figure, reference numeral 22 denotes a memory. The memory 22 includes a data storage area composed of a plurality of n-bit registers 27, that is, a register group 26, and a plurality of m (> n) -bit registers 29. And a control circuit 23 that controls writing of data to the register groups 26 and 28 and reading of data from the register groups 6 and 28. The control circuit 23 is connected to a control bus 37 via a control bus 37. Connected to the register groups 26 and 28.

Further, the memory 22 includes a shared register 24 in which data common to a plurality of data strings, that is, common data is written, and a switching register 25 in which a value written by the CPU 21 is changed. ing. The shared register 24 is connected to the register groups 26 and 28 via a data bus 35, and the control circuit 23 is connected to the shared register 24 via a control bus 36. Further, the control circuit 23 is connected to the switching register 25 via the control bus 38, and can take in the value written in the switching register 25.

CPU 21 having a bus width of n bits
Are an address bus 30 for designating the address of the register 27 and a control bus 31 for sending a WR (write) signal.
And a control bus 32 for transmitting an RD (read) signal to the control circuit 23. Further, the CPU 21 is connected to the switching register 25 via the control bus 33, and sets 0 or 1 to the switching register 25. You can write to it. The CPU 21, the register group 26, and the shared register 24 are connected via a data bus 34.

The register group 26 is composed of n-bit registers 27 indicated by addresses A ₀ (not shown) to A _M , B _{0 to} B _N , C ₀ , C ₁ , C ₂ ,.
8 is an m-bit register 2 indicated by addresses D _{0 to} D _N
9. The register 29 indicated by the addresses D _{0 to} D _N (corresponds to the second register of the present invention)
Corresponds to each of the registers 27 (corresponding to the first register of the present invention) indicated by the addresses B _{0 to} B _N.

Next, a case where the CPU 21 writes data in the memory 22 will be described. First, the CPU 21, the address specifying whether writing where data to the address of the register _{27 (A 0 ~A M, B} 0 ~B N, C 0, C 1, C 2, ...), or the shared register 24 The designated address (E) is output to the address bus 30, and the data to be written is output to the data bus 34. Then, when the CPU 21 outputs the WR signal, data can be written to a target memory address.

The operation of the control circuit 23 in the memory 22 at this time will be described with reference to the flowchart shown in FIG. However, here, the CPU is already stored in the shared register 24.
It is assumed that desired common data D _C has been written in accordance with the command from 21.

First, in step 1, the address K output from the CPU 21 is fetched, and then in step 2, the data D output from the CPU 21 is
Then, control is performed so that the data is written to the register 27 or the shared register 24, and the process proceeds to step 3.

In step 3, address K is changed to address B
₀ .about.B _N determines whether either. If the address K is either the address B ₀ .about.B _N, it proceeds to Step 4, whereas, the address K unless any of the addresses B ₀ .about.B _N, terminating the operation.

[0030] In step 4, the data D and that of the combination of the common data D _C and the data D written in the shared register 24 'and then proceeds to step 5, data D'
27 (addresses B _{0 to} B
_N ) to control writing to the register 29 (addresses D _{0 to} D _N ).

Although the processing in step 3 is performed after the processing in step 2 here, this is for the sake of simplicity. It is more practical to perform the processing in step 3 after the processing in step 1. Needless to say, there is.

That is, if the memory control system (1) according to the above embodiment is adopted, a plurality of p (m ≧ p> n)
The q (n ≧ q ≧ pn) bits of data (common data D _C ) common to the bit data string are written in the common register 24, and the remaining data obtained by removing the common data D _C from the data string is written. by writing r (= p-q) data D of the bit to register 27 the address B ₀ ~B _N, common data D _C and the remaining data of the combination of the data D D ', i.e. the data sequence register 29.

Using the memory control system (1),
A data string larger than the bus width of the CPU 21 is stored in the memory 22.
The processing of the CPU 21 when writing to the. Here, a case will be described in which the bus width of the CPU 21 and the data width of the register 27 are 16 bits, and an 18-bit RGB image data string is written in the memory 22 as a data string larger than the bus width of the CPU 21. It is assumed that the register 29 has a data width of 18 bits equivalent to the RGB image data string.

FIG. 3 shows processes 1 to 6 for writing the RGB image data strings 11a to 11e shown in FIG.
And the address output from the CPU 21 to the address bus 30 and the data output from the data bus 34. FIG. 4 is a schematic diagram showing a state in which the image data strings 11a to 11e are written in the register group 28.

As is apparent from FIG. 3, by writing the upper two bits of data [10] as common data in the shared register 24 in advance, the CPU 21 writes only the remaining lower 16 bits of data. You just need to do the processing. Therefore, in order to write all the 5 (= N) image data strings 11a to 11e into the memory 22, one is added to the number of the image data strings 11a to 11e.
(N + 1) accesses are sufficient. here,
For ease of explanation, the case where the number of image data strings is five is described, but in actuality the number is very large,
The processing efficiency of the CPU 1 is greatly improved because the number of accesses is simply obtained by adding 1 to the number of accesses.

Subsequently, the CPU 21 stores the data in the memory 22.
The case where data is read from the memory will be described. First, the CPU 21
From address specified whether read data from the register 27 of anywhere address _{(A 0 ~A M, B 0} ~B N, C 0, C 1, C 2, ...)
Is output. Then, by outputting an RD signal from the CPU 21, data can be read from the target memory address.

The operation of the control circuit 23 in the memory 22 at this time will be described with reference to the flowchart shown in FIG. First, in step 11, takes in the address K output from the CPU 21, then at step 12, captured address K is equal to or either address B ₀ ~B _N. If the address K is either the address B ₀ .about.B _N, proceeds to step 13,
On the other hand, if the address K is not any of the addresses B _{0 to} B _N , the process proceeds to step S17.

In step 13, the value f (0 or 1) written in the switching register 25 is fetched, and in step 14, the fetched value f is set to 0 and 1
Is determined. If the value f is 0, the process proceeds to step 15 where the upper 12 bits of the data written in the registers 29 of the addresses D _{0 to} D _N corresponding to the registers 27 of the addresses K (B _{0 to} B _N ) are obtained. Is written to the register 27 at the address K, and the process proceeds to step 17. On the other hand, if the value f is 1, the process proceeds to step 16 where the lower 6 bits among the data written in the registers 29 of the addresses D _{0 to} D _N corresponding to the registers 27 of the addresses K (B _{0 to} B _N ). Control is performed so that the data for the bits is written to the register 27 at the address K, and the process proceeds to step 17. In step 17, the data written in the register 27 at the address K is
Control is performed so that 1 can be captured.

That is, if the memory control system (1) according to the above embodiment is adopted, the data written in the register 29 is changed by changing the value f (0 or 1) written in the switching register 25. The selected data is written into the register 27.

Using the memory control system (1),
A data string larger than the bus width of the CPU 21 is stored in the memory 22.
The processing of the CPU 21 when reading from the (register group 28) will be described. However, here, the bus width of the CPU 21 and the data width of the register 27 are 16 bits,
A case where an 18-bit RGB image data string is read from the register group 28 as a data string larger than the bus width of the CPU 21 will be described. The register 29 is RGB
It is assumed that it is configured with a data width of 18 bits equivalent to the image data sequence.

[0041] FIG. 6 shows a process X _a to X _e, and processing Y _a to Y _e when reading image data stream 11a~11e written in the register group 28 shown in FIG. 4 CPU 21 is, processing X _a to X _e, a case where the processing Y _a to Y _e is a value f which is respectively written into the switching register 25 is 0, 1.

As is apparent from FIG. 6, the switching register 2
If the value f of 5 is 0, the upper 12 bits (R information, G information) are selected and written into the register 27, while if the value of the switching register 25 is 1, the lower 6 bits (B information)
Is written in the register 27. The data written in the register 27 is transferred to the CPU 21.
Can be read.

Therefore, R information, G information,
And the RGB image data string composed of the B information can be read with good separation, and the processing efficiency of the CPU 21 can be greatly improved.

Although only the case where the 18-bit RGB image data string is read after being divided into upper 12 bits and lower 6 bits has been described, it goes without saying that the present invention is not limited to the above case. No.

In FIG. 1, the register group 26, the common register 24, and the switching register 25 are shown as physically different from each other. For example, any one of the registers 27 other than the addresses B _{0 to} B _{N is used.} One or two bits can be used as the shared register 24, and similarly, one bit can be used as the switching register 25.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a main part of a memory control system (1) according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of a control circuit when writing data to a memory.

FIG. 3 shows a process for writing an RGB image data string into a memory.

FIG. 4 is a schematic diagram showing a state in which an RGB image data string is written into a register.

FIG. 5 is a flowchart showing an operation of a control circuit when reading data from a memory.

FIG. 6 shows a process for reading an RGB image data string from a memory.

FIG. 7 is a block diagram schematically showing a main part of a conventional memory control system.

FIG. 8 is a schematic diagram showing an RGB image data sequence.

FIG. 9 is a schematic diagram showing a state in which an RGB image data string is written in a register.

FIG. 10 shows a process for writing an RGB image data string into a memory.

[Explanation of symbols]

1,21 CPU 2,22 memory 3,23 control circuit 4,26,28 register group 5,27,29 register 6,30 address bus 7,8,10,31,32,33,36,37,38
Control bus 9, 34, 35 Data bus 24 Shared register 25 Switching register

Claims (3)

[Claims] A CPU having a bus width of n bits;
A memory control system comprising a memory means used for a PU, wherein the memory means comprises: a plurality of n-bit first registers; and a plurality of m (> n) corresponding to each of the plurality of first registers. A second register of bits, a shared register in which data common to a plurality of data strings is written, and a command to write data to the first register is transmitted by the CP.
U, the data transferred from the CPU is written into the first register, and then the data obtained by combining the data and the data written in the shared register is written into the first register. A first control means for controlling writing to the corresponding second register. 2. A CPU having a bus width of n bits;
A memory control system comprising a memory means used for a PU, wherein the memory means comprises: a plurality of n-bit first registers; and a plurality of m (> n) corresponding to each of the plurality of first registers. A second register of bits, a switching register for changing a value written by the CPU, and a command to read data from the first register.
When the PU performs the control, data written in the second register corresponding to the first register is controlled in accordance with the value of the switching register to select and write the data to the first register. 2. A memory control system, comprising: a second control unit. 3. The memory device according to claim 2, wherein: a switching register for changing a value written by the CPU; and a command to read data from the first register.
When the PU performs the control, data written in the second register corresponding to the first register is controlled in accordance with the value of the switching register to select and write the data to the first register. 2. The memory control system according to claim 1, wherein said memory control system includes two control means.