JPS59132479A - Data processing circuit - Google Patents

Abstract

PURPOSE:To attain high speed processing in the unit of bits in forming a picture memory data by extracting a word data by a multiplexer output to obtain a shift data. CONSTITUTION:The 1st byte data in 2-byte data incoming continuously is set to a data register 13 and the 2nd byte data incoming next is set to data registers 11, 12. It is required to set data to the data register 11 so that it is set in the timing next to the data set to the data register 13 via a control line 102. Thus, the consecutive 2-byte data are arranged in the data registers 13, 12 respectively, then a consecutive 8-bit data in the 2bytes (16 bits) is outputted selectively by a selecting circuit 14. The selecting condition is set by the output of a shift control register 15 and data shift in 1-8-bit is executed between the 1st and the 2nd byte.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data processing circuit that performs data kREAD/WRITE across a plurality of addresses in a word-structured storage device.

[Technical background of the invention and its problems]

Normally, reading/reading data to an image storage device (a system that handles data in bits on word-structured memory)
WRITE is performed in word units. When writing data of one byte to an arbitrary storage location in the image storage device, for example, when writing one byte of data across two addresses, a predetermined amount of shift operation is required. This shift operation has conventionally been performed using the shift function (
Both ministries) were used for processing. Therefore, there was a problem with processing speed, making it unsuitable for systems aiming for high speed.

[Object of the Invention] □ The present invention has been made in view of the above-mentioned drawbacks, and provides a data processing circuit that generates image storage data at high speed by processing the above-mentioned shift operation using 8-doware logic. The purpose is to provide

[Summary of the invention]

The present invention provides a data processing circuit that performs a predetermined bit shift when reading/writing one word data across two addresses in a system that handles data in bit units on an image storage device configured in word units. This is what we provide. For this reason, the data processing circuit has, for example, two data registers in which the second byte data of consecutive two byte data is set, one data register in which the first byte data is set, and both registers. A selection circuit (consisting of a group of multiplexers and a shift control register in which the amount of data to be shifted is set) inputs consecutive 2-byte data set to , and selects and outputs consecutive 8-bit data t by the shift control register output. .

Word data is extracted from the multiplexer output to obtain shift data.

Due to this, when creating image memory data,
Bit-by-bit processing can be performed at high speed.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 11, 12, and 13 are set in data registers. Data registers 11 and 12 have 8-bit data lines 10
The second byte of the two-byte data successively arriving via the 2-byte data is set, and the first byte data is set in the data register 13.

The 1-byte data set in the data register 13 and the 1-byte data set in the data register 12 constitute continuous 2-byte data. A control line 103 is a signal line that instructs to latch the data propagated on the data lines 101 and 102f to each of the registers 11 and 12-IJ.

L is a selection circuit. The selection circuit 14 is composed of eight multiplexers 141-142, 143, . A total of 8 bits, including the 6th bit to 0th bit output of the data register 2/13 and the 7th bit output of the data register 12, are supplied to the multiplexer 141 constituting the selection circuit 14 as input.

In addition, the multiplexer 142 has 5 of the data registers 13.
Bit to 0th bit output and data register 12
A total of 8 bits of the 7th and 6th bit outputs are further sent to the multiplexer 143 from the 4th bit to O
A total of 8 bits, including the bit output and the 7th to 5th bits of the data register 12, are supplied as respective inputs.

Although not shown below, multiplexers 144 and 14
5, 146, and 147 are supplied with the above-mentioned combination of 8-pin data sequentially shifted by 1 bit as input, and the multiplexer 148 is supplied with all bits output (7 to 0) of the data register 12 as input data. .

The output of the multiplexer 141 is bit 7, the output of the multiplexer 142 is bit 6, the output of the multiplexer 143 is bit 5...the output of the multiplexer 148 is bit 0.
The data is taken out as 1-byte data via the data line 106f.

15 is a shift control register.

Data line 10 to shift control register 15
7, and 3-bit information propagated on the data line 107 is set in accordance with a signal arriving via the control line 10g. The output of this shift control register 15 becomes a selection condition input signal (S) via a line 109 to each multiplexer 141 to 148 constituting the selection circuit ±1. FIG. 2 conceptually shows the relationship between the value set in the shift control register 15 and the shift amount.

FIG. 3 is a conceptual diagram showing the operation of the embodiment of the present invention developed on a memory map.

Hereinafter, the operation of the present invention will be explained in detail.

First, the first byte of two consecutively arriving two-byte data is set in the data register 13, and then the next second byte of data is set in the data register 11/I2. Incidentally, it is necessary to control the data setting to the data register 11 via the control line 102f so that it is performed at the next timing after the data is set to the data register 13. This timing control can be handled by a conventionally known method and is not the subject matter of the present invention, so a description thereof will be omitted here.

As a result, the consecutive 2 bytes of data are arranged in the data registers 13 and 12, respectively, and the selection circuit 14 selects the consecutive 8 bytes of the 2 bytes (16 bits).
Bit data is selectively output. As mentioned above, the selection conditions are set by the output of the shift control register 15, and according to the example shown in FIG. executed.

The applied operation will be explained using the memory map shown in FIG. Byte areas 1 to 11 contain data bytes
Phase] (Same for ■ to ■) When starting yklf, the ``5-bit shift'' shown in FIG. 2 is used. Here, the $1 byte is set to ■, the second byte is set to ■, these are shifted by 5 bits, 1 byte data is taken out, and written to byte area 2. Next, ``■'' is set as the first byte and ``■'' is set as the third byte, which are shifted by 5 bits to take out 1-byte data and written into byte area 3.

In this way, each time new data is sent to the data registers 11 and 12, a predetermined shift (in this example, 5
Bit shift) f: Execute in 1 step. For byte areas 2 to 10, data is continuously shifted and scanned in the same manner as described above.

Note that although the above operation has been described only regarding writing, reading can also be executed in a similar manner. Further, the logic of the present invention cannot be used only in byte area 1 and byte area 11. It is necessary to perform edge data bit processing by a microprogram only for this area. Since this process is outside the scope of the present invention, a description thereof will be omitted.

〔Effect of the invention〕

As explained above, according to the present invention, when creating screen memory data, bit-by-bit processing can be performed at high speed, and continuous screen memory data can be created at high speed using a simple control method. .

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a conceptual diagram of a shift operation showing the relationship between the value set in the shift control register and the shift amount, and Fig. 3 is a memory map diagram showing the operation of the embodiment of the present invention. It is a conceptual diagram of the operation expanded and shown above. 11-12, 13... mock data register, 14... selection circuit, 15... shift control register, 14
1 to 148...Multiplexer.

Claims (1)

[Claims] In a system that handles bit-by-bit data on a word-structured storage device, a data processing circuit reads/writes data across multiple addresses to the storage device, and the data processing circuit is configured to read/write data across multiple addresses to the storage device. A plurality of data registers, each set in word units, and continuous plural word data set in these data registers are input, and continuous bit data (one word) is input by a selection condition input signal obtained via a shift control register. It consists of a selection circuit that selects and outputs the data (constituting the above), and a shift control register to which the amount of shift data is set externally and generates selection conditions for the selection circuit based on this value. A data processing circuit characterized in that word data to be read/written is taken out and read/written sequentially.