JP2002215563A - Dma controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DMA controller which is small in circuit scale and easily makes data transfer fast. SOLUTION: In a transfer-source device 20, a master read control part 11 inputs pieces of data stored in successive addresses areas following a 1st address at a burst and the data are stored in a buffer memory 13. The data stored in the buffer memory 13 are read by a buffer control part 12 in order according to the 1st address value of the transfer-source device 20 and the 2nd address value of a transfer-destination device 30, and a master write control part 14 outputs them at a burst to the successive address areas of the transfer- destination device 30 following the 2nd address value. When the 1st address value and 2nd address value are different, a buffer control part 12 rearranges the data according to the 1st address value and 2nd address value after they are read out of the buffer memory 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DM for controlling the transfer of data from a source input / output device to a destination input / output device.
It relates to the A control device.

[0002]

2. Description of the Related Art Generally, an information processing system is composed of a plurality of devices. Data is transferred between each device, and a target process is performed while performing the data transfer. For example, considering a printer control system as an example of an information processing system, this system has a CPU (Central Processing Uniform) that performs various controls and calculations.
t), a hard disk for storing image data to be printed, a compressor for compressing image data, a system memory for temporarily storing image data, etc., a printer engine for printing an image on paper based on image data, etc. And transfers image data between these devices.

There is a demand for faster processing in such an information processing system, and in particular, a faster data transfer between devices. DMA (Direct Memory Ac) is a technology to speed up data transfer between devices.
cess) Transfer techniques are known. DMA transfer technology uses C
This is to transfer the data of the transfer source device to the transfer destination device without passing through the PU. Further, by reading a data string stored at each successive address of the transfer source device and writing a data string to each successive address of the transfer destination device in a burst cycle, data between the devices can be obtained. Transfer speed is improved.

For example, Japanese Patent Laying-Open No. 10-254817 discloses a DMA transfer control system for performing DMA transfer of data of a transfer source device to a transfer destination device in a burst cycle. In particular, this publication discloses that a first address value of an address area storing a data string to be read in a transfer source device is a first address value, and a first address value of an address area to which a data string is to be written in a transfer destination device is a second address value. A technique (data rearranging technique) of a DMA transfer by a burst cycle when the first address value differs from the second address value when the address value is used is disclosed. Here, the difference between the first address value and the second address value means a difference based on the bit width of the data bus. For example, if the data bus is 32 bits (4 bytes), the lower two bits are compared between the first address value and the second address value to determine whether there is a difference.

FIG. 9 shows a conventional DM disclosed in the above publication.
FIG. 3 is a schematic configuration diagram of a data rearranging unit in the A control device. This DMA control device rearranges 32 bits (4 bytes) of data input from a transfer source device.
4 multiplexer MUX1, this multiplexer MU
An 8-bit flip-flop FF _mn (m = 1 to M, N = 1 to 8) holding data rearranged by X1
4) and a 4-to-4 multiplexer MUX2 for rearranging the 4-byte data output from any four of the flip-flops FF and outputting the rearranged data to the transfer destination device. Although not shown, the DMA control device includes a circuit for selecting a flip-flop FF to store the 4-byte data output from the multiplexer MUX1 at the preceding stage, and
There is also provided a circuit for selecting a flip-flop FF for outputting 4-byte data to be input to the multiplexer MUX2 at the subsequent stage.

[0006] Under the control of these selection circuits, this conventional DMA controller operates, for example, as follows. Here, the lower two bits of the first address value (first address value) of the address area storing the data sequence to be read in the transfer source device are set to “01”. The lower two bits of the first address value (second address value) of the address area where the data string is to be written in the transfer destination device are set to “11”.

At this time, first, 3
The first to third bytes of data are sent from the transfer source device to the DMA controller, and the multiplexer MUX in the preceding stage is sent.
1 by sorted, the first data of which is stored in the flip-flop FF _11, the second data is stored in the flip-flop FF _12, are stored third data to the flip-flop FF _13. Subsequently, stores 4 bytes of the fourth to seventh data is sent from the transfer source device to the DMA controller, sorted by the preceding stage of the multiplexer MUX1, the fourth data of which the flip-flop FF ₁₄ is, the fifth data is stored in the flip-flop FF _21, the data of the sixth is stored in the flip-flop FF _22, the seventh data flip-flop F of the
It is stored in the F _23. The same applies to the following.

On the other hand, the data stored in each flip-flop is sent to the transfer destination device as follows. That is, in the beginning, the first one byte of data from the second address value (data stored in the flip-flop FF ₁₁₎ are sorted by subsequent multiplexer MUX2, sent to the transfer destination device. continue,
Four bytes of second to fifth data (flip-flop F
F ₁₂ to ff ₁₄ and FF ₂₁ data that was stored in, respectively), sorted by subsequent multiplexer MUX2, sent to the transfer destination device. Further on,
Sixth to ninth data of four bytes (flip-flop F
F ₂₂ to ff ₂₄ and FF ₃₁ data that was stored in, respectively), sorted by subsequent multiplexer MUX2, sent to the transfer destination device. The same applies to the following.

[0009]

In the above-mentioned conventional DMA controller, it is necessary to provide, in addition to the two 4-to-4 multiplexers and a large number of flip-flops, a selection circuit for selecting a flip-flop from which data is written or from which data is read. As a result, the circuit scale becomes large and expensive. In addition, this DMA control device has an increased latency, and it is difficult to speed up data transfer.

In addition, since data must be written from a fixed position at the time of writing, data is always rearranged into one DMA block. Even if the number of FFs for holding data is increased, writing of the next DMA block cannot be performed until all readings have been completed, so that the FFs actually used are limited and wasted.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a DMA controller which has a small circuit scale and facilitates high-speed data transfer.

[0012]

SUMMARY OF THE INVENTION A DMA control device according to the present invention is a direct access (DMA) device for controlling data transfer between input / output devices connected to a single or independent bus without using a CPU. (1) data input means for performing control to read block data specified by a start address (address 1) and a size from a transfer source input / output device and to take in block data by one or more accesses; (2) temporary storage means for temporarily holding data fetched by the data input means; and (3) temporary storage of block data specified by a start address (address 2) and a size in a transfer destination input / output device. Data output means for performing control to read from the means and output the data in one or more accesses; and (4) the address value of the source input / output device and the address value of the destination input / output device. Buffer control means for sequentially reading data to be output by the data output means from the temporary storage means and sending the data to the data output means based on the data.

According to this DMA control device, each data stored in a continuous address area after the start address value in the transfer source input / output device is input by the data input means and stored in the temporary storage means. Each data stored in the temporary storage means is sequentially read out by the buffer control means based on the start address value in the transfer source input / output device and the start address value in the transfer destination input / output device, and is read out to the data output means. The data is output by the data output means to a continuous address area after the start address value in the transfer destination input / output device. If the addresses of the transfer source and the transfer destination are different, it is necessary to rearrange the data.
In the A control device, the buffer control unit reads the data from the temporary storage unit based on the two address values, and at the same time, rearranges the data.

Further, in the DMA control device according to the present invention,
It is preferable that the temporary storage means includes a plurality of unit buffers and sequentially handles two or more DMA blocks having different address differences. The unit buffer includes data to be transferred and attribute information, and the attribute information is stored in the unit buffer with an address having a sufficient number of bits to represent the number of bytes of the unit buffer among the start addresses of the transfer source. Preferably, it has a valid number of bytes, a start block bit indicating the start of the block, and an end address bit indicating the end of the block.

Further, in the DMA control device according to the present invention,
The address used for reading the temporary storage means is generated by converting an address to be output to the destination input / output device based on a difference between the address value of the source input / output device and the address value of the destination input / output device. Is preferred. The temporary storage means preferably includes n RAMs of the same number as the data width n of the transfer destination or transfer source. The temporary storage means stores the n bytes into two areas according to the shift amount calculated from the difference between the start addresses of the transfer source and the transfer destination when reading from the data output means for each of the n RAMs. It is preferable to give the converted address or an address obtained by subtracting 1 from the converted address. When the cycle is interrupted due to the transfer destination, it is preferable to use the shift amount and the difference address from the start address for the transfer destination to perform the address conversion for the temporary storage unit after the restart.

[0016]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.

FIG. 1 is a block diagram showing a configuration of a DMA control device 10 according to the present embodiment. In this figure, DM
In addition to the A control device 10, a transfer source device 20, a transfer destination device 30, and a CPU 40 are also shown. The DMA controller 10 communicates with the transfer source device 2 via the first bus 50.
0, is connected to the transfer destination device 30 via the second bus 60, and is connected to the C
It is connected to PU40. First bus 50, second bus 6
0 and the CPU bus 70 each include an address line for transmitting an address signal, a data line for transmitting a data signal, and a control signal line for transmitting various control signals. DMA controller 1
0 is the master read control unit 11, the buffer control unit 12,
It includes a buffer memory 13, a master write control unit 14, a register 15, and a register control unit 16.

The master read control unit 11 itself becomes a master and outputs a bus use request signal indicating that a request to acquire the right to use the first bus 50 is issued, indicating that the use of the first bus 50 has been permitted. Is input. After that, the master read control unit 11 determines the first address value (first address value) of the address area where the data sequence to be read in the transfer source device 20 is stored, and the size of the data to be read, on the first bus 50. Through
It transmits to the transfer source device 20 which is the target. Then, a master read control unit (data input means) 1
1 represents each data stored in a continuous address area after the first address value in the transfer source device 20,
A burst is input via the first bus 50 and sent to the buffer control unit 12.

The buffer control unit 12 stores the data sent from the master read control unit 11 in the buffer memory 13, reads the data stored in the buffer memory 13 and sends the data to the master write control unit 14.
Data is written to or read from the buffer memory 13 by the buffer control unit 12. The details of the buffer control unit 12 and the buffer memory 13 will be described later.

The master write control unit 14 itself becomes a master and outputs a bus use request signal indicating a request to acquire the right to use the second bus 60, indicating that the use of the second bus 60 has been permitted. Is input. After that, the master write control unit 14 determines, via the second bus 60, the start address value (second address value) of the address area where the data string is to be written in the transfer destination device 30 and the size of the data to be written. It transmits to the transfer destination device 30 which is the target. Then, the master write control unit (data output unit) 14 transfers each data stored in the buffer memory 13 to the continuous address area after the second address value in the transfer destination device 30 via the second bus 60. Output burst.

The register 15 stores the first address value, the second address value, and the data size described above. Each of the master read control unit 11, the buffer control unit 12, and the master write control unit 14 operates based on the parameters stored in the register 15. The register control unit 16 controls the CPU 4 via the CPU bus 70.
It is connected to 0 and receives the first address value, the second address value and the data size from the CPU 30 and stores them in the register 15.

FIG. 2 is a diagram showing a configuration of the buffer memory 13 of the DMA control device 10 according to the present embodiment. Buffer memory 13 includes eight blocks. Each block stores a data string burst-inputted from the transfer source device 20 and stored, and a head address value and a data size of the data string. FIG. 3 is a diagram illustrating a configuration of a data storage unit in each block of the buffer memory 13 of the DMA control device 10 according to the present embodiment. The data storage unit in each block is an 8-bit RA
M are arranged.

In the following, the first bus 50 and the second bus 6
0 each 32 data lines (4 bytes) DATA 0-31
It is assumed that Source device 20 in one burst
It is assumed that the maximum size of data that can be transferred to the DMA controller 10 is 256 bytes, and the size of an area for storing a data string in each block is 256 bytes.
At this time, as shown in FIG. 3, the data storage unit in each block is composed of 4 × 64 8 bit RAMs each.
_{m, n} (m = 1 to 64, N = 1 to 4) are arranged.

The first address value is 10 in hexadecimal notation.
001h, and the size of all data to be read from the transfer source device 20 is 1024 bytes. In the transfer source device 20, the first address value "10001"
h "subsequent to consecutive address area 1024 bytes of data stored in the order represented as D ₀ to D _1023.

At this time, in the first block, as shown in FIG.
The first address corresponding to the first burst transfer
The first address value "10001h" is stored as the value,
“255” is stored as the data size, and the data string
And D₀~ D₂₅₄Is stored. In this burst transfer,
First 3 bytes of data D₀~ D_TwoIs the DMA controller 10
To the data D as shown in FIG.₀Is R
AM_1,2And the data D₁Is RAM_1,3Stored in
And data D_TwoIs RAM_1,4Is stored in Then 4 buy
Data D_Three~ D₆Is transferred to the DMA controller 10
Come, data D_ThreeIs RAM_2,1And the data D_FourBut
RAM_2,2And the data D_FiveIs RAM_{2, Three}Stored in
And data D₆Is RAM_2,4Is stored in And so on
Each data is stored in each RAM, and the data D₂₅₁
Is RAM_64,1And the data D₂₅₂Is RAM_64,2To
Stored and data D₂₅₃Is RAM_64,3Stored in the
TA D₂₅₄Is RAM_64,4Is stored in

In the second block, as shown in FIG.
As the first address value corresponding to the second burst transfer
“10100h” is stored, and “2” is set as the data size.
56 "is stored, and D₂₅₅~ D₅₁₀Is stored
Is done. In this burst transfer, four bytes of data are first
TA D₂₅₅~ D₂₅₈Is transferred to the DMA controller 10.
As shown in FIG.₂₅₅Is RAM_1,1Stored in
And data D₂₅₆Is RAM_1,2And the data D
₂₅₇Is RAM_1,3And the data D₂₅₈Is RAM _1,4To
Is stored. Then, 4-byte data D₂₅₉~ D₂₆₂Is D
The data D transferred to the MA controller 10₂₅₉Is R
AM_2,1And the data D₂₆₀Is RAM_{Two , 2}Stored in
And data D₂₆₁Is RAM_2,3And the data D₂₆₂
Is RAM_2,4Is stored in In the same way, each data
Stored in each RAM, data D_{50 7}Is RAM_64,1
And the data D₅₀₈Is RAM_64,2Stored in
Data D₅₀₉Is RAM_64,3And the data D₅₁₀Is RA
M_64,4Is stored in

In the third block, as shown in FIG.
As the first address value corresponding to the second burst transfer
“10200h” is stored, and the data size is “2”.
56 "is stored, and D₅₁₁~ D₇₆₆Is stored
Is done. In this burst transfer, four bytes of data are first
TA D₅₁₁~ D₅₁₄Is transferred to the DMA controller 10.
Thus, as shown in FIG.₅₁₁Is RAM_1,1Stored in
And data D₅₁₂Is RAM_1,2And the data D
₅₁₃Is RAM_1,3And the data D₅₁₄Is RAM _1,4To
Is stored. Then, 4-byte data D₅₁₅~ D₅₁₈Is D
The data D transferred to the MA controller 10₅₁₅Is R
AM_2,1And the data D₅₁₆Is RAM_{Two , 2}Stored in
And data D₅₁₇Is RAM_2,3And the data D₅₁₈
Is RAM_2,4Is stored in In the same way, each data
Stored in each RAM, data D_{76 Three}Is RAM_64,1
And the data D₇₆₄Is RAM_64,2Stored in
Data D₇₆₅Is RAM_64,3And the data D₇₆₆Is RA
M_64,4Is stored in

In the fourth block, as shown in FIG.
As the first address value corresponding to the second burst transfer
“10300h” is stored, and the data size is “2”.
56 "is stored, and D₇₆₇~ D₁₀₂₂But
Will be delivered. In this burst transfer, first 4-byte data
Data D₇₆₇~ D₇₇₀Is transferred to the DMA controller 10.
As shown in FIG.₇₆₇Is RAM_1,1Stored in
And data D₇₆₈Is RAM_1,2And the data D
₇₆₉Is RAM_1,3And the data D₇₇₀Is RAM_1,4To
Is stored. Then, 4-byte data D₇₇₀~ D₇₇₃Is D
The data D transferred to the MA controller 10₇₇₁Is R
AM_2,1And the data D₇₇₂Is RAM_2,2Stored in
And data D₇₇₃Is RAM_2,3And the data D₇₇₄
Is RAM_{2, Four}Is stored in In the same way, each data
Stored in each RAM, data D₁₀₁₉Is RAM_64,1
And the data D₁₀₂₀Is RAM_64,2Stored in
Data D₁₀₂₁Is RAM_64,3And the data D₁₀₂₂Is R
AM_64,4Is stored in

In the fifth block, as shown in FIG. 2, "10400h" is stored as the head address value and "1" is stored as the data size in response to the fifth burst transfer. As shown in FIG. 7, D ₁₀₂₃ is stored in the RAM _1,1 as data.

The buffer controller 12 stores the data sent from the master read controller 11 in each block of the buffer memory 13 as described above. That is,
The buffer control unit 12 sends a data writable block (a block in which no data is stored, or all stored data has been already read out and sent to the transfer destination device) among the eight blocks in the buffer memory 13. Block), and the data sent from the master read control unit 11 is stored in the selected block. The buffer control unit 12 also stores, in the selected block, the start address value and the data size of the data string stored in this block. When the storage of data in the selected block is full, the buffer control unit 12 selects the next block in which data can be written, and transfers the data and the like sent from the master read control unit 11 to the selected block. Store in blocks.

At this time, the buffer control unit 12 stores the data transmitted on the data lines DATA 0 to DATA 7 of the first bus 50 in the RAM _{m, 1} (m = 1 to 64) in order, and
The data transmitted on the data lines DATA 8 to 15 of 0
M _{m, 2} (m = 1 to 64) in order, and the data transmitted through the data lines DATA 16 to 23 of the first bus 50 is stored in the RAM
_{m, 3} (m = 1 to 64) in order, and the data transmitted on the data lines DATA 24 to 31 of the first bus 50 is stored in the RAM _{m, 4}
(M = 1 to 64).

However, as in the above example, at first, the transfer
3 consecutive after the first address in the original device 20
Byte data D₀~ D_TwoAre the data lines DATA 8 of the first bus
It is sent to the DMA control device 10 via 23. This and
At this time, the buffer control unit 12₀The RAM_1,2
And the data D₁The RAM_1,3And the data D _Two
The RAM_1,4To store. Also, as in the above example,
After that, one byte of the last address in the transfer source device 20
Site data D₁₀₂₃Via the data lines DATA0 to DATA7 of the first bus
And sent to the DMA controller 10. At this time
Indicates that the data D₁₀₂₃The RAM
_64,1To store.

Next, reading of data stored in the buffer memory 13 will be described. When the data writing to each block of the buffer memory 13 is completed, the buffer control unit 12 reads the data stored in the block where the writing has been completed, and
4 can be sent. When reading this,
The buffer control unit 12 stores the lower 2 bits of each of the first address value and the second address value stored in the register 15.
Bits are compared, and data stored in each block is read out in a predetermined order based on the comparison result.

The first address value is set to 100 as in the above example.
01h and the second address value 20003h, the difference between the lower two bits is 2, so that the buffer controller 12 stores the data stored in RAM _{m, 1} and RAM _{m, 2} respectively. The data stored in the RAMs _m-1,3 and _m-1,4 are simultaneously read and rearranged and sent to the master write controller 14.
When rearranging this data, a 4 to 4 multiplexer MUX is used (see FIG. 3).

That is, when data writing to the first block of the buffer memory 13 is completed, first, the buffer control unit 12 stores the data in the RAMs ₁ and ₂ of the data storage unit (see FIG. 4) of the first block. It reads the data D ₀ you are, the data D ₀ data line dATA. 24 to the second bus 60
The data D ₀ is sent to the master write control unit 14 so that the data D ₀ can be sent to the master write control unit 14. Subsequently, the buffer control unit 12 stores the data D ₁ stored in the RAMs ₁ and ₃ of the data storage unit of the first block, the data D ₂ stored in the RAMs ₁ and ₄ ,
Data D ₃ stored in RAMs ₂ and ₁ and RAM
Data D ₄ stored in ₂ and ₂ are simultaneously read out,
By rearranging these 4-byte data, the data D
₁ is adapted to be sent to the data line DATA 0 to 7 of the second bus 60, the data line DATA 8 to 15 of the data D ₂ second bus 60
As it may be sent to, and adapted to send data D ₃ to data lines DATA 16 to 23 of the second bus 60, and adapted to send data D ₄ to the data line DATA 24 to 31 of the second bus 60 Then, these 4-byte data D _{1 to} D ₄ are sent to the master write control unit 14. Similarly, the buffer control unit 12 reads the data stored in each RAM of the data storage unit of the first block every 4 bytes and sends the data to the master write control unit 14.

The data stored in the second block of the buffer memory 13 is
When the data writing is completed, the buffer control unit 12
RAM of one block data storage unit (see FIG. 4)_64,3To
Stored data D₂₅₃, Data case of the first block
RAM in storage_64,4Data D stored in₂₅₄, Second
RAM of block data storage (see FIG. 5)_1,1Case
Data D stored₂₅₅, And the data of the second block
RAM for data storage_1,2Data D stored in
₂₅₆Are read at the same time, and these 4 bytes of data are
By rearranging, the data D₂₅₃On the second bus 60
Data D0 to DATA7, and the data D₂₅₄The
2 so that it can be sent to the data lines DATA 8 to 15 of the bus 60
And data D₂₅₅To the data lines DATA 16 to 23 of the second bus 60.
And the data D₂₅₆Of the second bus 60
So that they can be sent to the data lines DATA 24-31.
4-byte data D₂₅₃~ D₂₅₆To the master light control unit 1
Send to 4. Subsequently, the buffer control unit 12
RAM for data storage_1,3Data stored in
D₂₅₇, RAM_1,4Data D stored in₂₅₈, RA
M_2,1Data D stored in₂₅₉And RAM
_2,2Data D stored in₂₆₀At the same time
By rearranging these 4 bytes of data,
TA D_{twenty five 7}To the data lines DATA 0 to DATA 7 of the second bus 60.
Data D₂₅₈To the data line DAT of the second bus 60
A so that it can be sent to₂₅₉The second bus
60 data lines DATA 16 to 23, and
Data D₂₆₀To the data lines DATA 24 to 31 of the second bus 60
As a result, these four bytes of data D_{Two 57}~ D
₂₆₀To the master write control unit 14. And so on
The buffer control unit 12 stores the data of the second block.
The data stored in each RAM of the
The data is sent to the master write control unit 14.

The data stored in the third block of the buffer memory 13 is
When the data writing is completed, the buffer control unit 12
RAM of data storage unit of two blocks (see FIG. 5)_64,3To
Stored data D₅₀₉, Data case of the second block
RAM in storage_64,4Data D stored in₅₁₀, Third
RAM of block data storage (see FIG. 6)_1,1Case
Data D stored₅₁₁, And the third block
RAM for data storage_1,2Data D stored in
₅₁₂Are read at the same time, and these 4 bytes of data are
By rearranging, the data D₅₀₉On the second bus 60
Data D0 to DATA7, and the data D₅₁₀The
2 so that it can be sent to the data lines DATA 8 to 15 of the bus 60
And data D₅₁₁To the data lines DATA 16 to 23 of the second bus 60.
And the data D₅₁₂Of the second bus 60
So that they can be sent to the data lines DATA 24-31.
4-byte data D₅₀₉~ D₅₁₂To the master light control unit 1
Send to 4. Subsequently, the buffer control unit 12
RAM for data storage_1,3Data stored in
D₅₁₃, RAM_1,4Data D stored in₅₁₄, RA
M_2,1Data D stored in₅₁₅And RAM
_2,2Data D stored in₅₁₆At the same time
By rearranging these 4 bytes of data,
TA D_{51 Three}To the data lines DATA 0 to DATA 7 of the second bus 60.
Data D₅₁₄To the data line DAT of the second bus 60
A so that it can be sent to₅₁₅The second bus
60 data lines DATA 16 to 23, and
Data D₅₁₆To the data lines DATA 24 to 31 of the second bus 60
As a result, these four bytes of data D_{Five 13}~ D
₅₁₆To the master write control unit 14. And so on
The buffer control unit 12 stores the data of the third block.
The data stored in each RAM of the
The data is sent to the master write control unit 14.

The data stored in the fourth block of the buffer memory 13 is
When the data writing is completed, the buffer control unit 12
RAM of data storage unit of three blocks (see FIG. 6)_64,3To
Stored data D₇₆₅, Data case of the third block
RAM in storage_64,4Data D stored in₇₆₆, Fourth
RAM of block data storage (see FIG. 7)_1,1Case
Data D stored₇₆₇, And the fourth block
RAM for data storage_1,2Data D stored in
₇₆₈Are read at the same time, and these 4 bytes of data are
By rearranging, the data D₇₆₅On the second bus 60
Data D0 to DATA7, and the data D₇₆₆The
2 so that it can be sent to the data lines DATA 8 to 15 of the bus 60
And data D₇₆₇To the data lines DATA 16 to 23 of the second bus 60.
And the data D₇₆₈Of the second bus 60
So that they can be sent to the data lines DATA 24-31.
4-byte data D₇₆₅~ D₇₆₈To the master light control unit 1
Send to 4. Subsequently, the buffer control unit 12
RAM for data storage_1,3Data stored in
D₇₆₉, RAM_1,4Data D stored in₇₇₀, RA
M_2,1Data D stored in₇₇₁And RAM
_2,2Data D stored in₇₇₂At the same time
By rearranging these 4 bytes of data,
TA D_{76 9}To the data lines DATA 0 to DATA 7 of the second bus 60.
Data D₇₇₀To the data line DAT of the second bus 60
A so that it can be sent to₇₇₁The second bus
60 data lines DATA 16 to 23, and
Data D₇₇₂To the data lines DATA 24 to 31 of the second bus 60
As a result, these four bytes of data D_{7 69}~ D
₇₇₂To the master write control unit 14. And so on
The buffer control unit 12 stores the data of the fourth block.
The data stored in each RAM of the
The data is sent to the master write control unit 14.

When the data writing to the fifth block of the buffer memory 13 is completed, the buffer control unit 12 sets the data D ₁₀₂₁ and D ₁₀₂₁ stored in the RAMs ₆₄ and 3 of the data storage unit of the fourth block (see FIG. 7). The data D ₁₀₂₂ stored in the RAMs ₆₄ and 4 of the data storage unit of the fourth block, and the RAM of the data storage unit (see FIG. 8) of the fifth block.
_By reading out the data D ₁₀₂₃ stored in ₁ , ₁ at the same time and rearranging these three bytes of data, the data D ₁₀₂₁ can be transmitted to the data lines DATA 0 to DATA 7 of the second bus 60, Data D ₁₀₂₂ to the data line of the second bus 60
DATA 8 to 15 and transmit the data D ₁₀₂₃ to the second
The three-byte data D _{1021 to} D ₁₀₂₃ are sent to the master write control unit 14 so that they can be sent to the data lines DATA 16 to 23 of the bus 60.

The master write control unit 14 receives the data sent from the buffer control unit 12 as described above after acquiring the right to use the second bus 60 as a master, and Burst output to the transfer destination device 30.

As described above, in the DMA control device 10 according to the present embodiment, the buffer memory 14 is constituted by a RAM, and the data burst-input from the transfer source device 20 is stored in the buffer memory 14 without being rearranged.
On the other hand, the data stored in the buffer memory 14 is read, the data is rearranged as necessary, and then the data is burst output to the transfer destination device 30. At the time of this data rearrangement, the buffer control unit 12 determines each data to be burst output by the master write control unit 14 based on the first address value in the transfer source device 20 and the second address value in the transfer destination device 30. The data is sequentially read from the buffer memory 13, rearranged, and sent to the master write control unit 14.

Therefore, this DMA control device 10
Since it is sufficient to provide only one 4to4 multiplexer as a circuit for rearranging data, the circuit scale is small and inexpensive. Also, this DMA control device 10
Has a low latency and is easy to speed up data transfer. Further, since there is no limitation on either the first address value or the second address value, even if the data widths of the first bus 50 and the second bus 60 are different from each other, the transfer source device 20 and the This DMA control device 10 can be used regardless of the type of each of the transfer destination devices 30.

[0043]

As described above in detail, according to the DMA control device of the present invention, each data stored in the continuous address area after the start address value in the transfer source input / output device is the data input / output device. Input by means,
It is stored in the temporary storage means. Each data stored in the temporary storage means is sequentially read out by the buffer control means based on the start address value in the transfer source input / output device and the start address value in the transfer destination input / output device, and is read out to the data output means. The data is output by the data output means to a continuous address area after the start address value in the transfer destination input / output device. If the addresses of the transfer source and the transfer destination are different, the data must be rearranged. However, in the DMA control device according to the present invention, the buffer control means transfers data from the temporary storage means based on both address values. At the same time as the data is read, the data is rearranged.

Therefore, the DMA control device according to the present invention only needs to include only one multiplexer as a circuit for rearranging data.
It will be cheap. Further, this DMA control device has a small latency and can easily achieve high-speed data transfer. In addition, since a plurality of unit buffers are used, a plurality of blocks having different address difference amounts can be continuously transferred. Since the address conversion is performed on the unit buffer, even if the cycle is interrupted in the middle of the data output, the access using the transfer destination address after the restart is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a DMA control device 10 according to the present embodiment.

FIG. 2 is a diagram showing a configuration of a buffer memory 13 of the DMA control device 10 according to the present embodiment.

FIG. 3 is a diagram showing a configuration of a data storage unit in each block of a buffer memory 13 of the DMA control device 10 according to the present embodiment.

FIG. 4 is a diagram illustrating a state of storing data in a data storage unit in a first block of a buffer memory 13 of the DMA control device 10 according to the present embodiment.

FIG. 5 is a diagram illustrating a state of storing data in a data storage unit in a second block of the buffer memory 13 of the DMA control device 10 according to the present embodiment.

FIG. 6 is a diagram illustrating a state of storing data in a data storage unit in a third block of the buffer memory 13 of the DMA control device 10 according to the present embodiment.

FIG. 7 is a diagram illustrating a state of storing data in a data storage unit in a fourth block of the buffer memory 13 of the DMA control device 10 according to the present embodiment.

FIG. 8 is a diagram illustrating a state of storing data in a data storage unit in a fifth block of the buffer memory 13 of the DMA control device 10 according to the present embodiment.

FIG. 9 is a schematic configuration diagram of a data rearranging unit in a conventional DMA control device.

[Explanation of symbols]

10 DMA controller, 11 Master read controller, 1
2 ... Buffer control unit, 13 ... Buffer memory, 14 ... Master write control unit, 15 ... Register, 16 ... Register control unit, 20 ... Transfer source device, 30 ... Transfer destination device,
40: CPU, 50: First bus, 60: Second bus, 70
... CPU bus.

Claims (7)

[Claims] 1. A direct access (DMA) device for controlling data transfer between input / output devices connected to a single or independent bus without passing through a CPU, comprising: Data input means for reading out block data specified by the address 1) and the size and taking in the data by itself once or plural times; and temporary storage for temporarily holding the data taken in by the data input means Data output means for controlling a transfer destination input / output device to read block data specified by a start address (address 2) and a size from the temporary storage means and to output the data in one or more accesses. The data output means outputs based on an address value of the transfer source input / output device and an address value of the transfer destination input / output device. DMA controller, characterized in that it comprises successively the buffer control means for sending read from the temporary storage means to said data output means, the the data should. 2. The DMA control device according to claim 1, wherein said temporary storage means includes a plurality of unit buffers, and sequentially handles two or more DMA blocks having different address differences. 3. The unit buffer includes data to be transferred and attribute information, and the attribute information includes an address having a sufficient number of bits to represent the number of bytes of the unit buffer in the start address of the transfer source. 3. The DMA control device according to claim 2, comprising: a number of valid bytes stored in a unit buffer, a start block bit indicating the start of a block, and an end address bit indicating an end of the block. 4. An address used for reading from said temporary storage means is an address to be output to said transfer destination input / output device, and a difference between an address value of said transfer source input / output device and an address value of said transfer destination input / output device. 2. The DMA control device according to claim 1, wherein the DMA control device generates the data based on the conversion. 5. The DMA control device according to claim 4, wherein said temporary storage means includes n RAMs equal in number to a data width n of a transfer destination or a transfer source. 6. The temporary storage means comprises: the n RAMs
For each of them, at the time of reading from the data output means, n bytes are stored in accordance with the shift amount calculated from the difference between the start addresses of the transfer source and the transfer destination.
6. The DMA control device according to claim 5, wherein the DMA control device is divided into two areas, and the converted address or the address obtained by subtracting one from the converted address is given. 7. When a cycle is interrupted due to a transfer destination, an address conversion for the temporary storage means after resumption is performed by using the shift amount and a difference address from a start address for the transfer destination. 7. The DMA controller according to claim 6, wherein: