JPH11119975A - Bit width converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve data transfer efficiency and to eliminate the waste of a storage area by arranging a read N-bit part and the M-bit part of a multiplexer output to the constitution of prescribed bit width data. SOLUTION: In an input circuit 10, N/M=32/1=32 pieces are gathered into one word of the internal bus width of 32 bits for data (m) composed of 1 bit of a data area 11 prior to data transfer to a bit width conversion buffer circuit 20, the data (n) composed of 32 bits are stored in a transfer area 12 with 32 words as one unit, and this one unit is sent out to the bit width conversion buffer circuit 20. For the data to be sent to an output circuit 30, (n) from an N part buffer memory 21 and (m) corresponding to (n) inside an M part buffer register 22 are selected in an M part multiplexer 25 by the designation of a read pointer 24 and they are arranged to (n)+(m)=L which is the constitution of prescribed 33-bit width data. That is, the 32 pieces of the prescribed 33-bit width data are turned into a single unit, the generation of a wasteful idle area is suppressed, and bit width conversion is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer buffer circuit having a function of converting data over a plurality of words into data having a predetermined bit width.

[0002]

2. Description of the Related Art A conventional technique of converting predetermined L-bit width data processed at a transfer source 110 constituted by an N-bit width internal bus 112 and a storage area 111 using a transfer buffer 120 is shown. 4 will be described.

The predetermined L-bit width data is stored in the storage area 111 of the transfer source 110 in two words consisting of an N-bit part and an N-bit part of an M-bit part. (Indicated by Ami-kake in the figure).

The data stored in the storage area 111 is transferred to the transfer buffer 12 through an internal bus 112 having a width of N bits.
When transferring to 0, two transfer processes are performed to transfer the N-bit part to the N-part buffer 121 and the M-bit part to the M-part buffer 122 for one word of predetermined L-bit width data.

[0005] N section buffer 121 and M section buffer 122
Are read out simultaneously, adjusted to predetermined L-bit width data, and transferred to an external circuit via the external bus 123. As described above, the conventional technique has problems that the number of times of data transfer is twice as large as the amount of data to be transferred, and that the data storage area includes a useless free area.

[0006]

As described above, when bit width conversion is performed by the conventional technique, there are problems such as poor transfer efficiency and waste of storage area. For example, L = 33 bits, N = 32 bits, M =
In the case of 1 bit and data amount of 32 words, the transfer count is 32
The word x 2 times = 64 times, and the useless empty area is (32 bits-1 bit) x 32 words = 992 bits (32 words / word becomes 31 words). An object of the present invention is to improve data transfer efficiency and eliminate waste of a storage area.

[0007]

In order to achieve the above object, a predetermined L-bit width data is transferred to a bit-width conversion buffer circuit before the predetermined L-bit width data is transferred via an N-bit input data bus. Is divided into an N-bit part and an M-bit part (N> M), N / M words are collected from the N-bit part, N / M parts of the M-bit part are collected into one word composed of N bits, and stored in the transfer area. Input circuit, a write pointer for holding an address sent from the input circuit to a bit width conversion buffer circuit, an N-part buffer memory for storing N / M words in an N-bit part, and N / M M-bit parts. An M-part buffer register composed of N bits to be stored, a read pointer for indicating an address to read out the contents of the N-part buffer memory and the M-part buffer register to the output circuit,
It has a multiplexer for selecting an M-bit portion corresponding to the read N-bit portion, and means for adjusting the read N-bit portion and the M-bit portion of the multiplexer output to a predetermined L-bit width data configuration.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the embodiment of the present invention, a case where L = 33 bits, N = 32 bits and M = 1 bit will be described. In the input circuit, predetermined L-bit width data is divided into an N-bit portion and an M-bit portion prior to data transfer, and each of the divided data is represented by n and m. N divided into 32 words consisting of n1 to n32 and m
Are collected in the transfer area as one word composed of m1 to m32 and sent to the bit width conversion buffer circuit.

In the bit width conversion buffer circuit, n sent from the input circuit is stored in a 32-bit N-part buffer memory, and m1 to m3 stored in one word.
2 is stored in an M-part buffer register consisting of one word having a 32-bit configuration.

For reading for sending to the output circuit, n is selected from the N-part buffer memory and m corresponding to n from the M-part buffer register through the multiplexer according to the designation of the read pointer. These n and m are arranged in a predetermined L-bit width data configuration and sent to an output circuit via an L-bit width output data bus.

As described above, for example, when 32 bits of data are to be converted into a bit width, 64 times of data transfer are required in the prior art. However, according to the bit width conversion buffer circuit of the present invention, 33 times of data transfer are required. Bit width conversion can be completed by transfer. In addition, the useless empty area of the storage area of the input circuit is 32 bits 31 in the conventional method.
Although an empty area of a word has been generated, the generation of an empty area can be suppressed according to the bit width conversion buffer circuit of the present invention.

[0012]

[Embodiment 1] An embodiment of the present invention will be described below. FIG. 1 is a configuration diagram of a bit width conversion device according to the present invention. As shown in FIG. 1, the bit width conversion device includes an input circuit 10, a bit width conversion buffer circuit 20, and an output circuit 30.
And an input data bus 1 for connecting respective circuits.
3, an input address bus 14, and an output data bus 26.

In an input circuit 10 having an internal bus width of 32 bits, predetermined L-bit width data of an output circuit 30 which finally performs data processing as shown in a data area 11 is divided into an N-bit portion and an M-bit portion. It is processed as information of two words consisting of 32 bits per word.

In the input circuit 10, prior to data transfer to the bit width conversion buffer circuit 20, N / M = 32/1 =
Thirty-two bits are collected into one word having an internal bus width of 32 bits, the 32-bit data n is stored in the transfer area 12 in units of 32 words, and this one unit is sent to the bit width conversion buffer circuit 20.

The bit width conversion buffer circuit 20 includes an N buffer memory 21, an M buffer register 22, a write pointer (WTPT) 23, and a read pointer (RD).
PT) 24, an M section multiplexer (MPX) 25, and a control circuit 27 for controlling writing / reading of a buffer.

In the data sent from the input circuit 10, an address sent via the input address bus 14 is latched by a write pointer (WTPT) 23, and m1 to m1 are integrated into one word of a 32-bit configuration by designation. m32 is written to the M buffer register 22, and 32-word data consisting of n1 to n32 is written to the N buffer memory 21.

The data to be sent to the output circuit 30 is selected from the N buffer memory 21 by the designation of the read pointer (RDPT) 24 and m corresponding to n in the M buffer register 22 by the M multiplexer 25. The data is adjusted to n + m = L, which is a structure of predetermined 33-bit width data. Then, the data is sent to the output circuit 30 via the output data bus 26 having a width of 33 bits.

The writing / reading to / from the bit width conversion buffer 20 is performed by "FUL" generated by the control circuit 27.
L and “EMPTY”. When the input circuit 10 completes the writing of n1 to n32 and m1 to m32 into all the areas of the N buffer memory 21 and the M buffer register 22, the "FULL" signal is turned ON, the subsequent data transmission is suppressed, and the Reading for sending data to the circuit 30 becomes possible. All data 3 of N section buffer memory 21 and M section buffer register 22
When the reading of two words is completed, the "EMPTY" signal turns on.
When there is data to be sent to the input circuit 10, data can be sent.

With the above processing, the bit width conversion is performed with the number of transfer times of 33 and the generation of useless empty areas suppressed, with 32 predetermined 33-bit width data as one unit.

[0020]

[Embodiment 2] An embodiment of claim 2 will be described below with reference to FIG.
This will be described with reference to FIG. Since the M-bit part consisting of one word collected in the transfer area 12 of the input circuit 10 is composed of m1 to m32, data corresponding to n1 to n32 of the N-bit part is collected into one word. Therefore, if one word of the M-bit part is written in the M-part buffer register 22 first, then when the first data n1 of the N-bit part is written in the N-part buffer memory 21, a predetermined 33 bits are written. As soon as the first data (n1 and m1) of the width data is completed, reading for sending to the output circuit 30 can be started immediately.

In the read control of this embodiment, the completion of writing to the M buffer register 22 and the writing pointer (W
This is performed by comparing the value of the read pointer (RDPT) 24 with the value of the read pointer (RDPT) 24, and if WTPT> RDPT, enables reading. In FIG. 2, a shaded portion indicates a written area.

By performing the above processing, the bit width conversion buffer circuit 20 converts the data into predetermined 33-bit width data to the output circuit 30 and sends the converted data to the N-bit portion 32 words and the M-bit portion 1 word. Need not wait for the input circuit 10 to be sent from the input circuit 10 to the bit width conversion buffer circuit 20,
Transfer efficiency is improved.

[0023]

[Embodiment 3] An embodiment of claim 3 will be described below. With the N buffer memory 21 and the M buffer register 22 as one set, the same circuit is
The transfer efficiency can be improved by alternately using the group-provided banks A and B, but this method requires more hardware. In this embodiment, only the M buffer register 22 is set to 2
By simply providing a set, the transfer efficiency is improved with a smaller circuit configuration than the method of providing the two sets of circuits.

FIG. 3 is a block diagram of the present embodiment. Bank B
The M section buffer register 221 for bank, the M section multiplexer 222 for bank B, the bank switching multiplexer 223, and the bank designation circuit 224 are additional circuits in this embodiment. Specifically, after all data of 33 words have been written from the input circuit 10 to the N buffer memory 21 and the M buffer register 22, the next sent m1 to m32 are written to the bank B M buffer register 221. .

Thereafter, in the bit width conversion buffer circuit 20, n and m specified by the read pointer 24 are sequentially read from the N buffer memory 21 and the M buffer register 22 for transmission to the output circuit 30. At this time, control is performed so that data n to be transmitted next can be written in the N-part buffer memory area from which reading has been completed. With this control, the N-part buffer memory 21 stores “EM
Before becoming “PTY”, the next data to be sent can be prepared in the bit width conversion buffer circuit 20.

All data consisting of 32 words of the N-part buffer memory 21 and the M-part buffer register 22 are read and read as "EM
When the “PTY” signal is turned on, the bank designating circuit 2
24 is inverted to switch to the bank B M section buffer register 221 designation. Then, m1 to m32 to be sent next are M
Write to the section buffer register 22. Since then, "EMPT
This operation is repeated every time the "Y" signal is turned ON.

In this embodiment, writing from the input circuit 10 to the bit width conversion buffer circuit 20 is performed in such a manner that m1 to m32 to be transmitted next are written to the M buffer register and a write pointer (WTPT). 23 and the value of the read pointer (RDPT) 24, and
If T <RDPT, it is controlled by enabling writing.

As described above, by providing two sets of only the M section buffer register, the 32
Without waiting for all the words to be read, the next transmission data is sent from the input circuit 10 to the bit width conversion buffer circuit 2 in advance.
Since it can be transmitted to 0, the use efficiency of the bit width conversion buffer circuit 20 can be improved.

In the embodiment of the present invention, a FIFO is configured using a memory as the N-part buffer memory 21, but it is obvious that the present invention can be applied to a configuration using a shift register.

[0030]

As described above, according to the bit width conversion apparatus according to the present invention, when performing bit width conversion in data transfer between circuits having different bit widths, the number of data transfers is reduced and the buffer use efficiency is improved. Buffer capacity can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a bit width conversion device of the present invention.

FIG. 2 is a configuration diagram of a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a third embodiment of the present invention.

FIG. 4 is a configuration diagram of a conventional method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Input circuit 11 Data area 12 Transfer area 13 Input data bus 14 Input address bus 20 Bit width conversion buffer circuit 21 N part buffer memory 22 M part buffer register 23 Write pointer 24 Read pointer 25 M part multiplexer 26 Output data bus 27 Control circuit 30 output circuit

Claims (3)

[Claims] 1. A predetermined L-bit width data is divided into an N-bit part consisting of N bits and an M-bit part consisting of M bits (N> M), and the N-bit part is collected by N / M words, and the M-bit part is collected. An input circuit that collects N / M pieces into one word composed of N bits and stores them in a transfer area, a write pointer that holds an address sent from the input circuit section, and N from the transfer area of the input circuit section. According to the value of the write pointer, N / bit data transmitted through the input data bus consisting of
An N-part buffer memory for storing M words, and M transmitted from the transfer area of the input circuit part via the input data bus.
An N-bit buffer register consisting of N bits for storing N / M data of a bit portion, a read address of the N-port buffer memory, and an M bit in the M-port buffer register corresponding to the read N-bit portion A read pointer for designating an N-bit buffer, a multiplexer for selectively outputting the M-bit portion designated by the read pointer,
A bit width conversion device, comprising: a bit width conversion circuit including a bit portion and a unit for adjusting an M bit portion of the multiplexer output to predetermined L bit width data. 2. The method according to claim 1, wherein the M-bit part is written into the M-part buffer register before the N-bit part is written into the N-part buffer memory, and the N-bit part is at least one.
As soon as a word is written into the N-part buffer memory, M
A bit width conversion device comprising: means for reading data from an external buffer register and an N buffer memory. 3. The bit width conversion device according to claim 2, further comprising: two sets of M section buffer registers, and means for writing the next transmission data from the input circuit to a read area of the N section buffer memory. .