JP2541117B2 - Data access device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data access device for data processing using a CD-ROM.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional example of a data access device of this type, and FIG. 5 is a timing diagram showing the relationship between each processing and the contents of RAM 21.

This data access device is a CD-ROM
Input data block 22 for reading serial input data from a CD data processor (not shown), converting it into parallel data and writing it to RAM 21, and correcting data by reading data from RAM 21 and performing a syndrome operation. Then, the correction processing block 23 to be written in the RAM 21, the output processing block 24 for reading the corrected data from the RAM 21 and outputting it to the host (not shown), and the data between the RAM 21 and each of the blocks 22, 23, 24. A bus 25 for transfer, a tri-state buffer 27 that outputs the output data of the input processing block 22 to the bus 25 when it is in the enable state, and a correction process for the data on the bus 25 when it is in the enable state. Triste output to block 23 And Tobaffa 28, by enabled state, tri-state buffer 29 for outputting the output data of the correction processing block 23 to the bus 25
Then, the tri-state buffer 30 that outputs the data on the bus 25 to the processing block 24 by the enable state, and the control signal indicating that each processing is in progress from the input processing block 22, the correction processing block 23, and the output processing block 24. From the bus control block 26 for inputting and enabling the corresponding tristate buffer among the tristate buffers 27 to 30, the input processing block 22, the correction processing block 23, and the output processing block 24 to the RAM 21.
The address control block 31 inputs the address of the above and outputs it to the RAM 21.

This data access device, as shown in FIG. 5, converts serial data input from a CD data processor into parallel data in an input processing block 22 and passes it to a RAM 2 through a tristate buffer 27 and a bus 25.
The data input to the bank 1 of 1 is read one by one from the bank 2 of the RAM 21 through the bus 25 and the tri-state buffer 28 in the correction processing block 23 to perform the syndrome operation, and the tri-state buffer 29 after the correction processing, RAM21 again via bus 25
In the output processing block 24, the corrected data input two sectors before is read from the bank 3 of the RAM 21 through the bus 25 and the tri-state buffer 30 and output to the host in parallel.

[0005]

In the conventional data access device described above, the input process, the correction process, and the output process must be performed in parallel, but since all the accesses are performed through one bus, the RAM 21 is used. Access count = input process (write) access count + correction process (write + read) access count + output process (read) access count. On the other hand, the time required for all the processing for one sector is the cycle in which the data for one sector is input. The cycle is 13.3 ms in the standard speed mode of the CD-ROM. When the CD-ROM becomes double speed or quad speed, the cycle is 6.66 ms, 3.33 m.
s. Therefore, if the number of RAM accesses is the same, the time required for one process is shortened if the data transfer speed is increased, and if the time required for one process is the same, the data transfer speed cannot be increased. .

An object of the present invention is to provide a data access device capable of performing high speed data transfer of a CD-ROM.

[0007]

A data access device of the present invention reads serial input data from a CD data processor and first and second RAMs in which data in a CD-ROM is temporarily stored, and converts the data into parallel data. An input processing block for converting and writing to the first RAM and the second RAM, and a correction processing for reading data from the first RAM, performing correction processing, and writing to the first RAM and second RAM A block; an output processing block for reading data from the second RAM and outputting the data to the host;
First RAM for transferring data between the RAM, the input processing block, and the correction processing block, and a second R
A second bus for transferring data between the AM and the output processing block, and by being enabled,
First transfer control means for outputting the data on the first bus to the second bus, and second transfer control for outputting the output data of the input processing block to the first bus by being enabled. Means for outputting data on the first bus to the correction processing block by being in the enable state, and output data of the correction processing block by the first transfer control means by being in the enable state. Fourth transfer control means for outputting to the output processing block, and fifth transfer control means for outputting the data on the second bus to the output processing block, and input data for the first and second transfer control means. When writing to the second RAM, the first and second transfer control means are enabled, and when the correction processing of the data in the first RAM is performed, the third transfer control means is enabled. The correction process is performed data first,
When writing to the second RAM, the first and fourth transfer control means are enabled, and when the corrected data written to the second RAM is output to the output processing block, fifth transfer control is performed. A bus control block for enabling the means, a first address control block for inputting an address to the first RAM from the input processing block or the correction processing block and outputting the first RAM, and the input processing It has a second address control block which inputs an address from the block, the correction processing block or the output processing block to the second RAM and outputs the address to the second RAM.

[0008]

The number of accesses to the first RAM is the sum of the number of accesses to the input process (write), the number of accesses to the correction process (read) and the number of accesses to the correction process (write), and the number of accesses to the second RAM is It is the sum of the access count of the input process (write), the access count of the correction process (write), and the access count of the output process. That is, the number of times of accessing each RAM is smaller than the number of times of accessing the RAM of the conventional device. Therefore, if the internal cycle is the same as the conventional one, the time until the processing of the data for one sector is completed becomes short, so the data input speed becomes short, and if the data input speed is the same as the conventional one. For example, since the internal cycle can be lengthened, the size of the element can be reduced, and the cost and power consumption can be reduced.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of a data access device according to an embodiment of the present invention, and FIG.
FIG. 3 is a timing chart showing the relationship between the contents of AM1 and AM2, and FIG. 3 is a timing chart showing the outputs of the buses 6 and 7 and the tri-state buffer 9.

A CD-RO is stored in the first and second RAMs 1 and 2.
The data of M is temporarily stored. Input processing block 3 is C
It receives input data from a D data processor (not shown) and outputs 8-bit width data to the first RAM 1 and the second RA 1.
Output to M2. The correction processing block 4 is the first RAM 4
Data is sequentially read according to the correction processing format of the CD-ROM, correction processing is performed, and the corrected data is written again in the RAM1 and RAM2. The output processing block 5 reads the data from the second RAM 2 and outputs it to the host side. The first bus 6 and the second bus 7 are connected to the first RAM 1 and the second RAM 2, respectively. The tri-state buffer 9 controls whether to output the data on the first bus 6 to the second bus 7. The tri-state buffer 10 controls whether to output the data of the input processing block 3 to the first bus 6. The tri-state buffer 12 controls whether or not the data corrected by the correction processing block 4 is output to the first bus 6.
The trist buffer 11 controls whether or not the data on the first bus 6 is input to the correction processing block 4. The tri-state buffer 13 controls whether or not the data on the second bus 7 is input to the output processing block 5. When the control signal for starting the input processing is input from the input processing block 3, the bus control block 8 receives the tri-state buffer 9
When the control signal for starting the correction processing is input from the correction processing block 4, the tri-state buffer 11 is first enabled, then the tri-state buffers 9 and 12 are enabled, and the output processing block When the control signal for starting the output process is input from 5, the tri-state buffer 13 is enabled. The first address control block 14 inputs the address of the first RAM 1 from the input processing block 3 or the correction processing block 4 and outputs it to the first RAM 1. The second address control block 15 includes the input processing block 3 or the correction processing block 4 or the output processing block 5 to the second processing block 5.
The RAM 2 address is input and output to the second RAM 2.

Next, the operation of this embodiment will be described with reference to FIGS. Input data from the CD data processor is input in sector units. If this input data is N sectors for convenience, the data of the Nth sector is first input to the input processing block 3 and becomes 8-bit parallel data. This 8-bit data is written to the bank 1 of the first RAM 1 through the tristate buffer 10 and the first bus 6, and from the tristate buffer 9 to the bank 1 of the second RAM 2 through the second bus 7. on the other hand,
In the correction processing block 4, the data input one sector before is stored in the first processing according to the correction processing format of the CD-ROM.
It is read from the bank 2 of the RAM 1 through the first bus 6 and the tri-state buffer 11 and used for the syndrome calculation. At the same time, in the output processing block 5, the data input two sectors before is read from the bank 3 of the second RAM 2 through the second bus 7 and the tristate buffer 13. The data corrected by the correction processing block 4 is transferred to the bank 2 of the first RAM 1 through the tristate buffer 12 and the first bus 6 and to the bank 2 of the second RAM 2 through the tristate buffer 9 and the second bus 7.
Is input to The timing when attention is paid to the bus in this state is shown in FIG. As can be seen from FIG. 3, input data write I, correction data read S, and correction data write C are performed on the first bus 6 (first RAM 1), and the input data is input on the second bus 7 (RAM 2). Write I, read O of output data, and write C of correction data.

In this embodiment, the number of accesses to the RAMs 1 and 2 is smaller than that in the conventional device, and therefore the time until the processing of data for one sector is completed is shortened in the same internal cycle, so that the data input rate is increased. Shorter, the same data rate, longer internal cycle, smaller device size, low cost,
Low power consumption can be realized.

[0014]

As described above, according to the present invention, by having a plurality of RAMs and a plurality of buses, the accesses to the RAMs can be dispersed and the number of accesses can be reduced. Since the time until the processing of the data for the sector is shortened, the data input rate is shortened, and if the data rate is the same, the internal cycle can be lengthened, the element size can be reduced, and the cost can be reduced. There is an effect that low power consumption can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a data access device according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing each process and contents of RAMs 1 and 2 in the embodiment of FIG.

3 is a timing diagram of buses 6 and 7 in the embodiment of FIG.

FIG. 4 is a block diagram of a conventional example of a data access device.

5 is a timing diagram showing each process and contents of RAM 21 in the conventional example of FIG.

[Explanation of symbols]

 1 1st RAM 2 2nd RAM 3 Input processing block 4 Correction processing block 5 Output processing block 6 1st bus 7 2nd bus 8 Bus control block 9-13 Tri-state buffer 14 1st address control block 15 Second address control block

Claims (2)

(57) [Claims] 1. First and second RAMs for temporarily storing CD-ROM data, serial input data from a CD data processor, converted to parallel data, and the first RAM and second RAM. An input processing block for writing to the RAM, a correction processing block for reading data from the first RAM, performing correction processing, and writing the data to the first RAM and the second RAM, and reading data from the second RAM. However, between the output processing block for outputting to the host, the first RAM for transferring data between the first RAM and the input processing block, and the correction processing block, and between the second RAM and the output processing block. A second bus for transferring data, and a first transfer controller for outputting the data on the first bus to the second bus by being in the enable state. A second transfer control means for outputting the output data of the input processing block to the first bus by being in the enable state, and the correction of the data on the first bus by being in the enable state. Third transfer control means for outputting to the processing block; and fourth transfer control means for outputting the output data of the correction processing block to the first bus by being in the enable state, and by being in the enable state, Fifth transfer control means for outputting data on the second bus to the output processing block, and when writing input data to the first and second RAMs, the first and second transfer control means are enabled. , When the correction processing of the data of the first RAM is performed, the third transfer control means is enabled, and the corrected data is written in the first and second RAMs. At this time, the first and fourth transfer control means are enabled, and when the corrected data written in the second RAM is output to the output processing block, the fifth transfer control means is enabled. Bus control block, a first address control block that inputs an address of the first RAM from the input processing block or the correction processing block, and outputs the first RAM address to the first RAM, the input processing block or the correction processing block Alternatively, a data access device having a second address control block for inputting the address of the second RAM from the output processing block and outputting it to the second RAM. 2. The first to fifth transfer control means try.
The data access according to claim 1, which is a state buffer.
apparatus.