JP3259688B2 - Data processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing circuit, and more particularly, to a data processing circuit having a parity for error correction for each column of data arranged in a matrix (matrix data) in two directions. And a data processing circuit for performing error correction and error detection using the parity and the error detection code in data having a format having an error detection code.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing an example of a conventional data processing circuit. This conventional data processing circuit includes a buffer RAM (random access memory) 2 for writing data read from a recording medium (not shown), a syndrome operation unit 31 for performing a syndrome operation on the data read from the buffer RAM 2, and a syndrome operation unit. An error correction processing unit 33 that performs error correction on data read from the buffer RAM 2 based on the result, and a CR that performs a CRC (cyclic redundancy check code) operation
And a C operation unit 32. Syndrome operation unit 31, C
The RC operation unit 32 and the error correction processing unit 33 constitute the data processing unit 30.

Next, the operation of the conventional data processing circuit will be described. The data read from the recording medium is
After processing specific to each data processing procedure such as data demodulation is performed, data (matrix data) arranged in a matrix, which is the basic configuration of this data, is n-
1, n, and n + 1 are sequentially written to the buffer RAM2. The error correction and error detection codes are obtained from the area indicated by the read pointer for the data already written in the buffer RAM 2 separately from the input data, that is, m
-1, m, and m + 1 are sequentially read.

The matrix data m written in the buffer RAM 2 will be described with reference to the flowchart of FIG. First, matrix data of m is sequentially read from the buffer RAM 2 with respect to certain column data of one column in two directions (hereinafter, one direction is a P column and the other direction is a Q column) (step 101). The syndrome calculation of the P-column or the Q-column is performed by the syndrome calculation unit 31 (step 102).

Next, it is determined whether or not there is an error based on the result of the syndrome operation (step 103). If there is no error, one of the next P or Q column is read from the buffer RAM 2. If there is an error, the error correction processing unit 33 obtains the error position and error data, reads data at a predetermined address from the buffer RAM 2, corrects and writes the data (step 104). This is all P columns and all Q
Perform a predetermined number of times in a row (steps 105, 101 to 101
104). Finally, for the data for which the correction processing has been completed, the matrix data of m is read from the buffer RAM 2 and the CRC calculation unit 32 performs a CRC calculation.
An error is detected in the matrix data (step 106).

As described above, in the conventional circuit of FIG.
As shown in the schematic diagram of FIG.
When matrix data is written in the order of n, n + 1, the data processing unit 30 already has a buffer RAM
2, the matrix data buffered by 2 is sequentially read out as m-1, m, and m + 1, and error correction processing and error detection processing are performed. In this processing procedure, a syndrome operation is performed in one matrix data input time. , Error correction, the next syndrome operation, and error correction are sequentially performed. After the syndrome operation and error correction of the last column are completed, the corrected matrix data is read from the buffer RAM 2 and the CRC operation is performed. .

Further, syndrome operation, error correction, C
Since the buffer RAM 2 is accessed in each of the RC calculations, the occupancy of the memory bus is high and the current consumption is large. In recent years, with the increase in speed and current consumption of a device for reproducing a recording medium, shortening of data processing time such as error correction and error detection, reduction of the bus occupancy at that time, and suppression of current consumption have been performed. Is required.

In order to satisfy this demand, for example, FIG.
A data processing circuit having the configuration shown in the block diagram of FIG. 1 has been proposed (Japanese Patent Application Laid-Open No. 63-321837). In this data processing circuit, the data is read out from a recording medium (not shown).
-7 The data demodulated by the demodulation circuit 35 is
At the same time as writing to M2, a syndrome operation is performed by the syndrome operation unit 38, and a RAM for storing the result of the syndrome operation is used.

The error correction is performed by reading the syndrome operation result from the RAM storing the syndrome operation result based on the output timing pulse of the timing pulse generation circuit 37 under the control of the microprocessor 36.
The error correction processing unit 39 makes an error determination, and if an error is found, an error position and error data are obtained.
Data is read from a predetermined address of AM2, corrected, and written again. Then, the CRC operation unit 40 performs a CRC operation on the data read from the buffer RAM 2.

In this conventional data processing circuit, as shown in the schematic diagram of FIG.
When data is written in the order of n + 1, the syndrome operation is performed by the syndrome operation unit 38 in the order of n-1, n, and n + 1. When the syndrome operation of a certain data is performed, the error correction processing of the previous data is performed in parallel. And C
The data processing time is reduced by using only the RC operation.

Further, conventionally, a data processing circuit having a configuration shown in a block diagram of FIG. 12 has been known to satisfy the above demand (Japanese Patent No. 2605270). In this conventional data processing circuit, reproduced data reproduced from a recording medium and further demodulated is supplied from a terminal 41 to a RAM 43 through a switch 42 connected to a terminal A, and is operated by a signal from a timing controller 44. It is stored based on an address signal from the controller 45.

When the reproduced data is arranged in a matrix on the RAM 43 and stored, the switch 42 is connected to the terminal B, the switch 46 is connected to the terminal B ', and the RAM 32
The reproduction data of the P column read in the row direction from is generated by the syndrome generation circuit 47 to generate a syndrome based on the inspection data C1, and when there is an error, the error position and error value are calculated by the detection circuit 48, and the error position and The information of the error value is supplied to the error correction circuit 49, and the error data is corrected. The data at the error position is supplied to the address controller 45, and the detected error data in each row of the RAM 43 is rewritten to correct data corrected by the error correction circuit 49 by this address signal.

Subsequently, the switch 42 is connected to the terminal C, and the switch 46 is connected to the terminal C '. The reproduction data of the Q column read out from the RAM 32 in the column direction is supplied to the syndrome generation circuit based on the inspection data C2 in the same manner as described above. The generation of the syndrome by 50, the detection of the information of the error position and the error value by the detection circuit 51, the error correction by the error correction circuit 52, and the rewriting of the corrected data to the RAM 43 are performed.

Next, the switch 42 is connected to the terminal B,
The switch 46 is connected to the terminal B ′, the data is read out from the RAM 2 in the row direction, the remaining error is corrected again by the inspection data C1, and the information on the error position and the error value at that time is returned to the error position and the error value. The information of the error position and the error value suitable for generating the check syndrome obtained by the conversion by the change circuit 54 and the check syndrome from the check syndrome generation circuit 53 are added by the adder 55 to the mod. 2 is added, and the added value is checked by the check circuit 56. If the check result is correct, the amplifier 57 is enabled and the output data of the RAM 43 input via the switch 46 connected to the terminal A 'is amplified. If the result of the check is incorrect, the data output is blocked.

In this conventional data processing circuit, the reading of data from the RAM 43 is particularly performed for generating the check syndrome by adding the information of the error position and error value obtained at the time of error correction to the generated check syndrome. Instead of performing the check, a check is also performed at the end of error correction, thereby shortening the processing time.

[0016]

SUMMARY OF THE INVENTION However, FIG.
0, the conventional data processing circuit does not perform a CRC operation on the input data from the recording medium,
During the RC operation, the data is read from the buffer RAM 2 and the CRC operation is performed by the CRC operation unit 40. Since the syndrome operation, the error correction and the CRC operation are performed in parallel during the input time of one matrix data, a certain degree of correction is performed. Although the time can be shortened, the matrix data is read out from the buffer RAM 2 after the error correction is completed, and the CRC operation is performed. Therefore, the processing time for error correction is long, and the bus occupancy of the buffer RAM 2 is increased. A large amount of current flows.

Further, in the conventional data processing circuit shown in FIG. 12 shown in FIG. 12, it is necessary to read the RAM 43 three times for error correction, so that the bus occupancy of the RAM 43 increases and the current consumption increases. There is a problem that the power consumption is large.

The present invention has been made in view of the above points,
Provide a data processing circuit for error correction and error detection that reduces the bus occupancy and reduces current consumption by shortening the error correction processing time including the syndrome operation and CRC operation and reducing the access to the buffer RAM. The purpose is to do.

[0019]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention relates to a method in which one or two directions of information data arranged in a matrix and reproduced from a recording medium are used. In a data processing circuit for processing input matrix data having a parity for error correction based on the information data and having a format in which information data has an error detection code, a buffer memory for storing the input matrix data; In parallel with the writing, a first operation unit for performing an operation for error detection using an error detection code of the input data and storing the operation result in a built-in register, and an operation of the first operation unit in parallel, performed using the parity syndrome calculation of the input matrix data, the internal and the syndrome calculation result Independently writing or reading in the stomach
A second operation unit that temporarily stores the data in one of the operating first and second memory units; and a second operation unit that performs a parallel operation on the input matrix data on which the syndrome operation is performed by the second operation unit. And calculates the syndrome operation result of the immediately preceding input matrix data in a second operation unit.
It is determined whether or not the error is corrected by reading from the other of the built-in first and second memory units. If the error is corrected, the buffer memory of the buffer memory is determined based on the error position and error pattern indicated by the read syndrome operation result. correct the error data read from a predetermined address have a error correction processing unit for writing to the same address, first
And the second memory unit,
Temporary storage and syndrome of previous input matrix data
And the reading of the calculation result are performed alternately.
When the other memory is temporarily storing
In this configuration, the reading section performs reading .

According to the present invention, when the matrix data read from the recording medium is written into the buffer memory, an operation for error detection by the first operation unit and a second operation are performed on the input matrix data. Simultaneously with the syndrome operation by the section, the result is stored internally, and at the time of correction processing, the syndrome operation result is read from the memory storing the syndrome operation result, and error correction is performed by the error correction processing section, and the corrected data is corrected. If there is, read data at a predetermined address in the buffer memory,
Correct and write. Further, it corrects the operation result of the first operation unit and also corrects the syndrome operation result of the second operation unit. Thus, in the present invention, access to the buffer memory is performed only when the matrix data is actually correctable data and the data is corrected.

Further, according to the present invention, when an error is corrected by the above-described error correction processing unit, the operation result of the register built in the first operation unit is corrected based on the error position and error pattern indicated by the syndrome operation result. It is characterized by the following.

Further, according to the present invention, the matrix data is provided in two directions, a first direction and a second direction, for error correction based on information data in the respective directions.
When the error correction is performed by the error correction processing unit, the error correction processing unit corrects the read syndrome operation result, and converts the data string in the first direction or the second direction into the second direction. Alternatively, a column conversion circuit for converting the data into a data string in the first direction is provided, and the error pattern is supplied to the second calculation unit from the error position after the column conversion output from the column conversion circuit to correct the syndrome calculation result. It is characterized by the following.

Further, according to the present invention, the input matrix data stored in the buffer memory is input to the first arithmetic unit and the second arithmetic unit, respectively, or the error correction after column conversion output from the error correction processing unit is performed. A selector for selectively inputting the result to the second arithmetic unit;

Further, the present invention relates to the first aspect of the present invention.
The arithmetic unit that takes in the input matrix data and performs an arithmetic operation using an error check code, a gate circuit, and a load signal through the gate circuit after the arithmetic operation of the arithmetic unit is completed and before the next matrix data is read. A built-in register into which the operation result of the arithmetic unit is loaded, a correction circuit that generates a correction pattern according to a signal indicating an error pattern from the error correction processing unit, and a register stored in the register based on the register value and the correction pattern. And an adder circuit for correcting the operation result of the operation unit.

Furthermore, the present invention, the second calculation unit in the first aspect of the present invention, the first and second memory part, and the calculation means to perform the syndrome calculation, select signal toggles each input matrix data , Control signals such as an address to the first and second memory units, a write signal, a read signal, and the like, one of the first and second memory units is used for error correction, and the other is used as a syndrome. A switching circuit is used for calculation and has a switching circuit for alternately switching the assignment in units of input matrix data.

[0026]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a data processing circuit according to the present invention. The data processing circuit according to the present embodiment is a data processing circuit provided in a reproducing apparatus for an optical disk or the like, and includes a data processing unit 1 and a buffer RAM 2, both of which are a bidirectional memory bus 1
1 connected. The data processing unit 1 includes a syndrome calculation unit 3, a CRC calculation unit 6, an error correction processing unit 8, and a selector 10.

The syndrome calculation section 3 performs a syndrome calculation directly on data read from a recording medium (not shown) and stores two sets of Rs for storing the result of the syndrome calculation.
AM4 and AM5, the result of the syndrome operation is stored in the RAM4 (or 5), and the result of the syndrome operation of the immediately preceding matrix data used for error correction is stored in the RAM5 (or 4). I do.

The CRC operation unit 6 has a register 7 for performing a CRC operation on the data to be written to the buffer RAM 2 and storing the result of the CRC operation. The error correction processing unit 8 performs an error correction process based on the syndrome operation result of a certain P column (or Q column), and when performing the error correction, the error pattern is changed to the previous P column (or Q column).
Column conversion circuit 9 for converting into a Q column (or a P column) overlapping the column
have. The data subjected to the CRC operation is stored in the register 7 before the next matrix data is input. The selector 10 switches input data to the syndrome operation unit 3 at the time of error correction and at the time of data input.

Here, the matrix data stored in the buffer RAM 2 will be described. As shown in FIG. 2, the information data 12 is data (matrix data) arranged in a matrix of a bytes in the horizontal direction (for example, this is Q column) and b bytes in the vertical direction (this is P column). ), (C−a) -byte error correction data 13 is generated based on the a-byte information data in the Q column, added to the Q column, and (d−b) based on the b-byte information data in the P column. b) Byte error correction data 14 is generated and added to the P column, and as a whole, data of c bytes in the Q column and d bytes in the P column are arranged in a matrix. An EDC code is inserted at the end of the information data 12. The error correction data 13 is called a Q parity and the error correction data 14 is called a P parity. For example, the error correction data 13 is a parity of a Reed-Solomon code, and is generated based on information data in the same column direction. The EDC code is a parity of a CRC code generated based only on information data.

The matrix data read from the recording medium is used for demodulating data according to the standard of the medium.
After performing processing specific to each data processing procedure, the data is written to the buffer RAM 2 via the memory bus 11.
And the syndrome operation unit 3 performs a syndrome operation using the information data and P parity of the P column and the information data and Q parity of the Q column, respectively. Only the information data including the EDC code is subjected to the CRC operation by the CRC operation unit 6. You.

The buffer RAM 2 switches alternately for each of the above matrix data. The error correction process reads data from the RAM 5 (or 4) storing the syndrome operation result of the immediately preceding matrix data,
The processing is performed by the error correction processing unit 8. At this time, if there is a correction, the error pattern and the error position with respect to the P column (or the Q column) are obtained, the address of the error data in the buffer RAM 2 is obtained therefrom, this data is read, corrected and written.

In addition to correcting the syndrome operation result of the P column (or Q column), the column conversion circuit 9 converts the error position of the P column (or Q column) to the corresponding Q column (or P column).
Column, and corrects the syndrome operation result of column Q (or column P).

FIG. 3 is a block diagram showing an embodiment of the syndrome calculation section 3 shown in FIG. Syndrome operation unit 3
Is an XOR circuit group 15 for performing a syndrome operation,
Two sets of RAMs 4 and 5 for storing the values, a switching circuit 16 for switching control signals such as an address for error correction and a syndrome operation of the RAM, a write signal, a read signal, etc. by a select signal toggling for each matrix data; Consists of The number of words in the RAMs 3 and 4 is equal to the sum of the total number of P columns and the total number of Q columns.
There are as many as the number of syndromes in the row, and there are two sets.

FIG. 4 is a block diagram showing an embodiment of the CRC calculation unit 6 shown in FIG. As shown in FIG. 4, the CRC operation unit 6 receives information data written from the recording medium to the buffer RAM 2 and performs a CRC operation on the CRC operation unit 19.
The error data is found in the gate circuit 20, the register 7 in which the CRC operation result is loaded via the gate circuit 20 by the load signal by the load signal before reading the next matrix data after the CRC operation is completed, and the error correction processing unit 8. And CRC according to the error pattern and error position
It comprises a CRC operation correction circuit 17 for generating a correction pattern, and an XOR circuit 18 for correcting the CRC operation based on the value of the register 7 and the CRC operation correction pattern. From the above,
The CRC calculation result is corrected, and finally, when the error correction is completed, the error can be correctly detected as the CRC calculation result.

Next, the operation of this embodiment will be described. First, the operation of the data processing unit 1 for data written to the buffer RAM 2 will be described with reference to the flowchart of FIG. The matrix data reproduced and demodulated from the recording medium usually has an address indicating the data, and is sequentially written into the buffer RAM 2 in units of matrix data, that is, in units of matrix data of addresses n-1, n, and n + 1. Data to be written to the buffer RAM 2 is sequentially input to the data processing unit 1 as it is in the order of n-1, n, and n + 1.

Assuming that the matrix data at the address n + 1 is input to the buffer RAM 2 (step 201), the matrix data is stored in the selector 1
0, is supplied to the syndrome calculation unit 3 and is subjected to a syndrome calculation (step 202). In parallel with this, it is supplied to the CRC calculation unit 6 through the selector 10 and is subjected to a CRC calculation (step 203).
It is stored in AM4 (or 5) (step 204).
These operations are repeated until the end of the n + 1 matrix data (steps 205, 201 to 204).

Immediately before the next n + 2 matrix data is input, the CRC operation result is stored in the register 7 by the load signal (step 206). The RAMs 4 and 5 are switched by a signal that toggles for each matrix data, and the RAM 4 (or 5) that has been input so far, that is, the RAM 4 (or 5) that has stored the syndrome operation result for the n + 1 matrix data is used for error correction. Then, the other RAM 5 (or 4) is used for storing the syndrome operation result.

Here, when the syndrome operation and the CRC operation of the matrix data at the address n + 1 are performed as described above, the error correction processing is performed on the matrix data at the previous address n in parallel. 8 is performed. That is, the error correction of the matrix data at the address n is performed in the buffer RAM 2
Without reading the matrix data at the address n from the RAM 5, the syndrome calculation results are sequentially read from the RAM 5 (or 4) storing the syndrome calculation results of the matrix data at the address n (step 301), and sent to the error correction processing unit 8, Whether or not the error correction processing unit 8 performs error correction is first determined based on the syndrome operation result (step 302).

If there is an error in the P column (or Q column), the error data is read from a predetermined address of the buffer RAM 2 storing the matrix data of the address n from the error position and the error pattern and corrected. Is written again (step 303). RAM5
The address at which the syndrome operation result of the P column (or Q column) just read from (or 4) is stored is accessed to correct the syndrome operation result (step 304), and the P column (or Q column) is corrected. Q corresponding to
A column (or P column) is obtained by the column conversion circuit 9 (step 305). This column conversion output is input to the syndrome operation unit 3 through the selector 10, where the result of the syndrome operation of the Q column (or the P column) is corrected (step 3).
06).

The column conversion output is output to the CRC operation unit 6
Do not use. Further, without passing through the selector 10 from the error correction processing unit 8, the data is stored in the CRC calculation result storage register 7 based on the signal indicating the error pattern and the error position supplied to the CRC calculation correction circuit 17 in FIG. 4. The CRC operation result that has been corrected is also corrected (step 30).
7). This CRC calculation result is used to confirm whether or not the error-corrected matrix data has an error (the error pattern and the error position are unknown).

On the other hand, in step 302, the P column (or Q
When it is determined that there is no error in the column (column), it is determined whether the data is read data of the last column (step 30).
8) If it is not the last column, the operation after step 301 is repeated again, and if it is the last column, the process is terminated.

With the above operation, the addresses n-1, n, n + 1 are stored in the buffer RAM 2 as shown in the schematic diagram of FIG.
When the matrix data is sequentially written, the syndrome operation and the CRC operation are simultaneously performed as n−1, n, and n + 1 using the same matrix data, and the error correction operation and the CRC correction operation are performed in parallel. The processing is sequentially performed with the previous addresses n-2, n-1, and n.

That is, since the error correction operation is performed in parallel with the syndrome operation and the CRC operation,
At the time of reading one matrix data, only the correction operation needs to be performed on the matrix data on which the syndrome calculation and the CRC calculation have been completed. That is, since the syndrome operation, the CRC operation, and the error correction operation are processed in the pipeline, the error correction time including the syndrome operation and the CRC operation can be reduced.

In this embodiment, the buffer RA
Since M2 is accessed only when corrected data is generated, the occupancy of the memory bus 11 of the buffer RAM 2 can be suppressed and the current consumption can be reduced.

The present invention is not limited to the above embodiment. For example, the matrix data can be applied to the case where only one of the P and Q columns has error check data. It goes without saying that the error check code described above can also be used. Further, the column directions of the P and Q columns of the matrix data are vertical and horizontal in FIG. 2, but either one of them may be oblique.

[0046]

As described above, according to the present invention,
When the matrix data read from the recording medium is written into the buffer memory, an operation for error detection by the first arithmetic unit and a syndrome operation by the second arithmetic unit are simultaneously performed on the input matrix data. Then, the result is stored internally, and for the input matrix data on which the syndrome operation has been performed by the second operation unit, the syndrome operation result of the immediately preceding input matrix data is read out from the built-in memory to generate an error. Judgment is made as to whether or not to correct the data. If there is corrected data, data at a predetermined address in the buffer memory is read, corrected and written, so that only one error correction process is required during the time when one matrix data is input. , Access to buffer memory can actually correct matrix data Since it was only used to correct data when it was data, use of the memory bus was minimized, and there was no waiting time when transferring data in the buffer memory to the host (such as a personal computer), resulting in transfer. Speed can be increased. Further, according to the present invention, the number of accesses to the buffer memory is reduced,
Current consumption can be reduced.

Further, according to the present invention, a column conversion circuit is also provided for data having a format in which the data format has parity for error correction in one direction of the matrix data and has an error check code for the matrix data. Can be realized only by deleting the.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a format diagram of an example of matrix data applied to the present invention.

FIG. 3 is a block diagram of an embodiment of a syndrome calculation unit in FIG. 1;

FIG. 4 is a block diagram of an embodiment of a CRC calculation unit in FIG. 1;

FIG. 5 is a flowchart for explaining the operation of FIG. 1;

FIG. 6 is a schematic diagram for explaining the operation of FIG. 1;

FIG. 7 is a block diagram of an example of the related art.

FIG. 8 is a flowchart for explaining the operation of FIG. 7;

FIG. 9 is a schematic diagram for explaining the operation of FIG. 7;

FIG. 10 is a block diagram of another conventional example.

FIG. 11 is a schematic diagram for explaining the operation of FIG. 10;

FIG. 12 is a block diagram of another example of the related art.

[Explanation of symbols]

 Reference Signs List 1 data processing unit 2 buffer RAM 3 syndrome operation unit 4, 5 syndrome operation result storage RAM 6 CRC operation unit 7 CRC operation result storage register 8 error correction processing unit 9 column conversion circuit 10 selector 15 XOR circuit group 16 switching circuit 17 CRC operation correction circuit 18 XOR circuit 19 CRC operation unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 13/00 G06F 11/10 330 G11B 20/00

Claims (6)

(57) [Claims] The information data reproduced from a recording medium has a parity for error correction based on the information data in one or two directions of the information data arranged in a matrix. In a data processing circuit for processing input matrix data in a format having an error detection code, a buffer memory for storing the input matrix data, and in parallel with writing the input matrix data in the buffer memory, A first operation unit that performs an operation for error detection using an error detection code, and stores the operation result in a built-in register; and, in parallel with the operation operation of the first operation unit, the input matrix data Is performed by using the parity, and the result of the syndrome calculation is stored independently of each other.
The first and second memories that perform a write or read operation
A second operation unit that temporarily stores the data in one of the memory units; and a syndrome draw for the input matrix data on which the second operation unit performs the syndrome operation.
In parallel with the system operation, the result of the syndrome operation of the immediately preceding input matrix data is stored in the second operation unit.
It is determined whether the error is corrected by reading from the other of the first and second memory units. If the error is corrected, a predetermined value in the buffer memory is determined based on the error position and error pattern indicated by the read syndrome operation result. possess an error correction processing unit for writing correct the error data read from the address to the same address, the first
And the second memory unit,
Temporary storage of results and the previous input matrix data
When reading out the result of the syndrome operation alternately
In both cases, when one memory unit is storing the temporary memory
Is a data processing circuit wherein the other memory unit performs the reading . 2. The method according to claim 1, wherein the error correction processing section corrects an operation result of an internal register of the first operation section based on an error position and an error pattern indicated by the syndrome operation result when correcting the error. The data processing circuit according to claim 1, wherein: 3. The format in which the matrix data has first and second parities for error correction based on information data in two directions of a first direction and a second direction, respectively. When performing error correction, the error correction processing unit corrects the read syndrome operation result, and corrects the error in the first direction or the second direction.
A column conversion circuit for converting the data sequence in the direction of the second direction into a data sequence in the second direction or the first direction, and the error correction result after the column conversion output from the column conversion circuit is converted into the second operation unit 2. A data processing circuit according to claim 1, wherein said data processing circuit corrects the result of the syndrome operation by supplying the result to the control circuit. 4. The apparatus according to claim 1, wherein input matrix data stored in said buffer memory is input to said first and second operation units, respectively, or said column-corrected error correction output from said error correction processing unit is output. 4. The data processing circuit according to claim 3, further comprising a selector for selectively inputting a result to the second arithmetic unit. 5. The first arithmetic unit fetches the input matrix data, performs an arithmetic operation using the error check code, a gate circuit, and completes the arithmetic operation of the arithmetic unit and outputs the next matrix data. The built-in register into which the operation result of the arithmetic unit is loaded via the gate circuit by a load signal before reading the data, and a correction circuit that generates a correction pattern according to a signal indicating an error pattern from the error correction processing unit. 2. The data processing circuit according to claim 1, further comprising an adder circuit for correcting an operation result of said operation unit stored in said register based on a value of said register and said correction pattern. 6. The second operation unit, wherein the first and second calculation units are
Memory unit and arithmetic means for executing a syndrome operation
And control signals such as an address to the first and second memory units, a write signal, a read signal, etc., are switched by a select signal toggling for each of the input matrix data,
One of the first memory unit and the second memory unit is used for error correction, and the other is used for syndrome calculation, and a switching circuit for alternately switching the assignment in units of the input matrix data is provided. The data processing circuit according to claim 1, wherein: