JP3246926B2 - Error correction processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction processing apparatus for adding an error correction code and detecting an error using a triple Reed-Solomon code.

[0002]

2. Description of the Related Art In recent years, a digital audio tape recorder (hereinafter, referred to as DAT) records and reproduces digital data transferred from a computer instead of a digitized audio signal, so that the DAT can be used as a computer external storage device. Is being developed. In these devices, a third error correction code, which is a code sequence of digital data over a plurality of tracks, is added in addition to an error correction code in track units used at the time of recording and reproduction of an audio signal, so that at the time of recording and reproduction of digital data, Reliability is being enhanced. In the correction processing using the third error correction code, the error correction processing is efficiently performed by using the erasure information of each data by the error correction processing common to the audio.

[0003] A conventional error correction processing device will be described below. FIG. 15 shows a block diagram of a conventional error correction processing device. In the figure, a data reproducing unit 1 reproduces digital data from a magnetic medium and performs an error correction process common to the case of a digital audio signal, and its output is given to a data receiving unit 2 and a flag receiving unit 3. . The data receiving unit 2 receives the reproduced code data, and the flag receiving unit 3 receives the erasure flag added to the code data. On the other hand, the data memory 4 stores code data, and the flag memory 5 stores an erasure flag. Pieces reads erasure flags to code each sequence from the individual lost position calculating unit 6 flag memory 5
It calculates a separate erasure position, the output is given to the correction matrix calculation unit 7. The correction matrix calculation unit 7 calculates a correction matrix for each code sequence from the individual erasure position, and its output is provided to the correction processing unit 8. A correction processing unit 8 calculates a syndrome of one code sequence,
And a correction unit 10 that calculates an error pattern from the syndrome output from the syndrome operation unit 9 and the correction matrix and performs erasure correction. The memory management unit 11 manages access to the data memory 4 and the flag memory 5 according to instructions from the data reception unit 2, the individual erasure position calculation unit 6, the correction processing unit 8, the data output unit 12, and the like. A data output unit 12 for outputting data with the error corrected,
The control unit 13 controls operations of the correction matrix calculation unit 7, the correction processing unit 8, and the memory management unit 11.

[0004] The operation of the error correction processing apparatus configured as described above will be described with reference to FIG. FIG. 16 shows the control unit 13
Is a flowchart showing an operation procedure in which the error correction is performed by the following. When the operation is started, first, in step 21, the memory management unit 11 is controlled to store the reproduction code data of the entire code sequence received via the data reception unit 2 in the data memory 4 via the data bus 2a. At this time, the data reproducing unit 1 outputs an erasure flag for the coded data that could not be corrected by the common error correction processing with the audio data. The control unit 13 similarly controls the memory management unit 11,
The erasure flag of the code data received from the flag receiver 3 is stored in the flag memory 5 via the line 3a. The code data of the data memory 4 and the disappearance flag of the flag memory 5 are managed as two-dimensional data in a matrix shown in FIG. 3 described later, and are sequentially stored in the row direction. Each code sequence is configured in the column direction, with the row number being the code position and the column number being the code sequence number.

At step 22, the code sequence number is cleared and error correction processing is initialized. And step 23
The control unit 13 controls the memory management unit 11 to read out the erasure flag in the code sequence indicated by the code sequence number from the flag memory 5. Then, in the next step 24, the individual erasure position calculation unit 6 calculates the individual erasure position of the code sequence. Proceeding to step 25, the number of coded data with the erasure flag (hereinafter referred to as the erasure number) is checked, and if the erasure number is within a specified range, the flow advances to step 26 to control the correction matrix operation unit 7, and the obtained value is obtained. A correction matrix is calculated based on the individual erasure positions. Then, in the next step 27 and thereafter, the correction processing unit 8 is controlled to execute syndrome calculation, error pattern calculation, and error correction of one code sequence. That is, in step 27, the syndrome operation unit 9 of the correction processing unit 8 sequentially reads out the code sequence data indicated by the code sequence number via the memory management unit 11, and calculates the syndrome from the information bit and the check bit value. Then, in step 28, the correction unit 10 detects an error pattern from the syndrome and the correction matrix obtained in step 27. Correction unit 10
Corrects the code data at the code position indicated by the specific individual erasure position in the next step 29.

As described above, the error correction of one code sequence is performed. In the following step 30, the code sequence number is incremented. In step 31, the error correction of steps 23 to 30 is performed until the error correction processing of all other code sequences is completed. Repeat the process,
Error correction of all code data is executed one by one. After the error correction for all code sequences is completed, the process proceeds to step 32, where the corrected data is output via the data output unit 12, and the process is completed.

Next, if the number of erasures of the code data exceeds the correction capability of the correction processing unit 8 in step 25, the process proceeds to step 33, in which the same data is reproduced again from the recording medium as uncorrectable and error correction is attempted. Post processing such as reread transfer setting is performed, and the entire processing ends.

Here, the error correction processing will be described with reference to an actual correction example. For example, considering the error correction of the code sequence A shown in FIG. 3, the erasure flags of the code sequence A are sequentially read out from the flag memory 5 as the correction processing, and the code positions # 03, # 40, and # 62 with the erasure flags are set as the erasure positions. To detect. A correction matrix [H] is calculated based on this lost position. Subsequently, the code data of the code sequence A is sequentially read from the data memory 4, and the syndrome [S] is calculated. As shown by the following equation (1), an error pattern [Y] is obtained from the correction matrix [H] and the syndrome [S], and an error of data specified at the erasure position is corrected. Error pattern [Y]
Is obtained from the syndrome [S] and the correction matrix [H] by the following equation. [Y] = [H] [S] (1) By executing such processing on the code sequence B and all other code sequences, errors in all code data can be corrected.

[0009]

However, in such a conventional configuration, the erasure flag is read from the flag memory every time the error correction of one code sequence is executed, and the erasure position is detected. The matrix is calculated every time a code sequence is calculated. For this reason, firstly, a large amount of processing time is required for reading out the flag memory and calculating the correction matrix, secondly, a large memory capacity is required to store the erasure flag, and thirdly, Fourth, it is necessary to have high-speed hardware for calculating the correction matrix. Fourth, it is determined whether the number of erasures of the code data is calculated for each code sequence, whether or not the correction limit of the error correction device is exceeded. There was a problem of not doing so.

The present invention has been made in view of such a conventional problem. First, a correction process can be performed at a high speed, and second, an efficient correction process can be performed with a small memory capacity without deteriorating the correction capability. Thirdly, it is an object of the present invention to provide an error correction processing device capable of executing an accurate correction process and determining whether the correction capability is exceeded before the start of the correction process.

[0011]

According to a first aspect of the present invention, there is provided a data receiving section for receiving code data including an error correction code, a code data storage section for storing the received code data, A flag receiving unit that receives an erasure flag indicating whether there is an error or has a pseudo code in which a code error portion is inferred from previous and subsequent data by analogy, from the code data and receives the erasure flag;
When the code position is changed to the same code position in all code sequences,
The location information treated as existing is defined as the common vanishing location,
Common based on the reception order of the erasure flags corresponding to each code position
The common erasure position calculation unit for calculating the erasure position, and correction matrix calculation unit for calculating a correction matrix of the original code data from a common lost position calculated from the common erasure position calculating unit, which is calculated from a common lost position calculating unit common Erasure position and correction matrix operation
And a correction processing unit that performs an erasure correction process at the same erasure position on the entire code sequence of the received code data based on the correction matrix calculated by the unit .

According to a second aspect of the present invention, there is provided a data receiving section for receiving code data including an error correction code, a code data storage section for storing the received code data, a flag receiving unit for receiving and separating the erasure flag indicating whether a pseudo code that analogy complement error portion from the longitudinal data from the code data, one or more
The code position with the erasure flag in the above code sequence is
Assuming that an error exists at the same code position in the sequence
The position information to be handled is a common erasure position, and
Calculating a common erasure position based on the received order of the erasure flags, a common erasure position calculation unit, and a code position with the erasure flag
For each code sequence based on the reception order of the erasure flags.
Therefore, an individual erasure position calculation unit that calculates an individual erasure position for each code sequence, and an original coded data from the common erasure position or the individual erasure position.
A correction matrix calculation unit for calculating the over data correction matrix, the common loss
Same erasure for all code sequences based on position correction matrix
The operation of performing position erasure correction processing is set to a common correction mode,
Each code sequence is based on the correction matrix for the individual erasure position.
The operation to perform the erasure correction processing of the erasure position is called the individual correction mode.
When to perform, either common correction mode or individual correction mode
A correction processing unit that performs error correction processing, the common correction mode
And a correction processing selecting means for instructing the correction processing unit to select one of a correction mode and an individual correction mode .

[0013] The invention of claim 3 of the present application has erasure number counting means for counting the number of data to be corrected indicated at the common erasure position, and the correction processing selection means includes the erasure number and the erasure correction of the error correction code. Compare the abilities, select the common correction mode of the common erasure position calculation unit and the correction processing unit when the correction abilities are within the range, and set the individual correction mode of the individual erasure position calculation unit correction processing unit when the correction limit is exceeded. It is a feature that is selected.

The invention of claim 4 of the present application is directed to claim 2
In the error correction processing unit has a processing speed switching means for switching between a high-speed error correction processing and slow error correction processing, correction processing selection means, correction processing when the high-speed processing is set
And selecting an individual correction mode of the correction processing unit when the common correction mode of the processing unit is selected and the low-speed processing is set.

According to a fifth aspect of the present invention, there is provided a data receiving section for receiving code data including an error correction code, a code data storage section for storing the received code data, a flag receiving unit for receiving and separating the erasure flag indicating whether a pseudo code that analogy complement error portion from the longitudinal data from the code data, loss off
The code position with the lag is determined based on the reception order of the erasure flag.
The individual erasure positions for each code sequence are obtained individually for each code sequence.
An individual erasure position calculation unit for calculating, an individual erasure position storage unit for temporarily storing an individual erasure position, and an individual erasure position calculation unit
And a correction processing unit that performs erasure correction processing for each erasure position for each code sequence based on the individual erasure positions calculated from, and the correction matrix .

According to a sixth aspect of the present invention, there is provided a data receiving unit for receiving code data including an error correction code, a code data storage unit for storing the received code data, A flag receiving unit that separates and receives from the code data an erasure flag indicating whether or not a pseudo code has an error part supplemented by analogy from preceding and succeeding data, and a code data storage unit that stores the code data and the erasure flag as one word at the same address And when reading the code data of each code sequence from the code data storage means, an individual erasure position calculation unit that calculates an individual erasure position based on the erasure flag that is read at the same time, and a correction calculated from the individual erasure position. And a correction processing unit that performs erasure correction processing of each erasure position for each code sequence based on the matrix and the individual erasure positions.

According to a seventh aspect of the present invention, there is provided a data receiving section for receiving code data including an error correction code, a code data storage section for storing the received code data, a flag receiving unit for receiving and separating the erasure flag indicating whether a pseudo code that analogy complement error portion from the longitudinal data from the code data, one or more
The code position with the erasure flag in the above code sequence is
Assuming that an error exists at the same code position in the sequence
The position information to be handled is the common erasure position, and the number of common erasure positions
Erasure flag is input when the erasure flag is input, a correction matrix operation unit that calculates the correction matrix of the original code data from the common erasure position, and the count value of the common erasure number counter is erased.
Detects that it is impossible to correct the data when the uncorrectable capacity is exceeded
And uncorrectable detector that is calculated from a common lost position calculating unit
Common erasure position and the correction calculated by the correction matrix operation unit.
Based on the positive matrix, the entire code sequence of the received code data
And a correction processing unit for performing erasure correction processing at the same erasure position .

[0018] the invention of claim 8, of claim 1, wherein
In the error correction processor, the code data with the erasure flag
Data sequence based on the reception order of the erasure flag.
Number calculated for each code sequence and calculated as the number of individual erasures for each code sequence
The count values of the separate lost number counting unit and the individual lost number counting unit
Detects that it is impossible to correct the data when the uncorrectable capacity is exceeded
And an uncorrectable detection unit .

[0019]

According to the first aspect of the present invention having such a feature, the common erasure position calculation unit calculates the common erasure position, and performs correction processing assuming that there is erasure data at the erasure position common to all code sequences. I do. Then, the code data is corrected at high speed by using the same correction matrix operation for all code sequences.

According to the second to fourth aspects of the present invention,
A common erasure position calculation unit that calculates a common erasure position at the time of inputting a flag, or a correction process assuming that there is an error at a different erasure position for each code sequence. Correction processing of the code data is performed by any of the individual erasure position calculation units that calculate the individual erasure position to be performed when the flag is input.

Further, according to the invention of claim 5 of the present application, the individual erasure position is calculated by the individual erasure position calculation unit based on the reception order of the erasure flags input, and the individual erasure position is stored in the individual erasure position storage unit. The code data is temporarily stored, and the code data is corrected for each code sequence using the correction matrix calculated from the individual erasure position.

According to the invention of claim 6 of the present application, the code data storage unit stores the data and the erasure flag as one word, reads out the erasure flag therefrom, calculates the individual erasure position, and executes the correction processing of the coded data. Do.

According to the seventh and eighth aspects of the present invention, the number of code positions of code data is counted by the common erasure number counting unit or the individual erasure number counting unit based on the reception order of the erasure flags. Next, the uncorrectable detection unit compares the output of the common erasure number count value or the individual erasure number count value with the erasure correction capability of the error correction code, and performs code data correction processing.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of the error correction processing device according to the first embodiment of the present invention. The data reproducing unit 1, the data receiving unit 2, the flag receiving unit 3, the correction matrix operation unit 7, the correction processing unit 8, the syndrome operation unit 9, the correction unit 10, the memory management unit 11, the data output unit 12, and the control unit 13 Since the configuration is the same as that of the conventional error correction device, detailed description is omitted. The data reproducing unit 1 receives a signal from a recording medium and performs an error correction process common to audio data.
And the flag receiving unit 3. The flag receiving unit 3 receives the erasure flag of the code data, and its output is provided to the transfer counter 40 and the common erasure position calculation unit 45. The transfer counter 40 monitors the input order of the flag data, and its configuration is shown in FIG.

As shown in FIG. 4, the transfer counter 40 comprises a row counter 41, a column counter 42, and a row maximum value detecting section 43. The row counter 41 counts the row number of the code data including the erasure flag shown in FIG. 3 by a count-up signal, and outputs the row position of the code sequence including the erasure flag. When the count value of the code data in the row direction becomes the maximum value by the row counter 41, the row maximum value detection unit 4
3 clears the row counter 41 and the column counter 4
2 is incremented. The column counter 42 counts the column number of the code data and outputs the output as code position data. Here, the data of the row position and the column position including the erasure flag of the transfer counter 40 are given to the common erasure position calculation unit 45. The common erasure position calculation unit 45 calculates the common erasure position of the code data having the erasure flag from the output value of the transfer counter 40, and the output is provided to the correction matrix calculation unit 7. The correction matrix operation unit 7 calculates data of a common erasure correction matrix from a common erasure position.
The output is provided to the correction processing unit 8. The correction processing unit 8 includes a syndrome calculation unit 9 and a correction unit 10. The syndrome calculation unit 9 calculates a syndrome value using information bits and check bits of each code sequence, and provides the result to the correction unit 10. The correction unit 10 calculates an error pattern from the syndrome value from the syndrome operation unit 9 and the correction matrix from the correction matrix operation unit 7 and performs erasure correction.

On the other hand, the data receiving section 2 receives the reproduced code data, and its output is a data bus 2a.
To the syndrome operation unit 9, the correction unit 10, the data output unit 12, and the memory 46. The control unit 13 controls the operations of the correction matrix calculation unit 7, the correction processing unit 8, and the memory management unit 11, and outputs the corrected data from the data output unit 12 according to the operation procedure as described later. It manages blocks. The memory management unit 11 includes a data reception unit 2, a correction unit 10, a syndrome operation unit 9,
The control unit 13 and the data output unit 12 input and output control signals, respectively, and manage code data in the memory 46. The memory 46 receives an instruction from the memory management unit 11 and
This is a code data storage unit that stores reproduced code data output from the data receiving unit 2 as two-dimensional code data shown in FIG.

The operation of the thus configured error correction processing device of the first embodiment will be described with reference to FIGS. FIG. 2 is a flowchart illustrating an operation procedure in which the control unit 13 performs error correction. First, step 51
And controls the memory management unit 11 to store the reproduction code data received via the data reception unit 2 in the memory 46.
The code data in the memory 46 is two-dimensional code data as shown in FIG. The transfer order of the code data is performed in the row direction, and one column of data forms one code sequence. Further, the data reproducing unit 1 performs common error correction processing with the audio data, and outputs an erasure flag for the code data that could not be corrected by this processing in the same transfer order as the code data. In accordance with the input order of the erasure flags, the transfer counter 40 identifies the matrix position of the two-dimensional data in FIG. The number is calculated as the common erasure position. In the transfer counter 40 of FIG. 4, first, the two-dimensional data is transferred in the row direction. Therefore, the row counter 41 is incremented every transfer and reaches a maximum value, then the row counter 41 is cleared and the column counter 42 is incremented. You. Thus, each counter value indicates a row and column position, that is, a code position and a code sequence number .

Then, the process proceeds to a step 52, wherein the number of rows at the common erasure position (hereinafter referred to as the number of common erasures) is checked.
If the number of disappearances is within the specified range, the process proceeds to step 53. Here, the correction matrix calculation unit 7 is caused to calculate a correction matrix for the common erasure position. When the calculation of the correction matrix is completed, the process proceeds to step 54, where the code sequence number is cleared and the error correction processing unit 8 is initialized. Then, the process proceeds to a step 55, wherein calculation of a syndrome value, error pattern calculation, and error correction are performed from the error two-dimensional data. That is, the syndrome calculation unit 9 sequentially reads out the code data indicated by the code sequence number via the memory management unit 11 and calculates a syndrome value. Then, the correction unit 10 calculates an error pattern from the obtained syndrome value and the correction matrix, and corrects the code data at the code position indicated by the erasure position. When the error correction of one code sequence is executed, the process proceeds to step 56, where the code sequence number is incremented, and the processes of steps 55 and 56 are repeated until the error correction process of all code sequences is completed.
Executes error correction for all code data. After the errors of all the code data have been corrected in step 57, the process proceeds to step 58, where the memory management unit 11 is controlled to output the corrected code data via the data output unit 12, and the process ends.
If the erased number exceeds the correction capability in step 52, the process proceeds to step 59, in which the correction is disabled and the process is terminated.

A description will now be given of an example of a correction process based on a common erasure position. In the two-dimensional data shown in FIG. 3, the erasure flag is attached to code positions # 03, # 40, and # 62 in code sequence A, and code positions # 03, # 11, and # in code sequence B.
It is assumed that an erasure flag has been attached to 40, and that other code sequences have no erasure flag. In this case, looking at the entire code, code positions # 03, # 11, # 40, # 62
Is a code position with at least one erasure flag. As the common erasure position, the code position 11 to which the erasure flag is not attached in the code sequence A is also treated as the erasure position. Similarly, a code sequence without any erasure flag is also treated as having erasure positions 03, 11, 40, and 62. Therefore, in this correction processing, the erasure correction processing is performed on the assumption that there is an error at the same erasure position in all code sequences. In this case, since the erasure position is the same for all code sequences, the calculation of the correction matrix can be performed only once. Further, since the disappearance position is calculated each time the flag is inputted by using the input order of the disappearance flag, the processing time required for calculating the disappearance position can be reduced.

As described above, according to the first embodiment, by providing the common erasure position calculating section for calculating the common erasure position when the erasure flag is input, the erasure position is obtained when the transfer of the code data to the memory is completed. Can be determined, the processing time for calculating the erasure position is not required, and the calculation of the correction matrix can be performed once for all code sequences, so that the error correction processing can be executed at high speed. The correction matrix may be calculated by software.

Next, an error correction device according to a second embodiment of the present invention will be described. FIG. 5 is a block diagram showing the overall configuration of the second embodiment of the present invention. Blocks having the same configuration as in FIG. 1 are assigned the same reference numerals and detailed description is omitted. The difference from FIG. 1 is that the transfer counter 40
And the individual erasure position calculation unit 6 in addition to the common erasure position calculation unit 45
1 and that an individual erasure position storage unit 62 is provided between the individual erasure position operation unit 61 and the correction matrix operation unit 7. The individual erasure position calculation unit 61 is connected to each output terminal of the flag reception unit 3 and the common erasure position calculation unit 45, calculates the erasure position for each code sequence, and outputs the output to the individual erasure position storage unit 62. . Also, the individual erasure position storage unit 6
Numeral 2 stores an individual erasure position, and its output is supplied to a correction matrix operation unit 7. The configuration of the other blocks is the same as that of FIG.

The operation of the thus configured error correction processing device will be described with reference to FIGS. FIG. 6 shows the control unit 1.
3 is a flowchart showing an operation procedure in which error correction is performed by No. 3. When the operation is started, the memory control section 11 is controlled in step 71 so that the reproduction code data received via the data receiving section 2 is stored in the memory 46. At this time, similarly to the first embodiment, the common erasure position calculating unit 45 detects the common erasure position from the input order of the erasure flags. At the same time, the individual erasure position calculation unit 61 is caused to detect the individual erasure position. As shown in FIG. 4, the individual erasure position calculation unit 61 outputs the code sequence number and the code position from the row counter 41 and the column counter 42 of the transfer counter 40 as the erasure number counting means, and outputs the code of the code data with the erasure flag. The position is calculated for each code sequence, and is sequentially stored in the individual erasure position storage unit 62 as an individual erasure position. Then, the number of common erasures is checked. In step 72, it is checked whether or not the number of erasures is within the correction capability range. If the number is within the range, the process proceeds to step 73, and the same common steps as in the first embodiment are performed through the following steps 74 to 78. An error correction process using the erasure position data process is executed.

On the other hand, if the number of common erasures exceeds the correction capability in step 72, the flow advances to step 80 to check the number of individual erasures. If the number of individual erasures is within the correction capability, the process proceeds to step 81, and thereafter, error correction according to the individual erasure position is executed for each code sequence. That is, in step 81, the code sequence number is cleared and the error correction processing unit 8 is initialized. Then, the process proceeds to a step 82, wherein the individual erasure positions of the code sequence are stored in the correction matrix operation unit 7.
And a correction matrix is calculated. At step 83, the error correction processing unit 8 is controlled to calculate the value of the syndrome,
Error pattern calculation and error correction are performed, and error correction of one code sequence is performed. Next, in step 84, the code sequence number is incremented, and in steps 85, 82, 83, and 8 until the error correction processing for all code sequences is completed.
4 is repeated to execute error correction of all code data. After the error of all the code data is corrected, step 78
To control the memory management unit 11 to output the corrected data via the data output unit 12 and end the processing. On the other hand, if the number of individual erasures exceeds the correction capability in step 80, the flow advances to step 86 to make correction impossible and end the process.
Here, in the operation procedure by the control unit 13, step 72 achieves the function of the correction processing selecting means.

Next, switching between the correction processing based on the common erasure position and the correction processing based on the individual erasure position will be described with reference to the correction of the code shown in FIG. 3 as an example. In code sequence A, code position # 0
3, # 40, and # 62 have erasure flags, and code sequence B has erasure flags at code positions # 03, # 11, and # 40. Therefore, the common erasure positions are # 03, # 11, # 4
0, # 62. Here, if it is assumed that the erasure correction capability of the code is 3 at the maximum, the common erasure position becomes 4 in total, and correction by the common erasure position becomes impossible to correct. However, the number of individual erasures of the code sequences A and B is 3, and the individual code sequences are within the correction capability. In this case, the present embodiment does not use the correction process of the common erasure position in such a case,
The correction process is performed based on the individual erasure position. In this case, since it is an individual correction process, a calculation of a correction matrix is required for each code sequence, and the processing speed is deteriorated, but the maximum correction capability can be secured.

As described above, according to the second embodiment, the correction processing selecting means for switching between the correction processing based on the common erasure position and the correction processing based on the individual erasure position is provided. By switching to correction processing by position, high-speed correction processing is performed by the correction processing by the common erasure position up to the maximum limit by the common erasure position, and when the correction processing by the common erasure position is impossible, the correction processing by the individual erasure position is performed. And to ensure that the correction capability is always maximum and high speed.

FIG. 7 is a flowchart showing another operation procedure in which the control section 13 performs error correction. FIG. 7 differs from FIG. 6 in that step 71S is provided between step 71 and step 72, and the processing speed required for the error correction processing device can be appropriately switched. Step 7
When high-speed processing is selected in 1S, error correction of a common erasure position is performed, and high-speed processing is prioritized. If the high-speed processing is not selected, the process proceeds to step 80, where the error correction of the individual erasure position is executed, and the processing speed is sacrificed to speed up the error correction. In FIG. 7, the operation procedure other than step 71S is the same as that in FIG. 6, and the description of the other steps will be omitted. Here, in the operation procedure of the control unit 13, step 71S
Achieves the function of the processing speed switching means.

Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a block diagram showing the overall configuration of the error correction processing device according to the third embodiment of the present invention.
The present embodiment differs from the second embodiment in that the common erasure position calculation unit 45 is not provided. The individual erasure position calculation unit 61 and the individual erasure position storage unit 62 are the same as in the second embodiment,
The description of the configuration of the other blocks of the error correction processing is omitted.

The operation of the thus configured error correction processing device will be described with reference to FIGS. FIG. 9 is a flowchart illustrating an operation procedure in which the control unit 13 performs error correction. First, when the operation is started, step 91 is executed.
To control the memory management unit 11 to store the reproduction code data received via the data reception unit 2 in the memory 41.
At this time, similarly to the second embodiment, the individual erasure position calculation unit 61 detects the individual erasure position from the input order of the erasure flag, and
It is stored in the individual erasure position storage unit 62. Step 9
The process proceeds to step 2 to check the number of individual erasures. If the number of individual erasures is within the correction capability range, the process proceeds to step 83 and thereafter performs error correction according to the individual erasure position for each code sequence as in the second embodiment. (Steps 93 to 99).

Here, the required memory capacity when the individual erasure position is calculated at the time of input of the erasure flag by the individual erasure position calculation unit 61 and stored in the individual erasure position storage unit 62 will be described. For example, a code length of 64 rows and a parity length of 5 shown in FIG.
In the case of a line code format, the individual erasure positions need only be able to be stored in, for example, one having an allowable capacity of five correction limits. Since one erasure position is represented by a numerical value from 0 to 63, 6 bits are required, and storage of the individual erasure position of one code sequence requires 30 bits. On the other hand, in the conventional error correction device, since all erasure flags are stored, 64 bits are required for one code sequence. Therefore, the required memory capacity for recording the individual erasure positions is about half as compared with storing all the erasure flags.

As described above, according to this embodiment, the individual erasure position is calculated simultaneously with the input of the erasure flag, and the individual erasure position is stored instead of the erasure flag. It is. In addition, by checking the number of individual erasures, there is an advantage that an uncorrectable state can be detected before the correction processing is executed.

Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a block diagram showing the overall configuration of the error correction device according to the fourth embodiment of the present invention.
The difference from the third embodiment is that the memory 10 serves as a code data storage unit for storing code data and an erasure flag as one word.
0 is provided, and an individual erasure position calculation unit 101 that reads an erasure flag from the memory 100 and calculates an individual erasure position is provided. Here, the transfer counter 40 shown in FIG. 8 is not required. The output of the flag receiving unit 3 is stored in the memory 100
Is given to the part storing the flag. The erasure flag stored in the memory 100 is provided to the individual erasure position calculation unit 101, and the individual erasure position calculation unit 101 is configured to read the erasure flag and provide the individual erasure position to the correction matrix calculation unit 7. In addition, the memory management unit 11
And controls the data receiving unit 2, the correcting unit 10, the syndrome calculating unit 9, the data output unit 12, and the control unit 13 by input / output signals as in the third embodiment. is there.

The operation of the thus configured error correction processing device will be described with reference to FIGS. 10, 11, and 12. FIG. FIG. 11 is a flowchart showing an operation procedure in which the control unit 13 executes error correction. The difference from the third embodiment is the method of calculating the individual erasure position. When the operation is started, first, in step 111, the memory management unit 11 is controlled to store the reproduced code data received via the data reception unit 2 and the erasure flag received via the flag reception unit 3 as one word in the memory 100. I do. FIG. 12 is an explanatory diagram showing a configuration example of the memory 100. The configuration is such that eight bits of code data and one bit of the erasure flag are stored as one word at the same address.

Next, proceeding to step 112, the code sequence number is cleared. At the next step 113, the memory management unit 11 is controlled to read out the code data of the code sequence indicated by the code sequence number. Let the value be calculated. As shown in FIG.
The code data forming the code sequence is read from the memory 100, whereby the erasure flag recorded as one word is also read at the same time. Individual erasure position calculation unit 10
1 inputs the disappearance flag read out in synchronization with this,
Calculate the individual disappearance position. When these calculations are completed, the routine proceeds to step 114, where the number of erased cells is checked, and if the number is within the correction capability, the routine proceeds to step 115. Thereafter, the same processing as in step 94 of FIG. 9 is performed, and the error pattern calculation and error correction are performed through steps 116 and 117 for performing the same processing as in step 95. Further, the error-corrected data is output through the same procedure steps 118 to 121 as steps 96 to 99.

As described above, unlike the conventional error correction apparatus, the reading of the erasure flag can be performed simultaneously with the execution of the syndrome operation. As described above, according to the present embodiment,
By storing the erasure flag as one word together with the code data and extracting the erasure flag at the time of reading the data of the syndrome operation, the number of times of memory access can be reduced and the correction process can be executed, so that a high-speed correction process can be realized.

Next, a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 13 is a block diagram showing the overall configuration of the error correction processing device according to the fifth embodiment of the present invention. The difference from the first embodiment is that the common erasure number counting unit 130 counts the number of common erasures, which is the number of code positions that have become common erasure positions, and the correction capability setting for writing the maximum allowable erasure number that is the code correction limit. That is, a unit 131, a common erasure number counting unit 130, and an uncorrectable detection unit 132 that detects uncorrectable by comparing with the maximum correction capability are provided. The output of the common erasure position calculation unit 45 is provided to the common erasure number counting unit 130, and the correction capability setting unit 13 controlled by the control unit 13
The output of 1 is provided to the uncorrectable detection unit 132 together with the common erasure number counting unit 130. The output of the uncorrectable detection unit 132 is provided to the control unit 13. However, the configuration of the blocks other than the above-described units is the same as that of the first embodiment, and a description thereof will be omitted.

The operation of the thus configured error correction processing device of the fifth embodiment will be described with reference to FIG. First, the control unit 13 writes the maximum allowable number of erasures in the correction capability setting unit 131 in advance, and clears the common erasure number counting unit 130 in advance. Subsequently, the code data and the erasure flag are received in the same manner as in the first embodiment, and the common erasure position calculation unit 45 calculates the common erasure position at the same time as the reception of the erasure flag. At this time, the common erasure position calculation unit 45 generates a count pulse every time a code position that becomes a common erasure position is generated.
Output to 0. The uncorrectable detection unit 132 always compares the value of the common erasure number counting unit 130 with the maximum allowable erasure number written in the correction capability setting unit 131, and immediately when the maximum allowable erasure number is exceeded, the control unit 13 determines that the correction is impossible. Output. As a result, the control unit 13 immediately determines that the data cannot be corrected and performs processing such as rereading.

Next, a sixth embodiment will be described. FIG.
FIG. 19 is a block diagram showing a configuration in which the number of individual erasures is counted in place of the number of common erasure positions in the fifth embodiment, and an uncorrectable state is detected. The difference from the fifth embodiment is that the flag receiving unit 3
And an individual erasure position calculating unit 61 for receiving a signal from the transfer counter 40. The individual erasure position calculation unit 61 is the same as that shown in the third embodiment, and its output is provided to the individual erasure position storage unit 62 as in the third embodiment. Also, the output of the individual erasure position calculation unit 61 is the individual erasure number counting unit 1
35, and the number of disappearance flags is counted. This count result is stored in the individual erased number memory 136. On the other hand, as in the fifth embodiment, the correction capability setting unit 131
The control unit 13 sets the maximum allowable number of disappearances. The uncorrectable detection unit 132 includes the individual erasure number counting unit 13
The count value of 5 is compared with the maximum allowable erasure number written in the correction capability setting unit 131, and when the maximum allowable erasure number is exceeded, an uncorrectable signal is output to the control unit 13.
The configuration of the other blocks is the same as that shown in the fifth embodiment, and a description thereof will be omitted.

First, the individual erased number memory 136 is cleared. Every time a code position having an erasure flag is detected, the individual erasure position calculation unit 61 reads the number of erasures of the corresponding code sequence from the individual erasure number memory 136, increments it, and writes it again. The uncorrectable detection unit 132 always sets the value of the individual erasure number counting unit 135 and the correction capability setting unit 131
Is compared with the maximum allowable number of erasures, and when the maximum allowable number of erasures is exceeded, an uncorrectable value is output to the control unit 13 immediately. As a result, the control unit 13 immediately determines that the data cannot be corrected and performs processing such as rereading. As described above, according to the present embodiment, the counting means for counting the number of lost data at the time of inputting the lost flag is provided, and the uncorrectable data is detected by comparing the corrected data with the correction capability. It is possible to

[0049]

As described above, according to the present invention, the common erasure position calculation unit inputs the erasure flag of the code data to calculate the common erasure position, and the erasure data at the erasure position is common to all code sequences. As a result, a correction process can be performed. Therefore, there is an effect that the correction process can be performed at high speed by performing the correction matrix operation once for all the code sequences and performing the same type of correction process for all the code sequences. In addition, even when erasure correction is performed for each code sequence, it is possible to execute the correction processing at a high speed with a small memory. It is possible to do. Therefore, correction processing of code data having a code error can be performed at high speed, and efficient correction processing can be performed with a small memory capacity without deteriorating the correction performance. Further, it is possible to obtain an excellent error correction processing device capable of determining whether the correction capability is exceeded before the start of the correction processing.

[Brief description of the drawings]

FIG. 1 is a block diagram of an error correction processing device according to a first embodiment of the present invention.

FIG. 2 is a flowchart of a control unit according to the first embodiment.

FIG. 3 is a configuration diagram of a code format of an error correction code.

FIG. 4 is a block diagram illustrating a configuration of a transfer counter according to the first embodiment.

FIG. 5 is a block diagram of an error correction processing device according to a second embodiment of the present invention.

FIG. 6 is a flowchart of a control unit in the second embodiment.

FIG. 7 is a flowchart of a control unit at the time of processing speed switching according to the second embodiment.

FIG. 8 is a block diagram of an error correction processing device according to a third embodiment of the present invention.

FIG. 9 is a flowchart of a control unit in the third embodiment.

FIG. 10 is a block diagram of an error correction processing device according to a fourth embodiment of the present invention.

FIG. 11 is a flowchart of a control unit according to the fourth embodiment.

FIG. 12 is a configuration diagram of a memory according to a fourth embodiment.

FIG. 13 is a block diagram of an error correction processing device according to a fifth embodiment of the present invention.

FIG. 14 is a block diagram of an error correction processing device according to a sixth embodiment of the present invention.

FIG. 15 is a block diagram showing an example of a conventional error correction processing device.

FIG. 16 is a flowchart of a control unit in a conventional error correction processing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data reproduction part 2 Data reception part 3 Flag reception part 7 Correction matrix operation part 8 Correction processing part 9 Syndrome operation part 10 Correction part 11 Memory management part 12 Data output part 13 Control part 40 Transfer counter 41 Row counter 42 Column counter 45, Reference Signs List 101 Common erasure position calculation unit 46, 100 Memory 61 Individual erasure position calculation unit 62 Individual erasure position storage unit 130 Common erasure number counting unit 131 Correction capability setting unit 132 Uncorrectable detection unit 135 Individual erasure number counting unit 136 Individual erasure number memory

Continuation of front page (58) Fields investigated (Int.Cl. ⁷ , DB name) H03M 13/00 G06F 3/06 303 G06F 11/10 330

Claims (8)

(57) [Claims] A data receiving unit that receives code data including an error correction code; a code data storage unit that stores the received code data; A flag receiving unit that receives an erasure flag indicating whether or not the pseudo code has a pseudo code complemented by analogy from the code data, and a code position with the erasure flag in one or more code sequences
Is the error at the same code position in all code sequences
The position information to be treated as
Based on the reception order of the erasure flags corresponding to the
A common erasure position calculation unit that calculates an erasure position; a correction matrix calculation unit that calculates a correction matrix of original code data from the common erasure position calculated by the common erasure position calculation unit; Said common vanishing point
And the correction matrix calculated from the correction matrix operation unit.
An error correction processing device, comprising: a correction processing unit that performs erasure correction processing of the same erasure position on all code sequences of the received code data. 2. A data receiving unit for receiving code data including an error correction code, a code data storage unit for storing the received code data, and a code data having a code error or a code error A flag receiving unit that receives an erasure flag indicating whether or not the pseudo code has a pseudo code complemented by analogy from the code data, and a code position with the erasure flag in one or more code sequences
Is the error at the same code position in all code sequences
The position information to be treated as
Based on the reception order of the erasure flags corresponding to the
A common erasure position calculation unit for calculating an erasure position; and a code position with the erasure flag,
Individually obtained for each code sequence based on the reception order,
An individual erasure position calculation unit for calculating an individual erasure position, and an original code data from the common erasure position or the individual erasure position.
A correction matrix calculator that to calculate the correction matrix data, the entire code sequence on the basis of the correction matrix for the common erasure locator
On the other hand, common correction of erasure correction processing for the same erasure position
Mode and based on the correction matrix for the individual erasure position
Operation to perform erasure correction processing for each erasure position for each code sequence
When the individual correction mode is set, the common correction mode or
A correction processing unit that executes any one of the error correction processes in the separate correction mode, and any one of the common correction mode and the individual correction mode.
An error correction processing device, comprising: a correction processing selection unit that instructs the correction processing unit. 3. An erasure number counting means for counting the number of data to be corrected indicated by a common erasure position, wherein the correction processing selecting means compares the number of erasures with the erasure correction capability of an error correction code, and performs correction. Select the common correction mode of the common erasure position calculation unit and the correction processing unit when within the capability, and select the individual correction mode of the individual erasure position calculation unit correction processing unit when the correction limit is exceeded. 3. The error correction processing device according to claim 2, wherein 4. A processing speed switching means for switching between high-speed error correction processing and low-speed error correction processing, wherein said correction processing selection means includes a common correction unit for said correction processing unit when high-speed processing is set.
Select the mode and correct it if low-speed processing is set.
3. The error correction processing device according to claim 2 , wherein an individual correction mode of the processing unit is selected . 5. A data receiving unit for receiving code data including an error correction code; a code data storage unit for storing the received code data; and a code data having a code error or a code error A flag receiving unit that separates and receives from the code data an erasure flag indicating whether or not the erasure flag has a pseudo code complemented by analogy, and a code position with the erasure flag,
Individually obtained for each code sequence based on the reception order,
An individual erasure position calculating unit that calculates an individual erasure position; an individual erasure position storage unit that temporarily stores the individual erasure position; and the individual erasure position calculated from the individual erasure position calculation unit
And a correction processing unit for performing erasure correction processing for each erasure position for each code sequence based on the error correction matrix and the correction matrix . 6. A data receiving unit for receiving code data including an error correction code, a code data storage unit for storing the received code data, and a code error in which the code data has a code error or a code error A flag receiving unit that separates and receives from the code data an erasure flag indicating whether or not the pseudo code has a pseudo code complemented by analogy, a code data storage unit that stores the coded data and the erasure flag as one word at the same address, When reading the code data of each code sequence from the code data storage means, an individual erasure position calculation unit that calculates an individual erasure position based on an erasure flag that is simultaneously read out, and a correction matrix calculated from the individual erasure position And a correction processing unit that performs erasure correction processing for each erasure position for each code sequence based on the individual erasure positions. Correction processing unit. 7. A data receiving unit for receiving code data including an error correction code, a code data storage unit for storing the received code data, and a code data having a code error or a code error A flag receiving unit that receives an erasure flag indicating whether or not the pseudo code has a pseudo code complemented by analogy from the code data, and a code position with the erasure flag in one or more code sequences
Is the error at the same code position in all code sequences
The position information to be treated as the
A common vanishing number counting unit for counting the number of erasure position when entering the erasure flag, the common erasure from the position and correction matrix calculation unit for calculating a correction matrix of the original code data, the count value of the common erasure number counting unit is lost Beyond correction ability
An uncorrectable detection unit that detects that the data is uncorrectable at the time when the common erasure position is calculated by the common erasure position calculation unit.
And the correction matrix calculated from the correction matrix operation unit.
The same for all code sequences of the received code data
An error correction processing device comprising: a correction processing unit that performs erasure correction processing of an erasure position . 8. The number of code data with the erasure flag.
Number for each code sequence based on the reception order of the erasure flag.
Calculated and calculated as the number of individual erasures for each code sequence
Another lost number counting unit, the count value of the individual lost number counting unit exceeds the lost correction capability
Uncorrectable detector that detects that it is not correctable
2. The error correction processing device according to claim 1, further comprising: