JP3255183B2 - Error correction device and error correction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correcting device and an error correcting device.
Regarding the correction method .

[0002]

2. Description of the Related Art In a digital data transmission system (including a recording / reproducing system), a transmission error is detected and corrected by an error detection and correction code. That is, the transmission side is provided with an error detection and correction encoding circuit for adding an error detection and correction code,
The receiving side is provided with an error detection and correction circuit that detects and corrects a transmission error using the error detection and correction code.

FIG. 3 is a block diagram showing a configuration of a conventional error detection and correction circuit. To the input terminal 10, data or a code string which has been subjected to error detection / correction coding and in which a transmission error has occurred at a certain probability by the transmission system is input. Specifically, it is a reproduction head output of a digital video tape recorder or a signal received from a digital communication line.

[0004] The data reproducing circuit 12 demodulates data from the input terminal 10, separates each synchronous block by the synchronous code of the synchronous block, and recognizes the ID of the synchronous block. The data (information data and parity for error detection and correction) reproduced by the data reproduction circuit 12 is written to the data memory 14 according to the recognized ID.

The data reproduced by the data reproducing circuit 12 is also supplied to a syndrome calculating circuit 16, which calculates a syndrome for error detection and correction by a known method, and calculates a syndrome of each code string. The data is sequentially written to the syndrome memory 18.

The error processing circuit 20 detects and corrects error data in the data memory 14 with reference to the syndrome memory 18, and writes a correction flag in a corresponding location of the data memory 14 when correction is impossible. Specifically, first, an error is detected with reference to the syndrome memory 18 and, if correctable, an error position and an error pattern are calculated.
Then, for a correctable error, the error data stored at the calculated error position is read from the data memory 14, the error pattern is added, and the error data is written to the data memory 14 again. If the data cannot be corrected, the error data in the data memory 14 is left as it is, and a correction flag is written to the data memory 14 for the code string containing the error data.

The error processing circuit 20 is, specifically, a general-purpose digital arithmetic circuit loaded with a microprogram or microcode for executing the above error processing.

After the error processing by the error processing circuit 20, the data (including the correction flag) of the data memory 14 is sequentially read out, and a subsequent circuit (for example, an interpolation circuit for uncorrectable error data, etc.) is output from the output terminal 22. ) Is output.

Such an error detection and correction circuit is incorporated in a reproduction system of a digital video tape recorder (VTR), and the error detection and correction processing there will be briefly described.

FIG. 4 shows a recording format of one line in a digital VTR, and FIG. 5 shows a recording format of one track. As shown in FIG.
It is composed of synchronous data, ID, information data of m symbols, and an error detection and correction code (inner code parity) of (nm) symbols for the information data. In one track, FIG.
Are vertically arranged for a plurality of lines, and an outer code is formed in the vertical direction. An inner code and an outer code form a product code block for error detection and correction. The transmission order of the signals matches the inner code direction in FIG.

FIG. 6 shows a flowchart of error detection and correction. The syndromes of the inner code and the outer code are calculated for each reproduced code string, and stored in the syndrome memory. 1
Syndrome for the track (the inner code syndrome is q
(M, outer code syndromes) are written, first, error detection and correction processing of the inner code is executed. That is, the syndrome in the 0th row is read from the syndrome memory, and the presence or absence of an error is checked. In the case of one error, one correction is performed, in the case of two errors, two corrections, and in the case of three or more errors, correction is impossible, so that a correction flag is set, and the process proceeds to the next row. Of course, if there is no error, the process goes to the next line without doing anything. The above processing is executed for p rows of the inner code.

When the processing of the inner code is completed, the processing shifts to the processing of the outer code. The processing of the outer code is basically the same as the processing of the inner code. For each column, the syndrome of the outer code is read from the syndrome memory, and the presence or absence of an error is checked. In the case of one error, one correction is made, in the case of two errors, two corrections, and in the case of three or more errors, the correction is impossible, so a correction flag is set, and the process proceeds to the next column. Of course, if there is no error, the process goes to the next line without doing anything. The above processing is executed for m columns of the outer code.

[0013]

In the case of image data, if the data cannot be corrected, the error data can be corrected by interpolation.
However, in an electromagnetic conversion system such as a VTR, a burst error occurs due to clogging of a head or a scratch on a magnetic tape, and the error rate may be extremely deteriorated. For example, FIG.
8 is a recording and reproducing apparatus for recording and reproducing image data (information data) on a magnetic tape in a recording format as shown in FIG.
It is assumed that an error as shown in FIG. In FIG. 8, 2
Two horizontal lines and two vertical lines connecting two crosses indicate an error occurrence location. At this time, the error detection and correction by the inner code requires two corrections of the 94 code string and the uncorrectable processing of the two code strings, and the error detection and correction by the outer code requires the two correction processing of the 92 code strings. Become.

FIG. 9 shows the number of steps in each error detection and correction process. The numerical value on the right side of each block indicates the number of steps. Assuming that the time required to divide by one track in the error detection and correction processing of the inner code and the outer code is 20,000 steps, the two correction processing of the inner code has 11,280 steps,
40 steps for uncorrectable processing, 1 for 2 corrections of outer code
It takes 1,040 steps and 960 steps to write the correction flag. That is, 23,320 per track
Needs time for steps, overcorrection ability,
There is no time to write the correction flag to the data memory.

As described above, in the conventional example, when a large number of errors occur, the correction flag cannot be written. As a result, for example, in the case of image data, interpolation cannot be performed even if an attempt is made to interpolate at a subsequent stage.

According to the present invention, an erroneous solution that solves such inconveniences is provided.
It is intended to present a correction device and an error correction method .

[0017]

An error correcting device according to the present invention is provided.
Is an error correction device that performs error correction of a product code,
The second error correction processing time longer than the first error correction processing
Counting means for counting the number of times the correct processing has been executed,
The number of times counted by the counting means is equal to or more than a predetermined value.
In such a case, the second error correction processing is not performed.
And an error correction means. The error correction method according to the present invention provides a method for correcting an error of a product code.
A correction method, which takes longer processing time than the first error correction processing.
The number of times the second error correction process having a long
Counting step and counting in the counting step.
If the number of times the number of shots exceeds a predetermined value, the second error
Error correction step to prevent
It is characterized by having.

[0018]

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Reference numeral 30 denotes an input terminal to which an inner code and an outer code for error detection and correction are added and a synchronously blocked code sequence is input, 32 demodulates a code sequence input to the input terminal 30,
A data reproducing circuit for outputting reproduced data and its ID for each synchronous block; a data memory for temporarily storing data (information data and parity for error detection and correction) reproduced by the data reproducing circuit 32; Is a syndrome calculation circuit that calculates a syndrome from the data reproduced by the data reproduction circuit 32, and 38 is a syndrome memory that stores the syndrome calculated by the syndrome calculation circuit 36.

The circuits 32, 34, 36, 3
8 perform the same function as the circuits 12, 14, 16, and 18 of FIG.

Reference numeral 40 refers to the syndrome memory 38, detects and corrects error data in the data memory 34,
An error processing circuit that sets a correction flag when correction is impossible, 42 is a correction counter that counts the number of two correction processes of the error processing circuit 40, and 42 is a data output terminal after error processing is completed. Although the details will be described later, the error processing circuit 40 normally processes errors by two error detection and two error corrections. However, if the count value of the correction counter 42 becomes equal to or more than a predetermined value within a certain period (or a predetermined process), A correction flag is set immediately without performing correction processing for two or more errors.

The error processing circuit 40, like the error processing circuit 20, comprises a general-purpose digital arithmetic circuit loaded with a microprogram or microcode for executing the above error processing.

The operation of FIG. 1 will be described. Similarly to the input terminal 10, the input terminal 30 receives data or a code string to which an inner code and an outer code for error detection and correction are added to form a synchronous block and that a transmission error occurs at a certain probability by the transmission system. The data reproducing circuit 32 demodulates the data from the input terminal 30, separates each synchronous block by the synchronous code of the synchronous block, and recognizes the ID of the synchronous block. The data (information data and parity for error detection and correction) reproduced by the data reproduction circuit 32
D is written to the data memory 34.

The data reproduced by the data reproducing circuit 32 is also supplied to a syndrome calculating circuit 36. The syndrome calculating circuit 36 calculates a syndrome for error detection and correction by a known method, and calculates a syndrome of each code string. The data is sequentially written to the syndrome memory 38.

The error processing circuit 40 detects and corrects the error data in the data memory 34 with reference to the syndrome memory 38. If the error data cannot be corrected, the correction flag is written to the corresponding location in the data memory 34, When the two correction processes are executed, the correction counter 42 is counted up.

Specifically, the error processing circuit 40 first
An error is detected with reference to the syndrome memory 38, and if correctable, an error position and an error pattern are calculated. Then, for a correctable error, the error data stored at the calculated error position is read from the data memory 34, the error pattern is added, and the error data is written to the data memory 34 again. When the 2 correction process is executed, the correction counter 42 counts up. If uncorrectable,
The error data in the data memory 14 is left as it is, and a correction flag is written to the data memory 34 for the code string including the error data.

As described above, the correction counter 42 counts up each time the error processing circuit 40 executes the two correction processes. If the count value of the correction counter 42 becomes equal to or more than a predetermined value within a predetermined period (or a predetermined process such as an error process using an inner code), the error processing circuit 40 performs a simpler error processing, that is, a short-time error processing. Switch to.

After the error processing by the error processing circuit 40 is completed, the data in the data memory 34 (including the correction flag)
Are sequentially read and output from an output terminal 44 to a subsequent circuit (for example, an interpolation circuit for uncorrectable error data).

As in the case of the conventional example, an example in which the digital video tape recorder (VTR) is incorporated in a reproduction system will be described. FIG. 2 shows a flowchart of the error processing.

As an example, assume that a transmission error as shown in FIG. 8 occurs in the data format shown in FIG.
The syndromes of the inner code and the outer code are calculated for each reproduced code string, and stored in the syndrome memory. After writing the syndrome for one track, first, an error detection and correction process of the inner code is executed. In the example of FIG. 8, two correction processes are performed on 94 lines of the inner code string of 96 lines, and uncorrectable processing (that is, a correction flag is set) is performed on the remaining two lines. 2. Every time the correction processing is executed, the correction counter 42 counts up.

When the inner code processing is completed, the processing shifts to the outer code processing. Although two errors are detected in all of the 92 outer code strings by the error processing of the inner code, two errors are detected until the count value of the correction counter 42 reaches a predetermined value (117 in this case).
Two corrections are performed on the errors, and after the count value of the correction counter 42 becomes equal to or more than a predetermined value, an uncorrectable process (set of a correction flag) is performed on the two errors. That is, 2
Switch from error correction to one error correction.

In the example of FIG. 8, the number of 2 corrections of the inner code is 9
Since it is 4, the two corrections of the outer code are up to 23 code strings, and the remaining 71 code strings are uncorrectable.

When the error processing of the outer code is completed, a correction flag for interpolation is written in the data memory, and the error processing is terminated.

For the error example shown in FIG. 8, 11,280 steps for the inner code correction, 40 steps for the uncorrectable process, 2,760 steps for the outer code correction, and 960 steps for the correction flag writing. Thus, the total number of error detection and correction can be completed within 20,000 steps of processing time for one track.

In the present embodiment, the error detection and correction code of two error detection and two error correction has been described as an example, but it is apparent that the present invention is not limited to this. The error processing circuit 4
The switching of the processing within 0 is, of course, not limited to 2 corrections to 1 correction.

[0037]

As can be easily understood from the above description, according to the present invention, even if there are many errors, the product code
Error correction can be completed within a predetermined time.
You.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

FIG. 2 is an operation flowchart of an error processing circuit 40 of FIG. 1;

FIG. 3 is a configuration block diagram of a conventional example.

FIG. 4 shows a format of a synchronization block.

FIG. 5 shows a logical format of one track of a digital VTR.

6 is an operation flowchart of the error processing circuit 20 of FIG.

FIG. 7 shows a logical format of one track of a digital VTR.

FIG. 8 is an example of occurrence of an error.

FIG. 9 is an example of the number of steps of error processing.

[Explanation of symbols]

10: Input terminal 12: Data reproduction circuit 14: Data memory 16: Syndrome calculation circuit 18: Syndrome memory 20: Error processing circuit 22: Output terminal 30: Input terminal 32: Data reproduction circuit 34: Data memory 36: Syndrome Calculation circuit 38: Syndrome memory 40: Error processing circuit 42: Correction counter 44: Output terminal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 13/00 G06F 11/10 330 G11B 20/00 H04L 1/00 H04N 7/00

Claims (4)

(57) [Claims] (1)An error correction device that performs product code error correction.
So, The second error correction processing time longer than the first error correction processing
Counting means for counting the number of times the correct processing has been executed, The number of times counted by the counting means is equal to or more than a predetermined value.
In such a case, the second error correction processing is not performed.
Error correction means comprising:
Positive device. 2. The method according to claim 1, wherein the first error correction process is performed for one error.
Is corrected, and the second error correction is performed by 2
Claims characterized by processing to correct two errors
2. The error correction device according to 1. (3)An error correction method that corrects product code errors
So, The second error correction processing time longer than the first error correction processing
Count step to count the number of times the correct processing has been executed
When, The number counted in the counting step is equal to or less than a predetermined value.
If it is above, do not execute the second error correction processing
And an error correction step.
Error correction method. 4. The method according to claim 1, wherein the first error correction process is performed for one error.
Is corrected, and the second error correction is performed by 2
Claims characterized by processing to correct two errors
3. The error correction method according to 3.