JP2000010807A - Digital data reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the RAM access frequency of an error correcting circuit. SOLUTION: This reproducing device is provided with a digital data demodulating circuit 111 which inputs data in which at least a PI correction code and a PO correction code are added to plural data columns and demodulates the inputted digital data, a storage means which temporarily stores the demodulated digital data and an error correcting circuit 121 which reads the data out of the storage means and detects or corrects wrong data. The demodulating circuit 111 finds a syndrome showing the state of an error of which the said data columns have and to be corrected by using the PI correction code. The error correcting circuit 121 can perform the correcting processing even in the case that either of the PI syndrome and the data columns including the PI correction code is made to an input.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data reproducing apparatus, and more particularly to a digital data reproducing apparatus which temporarily stores data in a memory and performs processing such as error correction.

[0002]

2. Description of the Related Art An example relating to a reproducing apparatus for a recording medium on which digital data is recorded is described in "K. 56-71
(1990). This document describes the processing contents of a CD reproducing apparatus, a digital signal processing unit included in the apparatus, and a circuit configuration thereof. Japanese Patent Application Laid-Open No. 8-329622 describes a circuit configuration for performing a syndrome calculation required for error correction separately from an error correction circuit.

[0003]

However, in the conventional literature, the syndrome calculation required for error correction is performed separately from the error correction circuit, and the error correction that occurs when a plurality of data errors are corrected by a single code is performed. A method for minimizing the number of memory accesses of the error correction circuit when inputting data for which error correction is performed in a plurality of directions, such as data forming a product code, is described. Not listed. An object of the present invention is to provide a digital data reproducing apparatus capable of reducing the number of memory accesses of an error correction circuit even when data for which error correction is performed in a plurality of directions is input.

[0004]

In order to achieve the above object, according to the present invention, a digital data having at least a first check symbol and a second check symbol added to a plurality of data strings is input. And demodulating means for demodulating the digital data, storing means for temporarily storing the demodulated digital data, and error detecting means for reading out data from the storing means and detecting error data. A syndrome indicating an error state of a data string to be inspected by the first inspection symbol is obtained.

Further, in the present invention, digital data in which at least a first correction code and a second correction code are added to a plurality of data strings is input, and demodulation means for demodulating the digital data; The digital signal processing system comprises: a storage unit for temporarily storing digital data; and an error correction unit for reading data from the storage unit to generate error data. The demodulation unit has the data string to be corrected by the first correction code. Seeking a syndrome that indicates the state of the error that is present.

Further, the syndromes obtained by the demodulation means are temporarily stored in the storage means. The error correction means generates error correction data using the syndrome stored in the storage means.

Further, when the error correction means cannot generate error correction data using the syndrome stored in the storage means, the error correction of the data string to be corrected by the first correction code is performed. A mark indicating that it is impossible is written in the position of the syndrome. The storage means stores a data string and a second correction code in addition to the syndrome determined by the demodulation means. In this case, the error correction means generates error correction data using the syndromes stored in the storage means, and reads out the data string read from the storage means and the second correction code to read the second correction code. In this case, another syndrome indicating the error state of the data sequence to be corrected is obtained, and another error correction data is generated from the other syndrome. In the present invention,
Correction processing can be performed regardless of whether the syndrome or the data string including the first correction code is input to the error correction means.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a digital data reproducing apparatus according to the present invention.

First, input digital data handled in this embodiment will be described with reference to FIG. FIG.
FIG. 2A is a schematic diagram showing an ECC block of digital data, and FIG. 2B is a schematic diagram of a recording sector of digital data. As shown in FIG. 1A, the ECC block 206 is composed of several data sectors 201. The data sector 201 includes a sector ID 202, additional data 203, main data 204, and main data 20.
4 is composed of an error detection code (EDC) 205 for E.4. Further, a PI correction code 207 is arranged in the column direction of the sector data 201, and a PO correction code 208 is arranged in the row direction of the last sector data. Also, 20
Reference numeral 9 denotes an arrow indicating the direction of PI correction, and reference numeral 210 denotes an arrow indicating the direction of PO correction.

First, the configuration of the data sector 201 will be described. The data sector 201 is composed of a 2048-byte main data 204 divided in time series and a sector ID 202 indicating a position on a recording medium, and additional data 203 including information such as copy restrictions on the data sector 201. In addition to the above, even when an error is included in the data sector 201, the data sector 201 is composed of 2064 bytes of data obtained by adding a 4-byte EDC 205 after the main data 204.

Next, the configuration of the ECC block 206 which is a basic data unit of the error correction processing will be described. EC
The C block 206 has a 16-byte PO correction code for each of 172 columns of a data field (172 × 192 bytes) which is obtained by making one data sector 201 into 12 rows (172 bytes / row) and stacking 16 rows. 208 to PO
After adding after the data sequence according to the correction direction 210, 2
10-byte PI correction code 207 for each of the 08 rows
At the end of the data string according to the PI correction direction 209.

As shown in FIG. 2B, the recording sector 21
Reference numeral 1 denotes a newly added synchronization signal 212, sector data 213 composed of 8/16 modulated data, and a PI correction code.
It is composed of The synchronization signal 212 includes synchronization signals 0 to 12. The modulation of the main data is performed by sequentially configuring the data sector 201, the ECC block 206, and the recording sector 211. The recording sector 211 includes a PO correction code 208 added to the data sector 201 when forming the ECC block 206.
After performing the interleave on a row basis by adding the PI correction code 207 added to each of the one row and the thirteen rows thereof, and performing the 8/16 modulation for suppressing the DC component to all the data, , The generated data in time series 2912
The data is divided into bits, and each data sequence is composed of data generated by adding a 32-bit synchronization signal 212 thereto.

FIG. 1 is a block diagram schematically showing an embodiment of a digital data reproducing apparatus according to the present invention. FIG. 1 shows an example in which data for which error correction is performed in multiple directions is input,
This is a data reproducing apparatus that can reduce the number of memory accesses from an error correction circuit when accessing the same RAM from several signal processing circuits. In this embodiment, a description will be made using a data and data reproduction processing circuit in which error correction is performed in two directions, that is, the PI correction direction 209 and the PO correction direction 210. However, the error correction direction for the same data is particularly required to be two directions. There is no. The input data of the data reproduction processing circuit of FIG. 1 is a recording sector 211 which is data subjected to the modulation described with reference to FIG.

In FIG. 1, reference numeral 101 denotes an input terminal to which digital data input to a demodulation circuit and a clock synchronized with the data are input. 102 is data,
And an output terminal from which a clock synchronized with data is output. The digital data input to the terminal 101 and the clock synchronized with this data are supplied to the synchronization detection / 8/16 demodulation circuit 113 of the demodulation circuit 111 and output line 115
8/16 demodulated data is extracted. This 8
The / 16 demodulated data includes main data, PI code correction code, and PO correction code. Furthermore, 8/16
The demodulated data is used as a PI correction syndrome operation circuit 1.
12 and the PI syndrome 603
Is output. The 8/16 demodulated data taken out to the line 115 and the PI syndrome 603 taken out to the line 116 correspond to the selector or data select circuit 11.
The line 115 or the line 116 according to the select signal at 4
Is selected and taken out, and the RAM control circuit 141
Is written to the RAM 151 via the. In this way, the main data, the PO correction code, and the P
The I syndrome 603 is written (main data,
A PO correction code, a PI correction code, and a PI syndrome may be written. ). P written to RAM 151
The data including the I syndrome and the PO correction code are read from the RAM 151 by outputting a data read request signal from the error correction circuit 121 to the RAM control circuit 141, and read out of the P of the error correction circuit 121 through the line 105.
The signal is supplied to the O correction syndrome operation circuit 122 and to the selector 124. The PO correction syndrome calculation circuit 122 calculates the PO syndrome from the main data and the PO correction code, and takes out the PO syndrome to the output line 125. The selector 124 selects either the PO syndrome obtained from the line by the select signal or the PI syndrome 603 input to another input terminal, inputs the same to the error position / value calculation circuit, and calculates the error position / value. The PI or PO error position and value are obtained at the output of the circuit 123. The error position and value are supplied to the RAM control circuit 141, where the error in the main data is corrected,
Written to M151. When the PI correction is performed twice or more, the PI syndrome is obtained by the PO syndrome calculation circuit 122 with the PI correction code stored in the RAM 151, and the main data can be corrected using the PI syndrome. A data read request signal from the external circuit of FIG.
When the data is input to the AM control circuit 141, the data stored in the RAM 151 is output to the external circuit through the terminal 102 through the output control circuit 131. Conventionally, in order to perform PI correction, a PI correction code and data are written in a RAM 151, the written one-row data and the PI correction code are read, and supplied to a PI correction syndrome operation circuit to obtain a PI syndrome 603. However, in the present invention, the operation of the PI syndrome 603 is performed by the demodulation circuit 11.
1 is used, the data of each line is stored in the RAM 151.
The number of times of reading from can be reduced.

FIG. 1 shows data sectors 201, E shown in FIG.
The demodulation circuit 111 and the error correction circuit 121 perform data demodulation to return to the original format by inputting modulated data for sequentially configuring the CC block 206 and the recording sector 211 and a clock synchronized with the data. Thereafter, the data reproduction processing circuit outputs the main data 204 from the output control circuit 131 to the outside of the data reproduction processing circuit. less than,
The demodulation processing in the data reproduction processing circuit shown in FIG. 1 will be described in more detail with reference to FIGS. 3, 4, 5, and 6. FIG. 3 is a block diagram showing details of the demodulation circuit of FIG. 1. In FIG.
8/16 demodulated data (including sector ID 202 and PI correction code 207) is output to the third line 115, and this data is supplied to the PI syndrome operation circuit 112. The demodulation circuit 111 is provided with a control signal generation circuit 304, and a signal indicating that a synchronization signal has been detected from the synchronization signal detection / 8/16 demodulation circuit 113 is supplied to the control signal generation circuit 304 via a line 311, and its output Track 31
3 includes a PI syndrome reset signal, an enable signal,
A timing signal indicating the timing at which the select signal and the synchronization signal are detected is output. Of these signals, PI
The syndrome reset signal and the enable signal are supplied to the PI syndrome operation circuit 112. The PI syndrome operation circuit 112 includes an adder 321 on the Galois field, a × α ⁰ multiplier 322 on the Galois field, and a syndrome s ₀ register 32
3. × α ¹ multiplier 324 on Galois field, syndrome s ₁
The register 325 includes a × α ⁹ multiplier 326 on the Galois field, and a syndrome s ₉ register 327. P
The I syndrome reset signal is used to reset the register 323 and the like of the PI syndrome operation circuit 112 for the next PI syndrome operation, and the enable signal is a signal that allows the output signal of the adder 321 and the like to be supplied to the register 323 and the like. Used as The PI syndrome 603 of the line 116 and the 8/16 demodulated data of the line 115 are input to the data select circuit 114, and the line 313
, One of the inputs, that is, 8/16 demodulated data or PI syndrome 6
03 or a timing signal indicating the timing at which the synchronization signal is detected is output from the output terminal 1 of the data selection circuit 114.
04 and is input to the RAM control circuit 141 at the next stage.

The synchronization signal output to the terminal 104 is determined by the detected timing signal and the sector ID 202.
The 8/16 demodulated data and the PI syndrome 603 are written to the address of the AM 151. This 8/16
Demodulated data and PI syndrome 603 are stored in RAM
151 and supplied to the error correction circuit 121.

FIG. 4 is a schematic diagram showing an example of an ECC block format data array written in the RAM of the data reproduction circuit, and FIG. 5 is a diagram showing an EC written in the RAM of the data reproduction circuit.
It is a schematic diagram which shows the other example of the data arrangement of C block format. The data array in the form of the ECC block 206 shown in FIGS.
1 is written to the RAM 151. E shown in FIG.
The data string in the CC block format is composed of data sector 602 and P
It is composed of an I syndrome 603.

The data sequence in the ECC block format shown in FIG. 5 is composed of a data sector 204, a PI correction code 207, and a PI syndrome 603. In this data string, the PI correction code 207 is included.
The I correction code is used when performing correction in the PI direction two or more times. That is, the error correction circuit 121 uses the PI syndrome 603, the error position / value calculation circuit 123 obtains the error position and value, and corrects the data error.
The PI correction code is read from the RAM 151 and supplied to the PO syndrome operation circuit 122 of the error correction circuit 121,
The PI syndrome 603 is output to this output, and this PI
The error position and error value of the PI are obtained again from the syndrome 603 and used to correct the data error.
In general, the PO syndrome circuit 122 has a function of calculating a PI correction code to obtain a PI syndrome 603.

FIG. 6 is a schematic diagram showing an example in which a data field in the ECC block format of FIG. 4 is arranged in a RAM. In FIG. 6, data arranged in the RAM 151 is a data field including a PI syndrome 603 for each row of one ECC block 602 of 172 × 208 bytes excluding the PI correction code. For the data arranged in the RAM 151 as shown in FIG. 6, the error correction circuit 121 of the data reproduction processing circuit shown in FIG.
At the time of I correction, PI syndrome 603 is read from RAM 151.
Is read, and PI correction processing is performed using the read data.
The PO correction code and data of 08 bytes are read out, the PO syndrome is calculated by the PO syndrome calculation circuit 122, and the error position / value calculation circuit 123 outputs the error position and the error value using the PO correction code and performs PO correction processing. To do.

FIG. 7 is a block diagram showing details of the error correction circuit of the data reproduction processing circuit shown in FIG. In the figure, the error position / value calculation circuit 123 is the second calculation circuit 70
5, third arithmetic circuit 706, fourth arithmetic circuit 707, RAM
It comprises a write circuit 708. 709 is a control circuit of the error correction circuit 121. RAM on line 105
Output data, ie, 8/16 demodulated data, PI
The syndrome 603 and the PO correction code are input and input to the PO syndrome operation circuit 122. Control circuit 70
9, when a data fetch signal is supplied to the PO syndrome operation circuit 122 through a line 720, the PO syndrome operation circuit 122
When the correction code is taken in and an operation processing start signal is supplied from the line 730 to the PO syndrome operation circuit 122, the operation is performed by the circuit 122. The result of this operation is PO
Selector 124 through line 125 as a syndrome
Supplied to The PI syndrome 603 is supplied to the selector 124 through the line 105,
Is supplied through the PO syndrome. A PI / PO switching signal is supplied from the control circuit 709 to the selector 124 via the line 712, and the PI syndrome 603 or P
The O syndrome is selected and supplied to the second arithmetic circuit 705 of the error position / value arithmetic circuit 123. The arithmetic circuit 705 starts an arithmetic operation in response to an arithmetic processing start signal from the line 720, generates an error locator polynomial and an error evaluation polynomial from the PO or PI syndrome 603, and
2 and input to the third arithmetic circuit 706 to determine the position of the error contained in the data from the error locator polynomial. The error position calculated by the third arithmetic circuit 706 and the error evaluation polynomial and the error position polynomial which are temporarily stored in this circuit 706 are input to a fourth arithmetic circuit 707 through a line 713. An error value is calculated from the error evaluation polynomial and the error location polynomial. The obtained error value and error position are transmitted to the RAM writing circuit 7 through a line 714.
08, and these data are accumulated in the buffer circuit of the circuit 708 until the correction is completed. The third,
Fourth arithmetic circuits 706 and 707, RAM write circuit 708
The operation is also started by the operation processing start signal from the line 730. When a data write request signal is output from the RAM write circuit 708 to the RAM control circuit 141 through the line 722, a data write request acceptance signal is sent from the RAM control circuit 141 to the RAM write circuit 708 through the line 723. RAM write circuit 7 in response
From 08, a write position and an error value are output to the RAM control circuit 141 through a line 724. RAM control circuit 1
41 reads data from the RAM 151,
At 41, the data error is corrected. Tracks 722, 724
Corresponds to the line 109 in FIG.

In FIG. 7, when a data read request signal is sent from the control circuit 709 to the RAM control circuit 141 through the line 725, the RAM control circuit 141
Since the data read request acceptance signal is sent to the control circuit 709 through 6, the RAM data is input to the error correction circuit 121 from the line 105 based on the signal. The control circuit 709 generates a data fetch signal and an arithmetic processing start signal based on the data read request acceptance signal.
Is supplied to each of the arithmetic circuits 122, 705, 706, and 707. When the correction of one ECC block is completed, a 1 ECC block correction end signal is input from the control circuit 709 to the RAM control circuit 141 via the line 727. The arithmetic processing in the error correction circuit 121 is shown in FIG.
The pipeline processing shown in FIG.

FIG. 8 is a time chart showing the parallel processing of the error correction circuit. In the figure, the horizontal axis indicates time t, and the vertical axis indicates frame number n. Frame number n is PI
1 to 208 for correction, 1 to 172 for PO correction,
Whether the PI correction or the PO correction is performed is generated by the control circuit 709 and is selected by a PI / PO switching signal supplied through a line 721. In the error correction circuit 121 shown in FIG. 7, for example, at the time of PI correction, the PI syndrome 6 of the frame number n is read from the RAM 151 at the start of the arithmetic processing (T).
03 is read out, and the PI 124
By selecting 03, the PI syndrome 603 is taken into the second arithmetic circuit 705. And (T
+ T), the second arithmetic circuit 705 starts the PI syndrome 6
03, an error locator polynomial and an error evaluation polynomial are generated and output to the third arithmetic circuit 706. From (T + 2t), the third arithmetic circuit 706 determines the position of the error contained in the data from the error locator polynomial. From (T + 3t), the fourth arithmetic circuit 707 determines the position of the error determined by the third arithmetic circuit 706. An error value is calculated from the error evaluation polynomial and the error locator polynomial temporarily stored in the three arithmetic circuit 706.
The obtained error value and error position are input to the RAM writing circuit 708 from the time (T + 4t), and are added to the error data in the RAM 151 via the RAM control circuit 141 to be used to correct the error data. Can be Also,
At (T + t), the arithmetic processing of the frame number (n + 1) is started.

At the time of the PO correction, the PO correction code of frame number n and the data are RA
PO syndrome operation circuit 12 read from M151
The PO syndrome is calculated in step 2. At the start of the pipeline processing step indicated by (T + t) in FIG.
At 24, the output from the PO syndrome operation circuit 122 is selected as an input to the second operation circuit 705. Then, the operation of the second arithmetic circuit is performed from (T + t) time, and thereafter, the arithmetic operation of the third arithmetic circuit 706 is performed from (T + 2t) time.
From (T + 3t) time, the fourth arithmetic circuit 707 is performed, and (T + 3t)
From time + 4t), the data writing circuit 708 operates in the same manner as in PI correction, and corrects erroneous data.

In the data reproduction processing circuit of the present invention, the number of accesses to the RAM 151 from the demodulation circuit 111 and the output control circuit 131 is the same as that of the existing data, but the number of accesses to the RAM 151 for PI error correction is reduced. From the error correction circuit 121 to the RAM 15
1 can be reduced. Accordingly, in the case where the syndrome calculation time is longer than the other calculations with the existing technology, and the time required for the syndrome calculation is determined by the number of times the RAM 151 can be accessed within a certain period of time, Since the syndrome calculation time can be reduced, the error correction time for one ECC block can be significantly reduced. Also, the error correction processing is not pipeline processing as shown in FIG.
The same can be said for the case where the processing is performed in series.

Further, the error correction circuit 121 sends the RAM1
The number of accesses to the demodulation circuit 11 is reduced.
1. When the number of accesses from the output control circuit 131 to the RAM 151 can be increased, the transfer rate of input data to the data reproduction processing circuit increases, or the transfer rate of output data is temporarily increased. Also, the data reproduction process can be performed without stopping each process. The ECC block 20 as shown in FIG.
When the data field in the format of No. 6 is arranged in the RAM 151, the error correction processing in the repeated PI correction direction 209 can be performed. In this case, the first error correction in the PI correction direction 209 uses the PI syndrome 603 in the RAM 151, and the second and subsequent times correct the RA
Main data 204 in the PI correction direction 209 from M151
And the PI correction code 207, and the error correction circuit 121
The PI syndrome 603 may be generated by the PO syndrome calculation circuit 122 provided in the.

Next, referring to FIG.
The operation of the RAM control circuit 141 and the RAM 151 will be described. FIG. 9A shows an error correction circuit according to the present invention, RA
3 is a block diagram showing details of an M control circuit and a RAM. In the figure, the error correction circuit 121 switches to the RAM control circuit from FIG.
The transmission and reception of the signal described with reference to FIG. The RAM control circuit 141 includes a RAM control signal generation circuit 1104 with a write flag setting function, an error correction address counter 110
5, a RAM address conversion circuit 1106. A PI / PO switching signal is sent to the RAM control signal generation circuit with write flag setting function 1104 through a line 721,
A data read request signal is supplied through a line 725, a data write request signal is supplied through a line 722, and an error write position and an error value data are supplied through a line 724. An R / W switching signal is output to the output line, various control signals are output to the output line 733, and RAM input data is output to the output line 734, and are supplied to the RAM 151.

A data read request reception signal is supplied from the RAM control signal generation circuit with write flag setting function 1104 to the error detection circuit 121 through the line 726 and a data write request reception signal is supplied through the line 723. A data read request acceptance signal is supplied to the error correction circuit address counter 1105 through a line 726,
, A 1 ECC block correction end signal is supplied.
A RAM address is generated from the output, and the address is converted by a RAM address conversion circuit 1106 to output a line 731.
Through the RAM 151. Line 734 to R
The RAM input data input to the AM 151 is transmitted to the line 731.
Is written to the RAM 151 in accordance with the RAM address from. Also, according to the control signal from the line 733,
RAM output data (8/16 demodulated data, PI syndrome, PO correction code) from RAM 151
05 to the error correction circuit 121.

FIG. 9B is a time chart for explaining FIG. 9A, in which the R / W switching signal is read (Re)
ad) and write. At the time of reading, when the data reading reception signal is output (active state), the PI syndrome FFF is read from the address number specified by the RAM address, for example, 0123.
When the R / W switching signal changes from reading to writing, of the RAM input signals, a signal to be written to the RAM 151, for example, 0
Since 00 is written to the address number of the RAM 151, when the R / W switching signal changes to read again, 000 is read as RAM output data. The 000 includes, for example, a write flag described later. In the figure, "undefined" of the RAM output data indicates that it is not output at the time of writing.

FIG. 10 shows an error correction circuit according to the present invention, RA
FIG. 14 is a block diagram showing another embodiment of the M correction circuit and the RAM. 9A is different from the block diagram of FIG. 9A in that a RAM control signal generation circuit 11 with a write flag setting function is provided.
04 RAM write circuit 12 with write flag set function
04 is provided in the error correction circuit 121 separately.
The write flag function will be described later. Next, in this data reproduction processing circuit, when the demodulation circuit 111 cannot write data to the RAM 151, for example, when the input data is
It will be described that even when data is lost in the correction direction 209, it is possible to easily detect that data on the RAM 151 has been previously written and that data has not been correctly written.

First, an algorithm for detecting that data is not correctly written will be described with reference to FIGS. FIG. 11 shows the demodulation circuit 111 and the RAM 15
6 is a flowchart for data access between the first and second data. In step 902, the demodulation circuit 111 outputs R
Data input to the AM control circuit 141 is started. PI
The determination as to whether the PI syndrome 603 obtained by the syndrome calculation circuit 112 is to be written to the RAM 151 is made based on whether the end of the PI frame has been written to the RAM 151, counting from the beginning of the PI frame. Therefore, in step 903, the head of the PI frame is detected.
, The 8/16 demodulated data is written to the position of the write data counter 0 of the control signal generation circuit 304.
If the PI frame head is not detected, step 90
Increment the address of the write data counter to which data is written in 4, that is, add 1 to the address value.
Add. In step 906, the 8/16 demodulated data is written at the address of the write data counter, and in step 907, the end of the PI frame is searched. If the end of the PI frame is detected, at step 908 R
Write PI syndrome to AM151 Step 90
Move to 9. If the end of the PI frame is not detected, the process also proceeds to step 909. If the data input is completed in step 909, the process ends in step 910. If the data input is not completed, the process returns to step 903.

In order to realize this algorithm in an actual circuit, the control signal generation circuit 304 in FIG. 3 has a write data counter reset by the synchronization signal detection signal output from the synchronization signal detection circuit 304. This counter increases the value by one each time 1-byte data is input, so that the 8/16 demodulation circuit 113
Of the data output from the RAM 151 on the RAM 151. When the counter value reaches the value indicating the end of the PI frame, the PI syndrome 603 is stored in the RAM 1
51 to a data buffer (which may be provided in the data select circuit 114).
To be written in the PI syndrome area. At this time, if the synchronization signal cannot be detected by the synchronization signal detection circuit 113, the write data counter is not reset, and the value of the write data counter becomes a value that does not correspond to the address of the RAM 151.
Writing to M151 is stopped until the next synchronization signal is detected.

FIG. 12 is a flowchart of data access between the error correction circuit and the RAM.
4 is an example of an algorithm for data access between the RAM and the RAM 151. In step 1002, R
The error correction is started by inputting the PI syndrome from the AM 151 to the error correction circuit and obtaining the PO syndrome. If PI correction is performed in step 1003, the PI syndrome is read into the second arithmetic circuit 705 in step 1004 to determine an error position and an error value. If correction is impossible, a write flag is set in step 1006. If PI correction is not performed in step 1003, data in the PO direction is read in step 1005, and an error position and an error value are obtained from the PO syndrome. In step 1007, correct data is written on the error data. In step 1008, error correction is completed, and a 1 ECC block correction end signal is output. If the correction is not completed, the process returns to step 1003.

When the error correction processing is performed in the PO correction direction 210, data is read from the RAM 151 in the PO correction direction, and the error correction processing is performed as described above. When error correction processing is performed in the PI correction direction 209, and when correction in the PI
After the PI syndrome 603 is read from 151,
A write flag is set at the place where the PI syndrome 603 has been written. This flag is used by the error correction circuit 121
Indicates that correction in the PI correction direction 209 becomes impossible. Then, since a problem occurred in the demodulation circuit 111, the RAM
Even when writing to the data 151 becomes impossible, the write flag remains at the position of the PI syndrome 603, so that it is detected that there is a lot of erroneous data on the PI frame, and erroneous correction is prevented. It becomes possible.

An example of a circuit configuration for realizing the algorithm shown in the flowchart of FIG. 12 will be described with reference to FIGS. Data read / write of the RAM 151 to be used can be easily performed by an R / W switching signal or the like, and the bus width of the input data and the output data of the RAM 151 is the PI syndrome 6
If the width is 03 bytes, which is the same as the width of 03, when the PI syndrome 603 is read to the error correction circuit 121, the input data of the RAM 151 is set to the value of the write flag at the same time. After the value of the PI syndrome 603 is captured by the error correction circuit 121, the write flag can be easily written without switching the RAM address by switching the attribute of the R / W switching signal to write.

Even when the bus width of the data input to the RAM 151 is different, it can be easily realized by switching the RAM input data to the value of the write flag corresponding to the address. If the bus width is larger than 10 bytes,
Since the RAM output data includes not only the PI syndrome 603 but also the main data before and after,
The bus data corresponding to the main data of the M output data is
AM control signal generation circuit 1140
By outputting as an M input data bus, the PI syndrome 603 can be similarly rewritten to a write flag using an R / W switching signal.

In FIG. 10, the RAM 151 used
Since the data read / write cannot be easily performed by the R / W switching signal or the like, the function to set the write flag in the error correction circuit 121, that is, the function to set the write flag in the PI syndrome 603 in the same manner as the correction of the error data The algorithm in FIG. 12 is realized by providing a RAM write circuit having the following. Further, there is no particular problem even if the similar write flag setting function of the PI syndrome 603 is provided not in the error correction circuit 121 but in a part of the RAM control circuit 141.

FIG. 13 is a schematic diagram showing the internal state of the RAM when performing the error correction processing in the flowcharts of FIGS. As shown in the figure, a write flag 1302 indicating that correction has been made to the PI syndrome is overwritten on the error-corrected block 1301 of one ECC block. For the 1 ECC block 1303 undergoing the error correction process, the write flag is overwritten on the PI syndrome for the portion where the error correction is completed, but the PI syndrome is written for the portion where the error correction is not completed. I have. When the processing is being performed by the demodulation circuit 111, the previous syndrome and the write flag are left in the RAM 151. Thus, the data reproduction processing circuit shown in FIG.
PI syndrome 60 as shown in FIG. 9 or FIG.
3 is read, and the read PI syndrome 60 is read.
By adding the write flag setting function circuits 1104 and 1204 for setting the write flag at the write position of No. 3 in the PI correction direction 209 when the input data is erroneous in a burst or the input data is missing. Even if the data is missing, the error correction circuit 123 can easily detect that the data on the RAM 151 is the previously written data and that the data is not newly written correctly. As a result, the inability to correct the error due to the inability to detect the position of the error in the PO correction caused by the missing data is eliminated. Further, it is possible to prevent many erroneous corrections that occur at the time of erasure correction.

As described above, according to the present invention, in a data reproduction processing device which receives data for which error correction is performed in a plurality of directions, a syndrome operation used for error correction performed in an input data direction is performed by a demodulation circuit, and the data is obtained therefrom. By temporarily storing the syndrome on the memory, the number of memory accesses for reading data from the error correction circuit can be reduced. Therefore, even when the transfer rate of input data to the data reproduction processing circuit increases or when it is desired to temporarily increase the transfer rate of output data, data reproduction processing can be performed without stopping each processing. Becomes

[0039]

As described above, according to the present invention, in a data reproduction processing apparatus which receives data for which error correction is performed in a plurality of directions as input, a syndrome operation used for error correction performed in an input data direction is performed by a demodulation circuit. Thus, by temporarily storing the obtained syndrome in a memory, the number of memory accesses for reading data from the error correction circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing an embodiment of a digital data reproducing apparatus according to the present invention.

FIG. 2 is a schematic diagram of an ECC block of digital data and a recording sector of digital data.

FIG. 3 is a block diagram illustrating details of a demodulation circuit of FIG. 1;

FIG. 4 is an ECC written to a RAM of a data reproducing circuit.
It is a schematic diagram which shows an example of a data array of a block format.

FIG. 5 shows an ECC written to a RAM of a data reproducing circuit.
It is a schematic diagram which shows another example of the data array of a block format.

6 is a schematic diagram showing an example of a case where data fields in the ECC block format of FIG. 4 are arranged in a RAM.

FIG. 7 is a block diagram showing details of an error correction circuit of the data reproduction processing circuit shown in FIG. 1;

FIG. 8 is a time chart illustrating parallel processing of the error correction circuit.

FIG. 9 is an error correction circuit and a RAM control circuit according to the present invention;
It is a block diagram and a time chart of signals showing the details of the RAM.

FIG. 10 is a block diagram showing another embodiment of the error correction circuit, the RAM correction circuit, and the RAM according to the present invention.

FIG. 11 is a flowchart of data access between a demodulation circuit and a RAM.

FIG. 12 is a flowchart of data access between an error correction circuit and a RAM.

FIG. 13 is a schematic diagram showing an internal state of a RAM when performing error correction processing in the flowcharts of FIGS. 11 and 12;

[Explanation of symbols]

111 demodulation circuit, 112 syndrome calculation circuit for PI correction, 113 synchronization detection / 8/16 demodulation circuit, 114
... selector, 121 ... error correction circuit, 122 ... PO correction syndrome calculation circuit, 123 ... calculation circuit for finding error position and value, 124 ... selector, 131 ... output control circuit, 141 ... RAM control circuit, 151 ... RAM, 60
3: PI syndrome, 125: PO syndrome, 2
01 ... data sector, 204 ... main data, 206 ...
ECC block, 207: PI correction code, 208: PO
Correction code, 211: recording sector, 304: control signal generation circuit, 705: second arithmetic circuit, 706: third arithmetic circuit, 707: fourth arithmetic circuit, 708: RAM write circuit, 709: control circuit.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hiroshi Nagai 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Multimedia System Development Division, Hitachi, Ltd. (Reference) 5B001 AA08 AB02 AB05 AC01 AC05 AC07 AD03 AE02

Claims (13)

[Claims] 1. A demodulator for receiving digital data in which at least a first check symbol and a second check symbol are added to a plurality of data strings, and demodulating the digital data.
A storage means for temporarily storing the demodulated digital data; and an error detection means for reading data from the storage means and detecting error data, wherein the demodulation means is an object to be inspected by the first inspection symbol. A digital data reproducing apparatus for obtaining a syndrome indicating an error state of the data string. 2. A digital data reproducing apparatus according to claim 1, wherein said error detecting means obtains a syndrome indicating an error state of said data string to be checked by said second check symbol. Digital data reproducing apparatus. 3. A digital data in which a first correction code and a second correction code are added to a plurality of data strings, a demodulation means for demodulating the digital data, and a means for temporarily demodulating the demodulated digital data. And error correction means for reading out data from the storage means to generate error data, wherein the demodulation means has an error in the data string to be corrected by the first correction code. A digital data reproducing apparatus for obtaining a syndrome indicating the state of the digital data. 4. The digital data reproducing apparatus according to claim 3, wherein said storage means stores said syndrome obtained by said demodulation means. 5. The digital data reproducing apparatus according to claim 4, wherein said error correction means generates error correction data using said syndrome stored in said storage means. 6. A digital data reproducing apparatus according to claim 4, wherein said error correction means corrects the error using said first correction code when error correction data cannot be generated using said syndrome stored in said storage means. A digital data reproducing apparatus, characterized in that a mark indicating that an error of the data string as an object cannot be corrected is written at the position of the syndrome. 7. A digital data reproducing apparatus according to claim 3, wherein said storage means stores said data string, said second correction code, and said syndrome. 8. A digital data reproducing apparatus according to claim 7, wherein said error correction means reads said data string and said second correction code read from said storage means and uses said second correction code to read said data string and said second correction code. A digital data reproducing apparatus for obtaining another syndrome indicating an error state of the data string to be corrected. 9. The digital data reproducing apparatus according to claim 7, wherein said error correction means generates error correction data using said syndrome read from said storage means and reads out said error correction data from said storage means. From the data sequence and the second correction code, another syndrome indicating an error state of the data sequence to be corrected by the second correction code is obtained, and another error correction is performed from the other syndrome. A digital data reproducing apparatus for generating data. 10. A digital data reproducing apparatus according to claim 3, wherein said storage means stores said data string, said first and second correction codes, and said syndrome,
A digital data reproducing apparatus, wherein the error correction means selectively reads out the syndrome, the data string and the first correction code from the storage means to generate error correction data. 11. The digital data reproducing apparatus according to claim 3, wherein said storage means stores said first correction code and said second correction code.
The digital data to which the correction code is added and the syndrome are stored, and the error correction means detects an error from the syndrome, the first correction code, and the second correction code stored in the storage means. A digital data reproducing apparatus for generating corrected data. 12. A digital data reproducing apparatus according to claim 3, wherein said demodulating means generates a timing signal for writing said syndrome in said storage means. 13. The digital data reproducing apparatus according to claim 3, wherein said storage means stores said data string, said second correction code and said syndrome, and said error correction means is provided in said storage means. In addition to generating error correction data using the syndrome, the data string read from the storage means and the second correction code are read out, and the data string to be corrected by the second correction code has Find another syndrome that indicates the state of the error that has occurred, generate another error correction data from the other syndrome, and when the syndrome cannot correct the data, confirm that the correction cannot be made at the position of the syndrome. A digital data reproducing device for writing an indication mark.