JP2006191378A - Error correction apparatus, reproducing apparatus and reproducing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that when a synchronizing signal is misdetected as a normal signal in spite of an error synchronizing signal, erasing/correction which is executed while regarding information block just before or after the error synchronizing signal as a burst error can not be performed and error correction capacity can not be sufficiently utilized in conventional technology. <P>SOLUTION: When the error correction of an information block just before or after a synchronizing signal by an error detection/correction circuit 22 is impossible even if the synchronizing signal in a reproducing signal is normally reproduced, a SYNC signal control circuit 23 performs write control so that all synchronizing signals Sync stored in an ECC block memory 21 are regarded as errors. The error detection/correction circuit 22 erases/corrects the information block just before or after an error synchronizing signal in an ECC block after the write control. Therefore, even when error correction disablement is generated due to misdetection such that a synchronizing signal which is a substantially error signal is misdetected as a normal signal, erasing/correction can be performed and the error correction capacity can be fully utilized. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an error correction apparatus, a reproduction apparatus, and a reproduction method, and more particularly to an error correction apparatus that corrects a code error of a signal to which an error correction code based on a Reed-Solomon code is added, and a reproduction apparatus that reproduces and reproduces the error. Regarding the method.

  In an optical disc having a high recording density, for example, a Blu-ray Disc, an error correction block (ECC block) called a picket code is used in order to improve correction capability for a burst error of a reproduction signal due to a very thin cover layer. ) (See Non-Patent Document 1, for example). That is, the ECC block is configured in units of 64 kbytes of user data, and the user data is protected by a Reed-Solomon code composed of 304 code words. Each code word of the Reed-Solomon code is 216. 6 and 32 parity symbols. As shown in FIG. 6, an ECC block of 152 bytes wide and 496 bytes long is formed. One code word is composed of data every other line in the vertical direction.

  In this one ECC block, the above-mentioned four picket code columns are arranged at equal intervals, and the three right-hand picket codes are error-corrected and protected by a burst indicator subcode (BIS). . The BIS codeword is 62 symbols including 30 information symbols and 32 parity symbols. Each of the 3 picket sequences is composed of 496 bytes (in FIG. 6, the most significant values are B0 and B1 respectively). , B2 column) are interleaved and stored.

  That is, as shown in FIG. 6, the main signal is subjected to the error correction code by the Reed-Solomon code in the vertical direction of the ECC block configuration, and the BIS having information different from the main signal is also subjected to the error correction code by the Reed-Solomon code, It is embedded in the main signal constituting the ECC block as information for notifying an error position called Picket at a predetermined interval. Further, a synchronization signal Sync indicating a synchronization position is inserted at the beginning of each row in the horizontal direction of the ECC block (data recording method of the optical disk).

  FIG. 7 is a block diagram showing an example of a conventional error correction apparatus and an outline of a peripheral circuit. The reproduction signal of the format shown in FIG. 6 reproduced from the recording medium is detected by the synchronization detection circuit 11 and demodulated by the demodulation circuit 12 based on the timing of the synchronization signal Sync. The demodulated data obtained by the demodulation circuit 12 is written in the ECC block memory 13 in units of ECC blocks. The demodulated data written in the ECC block memory 13 is once read and supplied to the error detection and correction circuit 14, where error detection and error correction are performed.

  In the above error correction, for example, when the synchronization signal SY0 and the picket code B0 shown in FIG. 8 are known to be errors, 38 bytes of data D0 to data D37 between the synchronization signal SY0 and the picket code B0 are regarded as errors. Correct the deemed disappearance. The data error-corrected by the error detection / correction circuit 14 is written into the ECC block memory 13 again.

  Thereafter, the demodulated data read from the ECC block memory 13 is supplied to the subsequent signal processing circuit 15 where subsequent signal processing such as descrambling / deinterleaving is performed and then output as reproduction data. The circuit section from the demodulating circuit 12 to the subsequent signal processing circuit 15 constitutes a memory access block 16. The timing generation circuit 17 generates processing timing signals for the circuits 12, 14, and 15 in the memory access block 16 and supplies them to the circuits 12, 14, and 15.

  As described above, the reproduction signal in the above format uses the synchronization signal and the picket code as an index (pointer) indicating the position of the burst error, and regards a place where the synchronization signal and the picket code are continuously erroneous as a burst error, Perform erasure correction. This enables a burst error that greatly exceeds the correction capability obtained from the distance of the Reed-Solomon code applied in the vertical direction of the main data.

  In general, in order to read out desired data, address information is included at regular intervals of information data. As described above, the reproduction circuit detects the synchronization signal and the leading address of the ECC block from the signal reproduced from the recording medium by the synchronization detection circuit 11, and demodulates the subsequent information data in units of ECC blocks after the demodulation of the information data. Is temporarily stored, the information data in the ECC block memory 13 is read out, and error correction processing is performed by the error detection and correction circuit 14. As described above, error correction using the picket code is performed based on the detection result of the synchronization signal Sync. In order to use it as an index representing the position of an error, the ECC block memory 13 must be sent from the synchronization detection circuit 11 as to whether or not the detection result of the synchronization signal is available and held together with the information data.

Edited by Hiroki Eda et al., “Next-generation optical disc dismantling new book”, Nikkei BP, 2003, 72 pages

  However, in the error correction apparatus shown in FIG. 7, the synchronization signal is not subjected to the error correction code. For example, when decoding or demodulation having high detection performance such as Viterbi decoding is performed, the synchronization signal is originally a burst error. Even if it is better to do so, there are cases where it is regarded as error-free. In this case, the correction capability may be improved by treating the synchronization signal as an error.

  In addition, the synchronization detection circuit in the recording medium playback apparatus may transfer information to the ECC block memory because the head of the ECC block cannot be determined when the synchronization signal and the address cannot be reproduced due to a defect in the recording medium. Can not. In this case, transfer to the ECC block memory is started when the next address can be normally acquired.

  However, in this case, the information transferred in the past and the detection result of the synchronization signal remain in the ECC block memory, and if the detection result of the past synchronization signal is indicated as normal, the information is actually due to a defect. In spite of the error, the error correction circuit in the conventional reproducing apparatus does not perform erasure correction and reduces the correction capability.

  The present invention has been made in view of the above points, and an error correction apparatus capable of treating main data between a synchronization signal and subsequent predetermined information data as a burst error regardless of the detection result of the synchronization signal, and reproduction An object is to provide an apparatus and a reproduction method.

  Another object of the present invention is to provide an error correction device, a playback device, and a playback method capable of erasure correction without degrading the correction capability even when the synchronization signal and address cannot be played back due to a defect in the recording medium. Is to provide.

In order to achieve the above object, the error correction apparatus according to the first aspect of the present invention provides L information blocks (L is 2) that are obtained by dividing the first information data into predetermined bytes and are composed of a predetermined number of bytes. The above natural number), the synchronization signal arranged at the head of the information transmission direction of each L information block, and the second information data respectively inserted between the L information blocks And the first error correction code by the first Reed-Solomon code is added to the first information data, and the synchronization block is arranged with M rows (M is a natural number of 2 or more), An error for performing error correction on an error correction block having a configuration in which a second error correction code based on a second Reed-Solomon code is added to the second information data independently of the first information data. Correction device
The synchronization signal is extracted from the input error correction block, the synchronization signal detection means detects whether the synchronization signal is normally detected, and the first and second error correction codes from the input error correction block. Is used to perform error correction of the first and second information data, and is determined to be an error immediately before or immediately after the signal indicating that the signal is not normally detected and input from the synchronization signal detecting means. Error correction means for performing erasure correction of the first information data constituting the information block between the second information data and whether or not the synchronization signal is normally detected by the synchronization signal detection means. And synchronization signal control means for converting all of the synchronization signals of the error correction block inputted to the correction means with error.

  In the present invention, since all of the synchronization signals of the error correction block input to the error correction means are converted with errors regardless of whether the synchronization signal is normally detected or not, the error correction means The synchronization signal is normally detected in the erasure correction of the first information data constituting the information block between the second information data determined to have an error immediately before or after the synchronization signal of the error correction block to be corrected. Even if you do.

  In order to achieve the above object, an error correction apparatus according to a second invention is an error correction apparatus for performing error correction on an error correction block having a configuration similar to that of the first invention, wherein an input error is corrected. The synchronization signal is extracted from the correction block, and the synchronization signal detection means for detecting whether or not the synchronization signal is normally detected, and the first and second error correction codes from the input error correction block are used. The first and second information data are error-corrected, the signal input from the synchronization signal detecting means indicating that the data has not been detected normally, and the second determined to have an error immediately before or after the signal An error correction means for performing erasure correction of the first information data constituting an information block between the information data, and a result of error correction by the error correction means, as a result of the first information block immediately before or immediately after the synchronization signal. Of the error correction block input to the error correction means regardless of whether or not the synchronization signal is normally detected by the synchronization signal detection means. Synchronous signal control means for converting all signals with errors and performing error correction of the error correction block by the error correction means again is provided.

  In the present invention, when the first information data constituting the information block immediately before or immediately after the synchronization signal is uncorrectable as a result of error correction by the error correction means, it is related to whether or not the synchronization signal is normally detected. In addition, since all the error correction block synchronization signals input to the error correction means are converted into errors and the error correction block is corrected again by the error correction means, the error correction means The synchronization signal is normally detected in the erasure correction of the first information data constituting the information block between the second information data determined to have an error immediately before or after the synchronization signal of the error correction block to be corrected. Even if you do.

In order to achieve the above object, the playback device according to the third aspect of the present invention provides L information blocks (L is the number of information blocks each having a predetermined number of bytes obtained by dividing the first information data into predetermined bytes. A natural number of 2 or more), a synchronization signal arranged at the head of the information transmission direction of each of the L information blocks, and second information data inserted between each of the L information blocks, And a first error correction code based on the first Reed-Solomon code is added to the first information data, in which M rows (M is a natural number of 2 or more) are arranged. An error correction block having a configuration in which a second error correction code based on a second Reed-Solomon code is added to the second information data independently of the first information data is addressed at regular intervals. Record with information Body is recorded in a reproduction apparatus which reproduces the error correction block and address information from the recording medium,
A synchronization signal detection result indicating whether or not the synchronization signal extracted from the signal read from the recording medium is normally detected is output together with the first and second information data, and is normally reproduced first in the error correction block. Synchronization signal detection means for outputting the position information of the synchronization signal reproduced normally based on the address information that has been reproduced, and the synchronization signal detection result, position information, and first and second information output from the synchronization signal detection means The storage means for temporarily holding the data, the second information data is read from the storage means and error correction is performed, and the synchronization signal detection result, the position information, and the first information data are read from the storage means to correct the error. The synchronization signal detection result of the synchronization signal reproduced before the synchronization signal indicated by the position information in the block is regarded as an error, and the synchronization signal detection result corresponding to the error is detected. The erasure correction of the first information data constituting the information block between the signal and the second information data determined to have an error immediately before or after the synchronization signal is performed, and from the synchronization signal indicated by the position information An error correction means for correcting an error of the first information data using a synchronization signal detection result of the synchronization signal is provided for a signal reproduced later.

  According to the present invention, all the synchronization signal detection results of the synchronization signal reproduced before the normally reproduced synchronization signal obtained based on the address information reproduced normally first in the error correction block are regarded as errors. Erasure correction of the first information data constituting the information block between the synchronization signal corresponding to the detected synchronization signal detection result and the second information data determined to have an error immediately before or immediately after the synchronization signal I do.

In order to achieve the above object, the reproduction method according to the fourth aspect of the invention provides L information blocks each having a predetermined number of bytes obtained by dividing the first information data into predetermined bytes (L is A natural number of 2 or more), a synchronization signal arranged at the head of the information transmission direction of each of the L information blocks, and second information data inserted between each of the L information blocks, And a first error correction code based on the first Reed-Solomon code is added to the first information data, in which M rows (M is a natural number of 2 or more) are arranged. An error correction block having a configuration in which a second error correction code based on a second Reed-Solomon code is added to the second information data independently of the first information data is addressed at regular intervals. Record with information Body are recorded in, from the recording medium a reproducing method for reproducing error correction block and address information,
A first step of outputting a synchronization signal detection result indicating whether or not a synchronization signal extracted from a signal read from the recording medium has been normally detected together with the first and second information data, and a signal read from the recording medium A second step of outputting the position information of the normally reproduced synchronization signal based on the address information normally reproduced first in the error correction block; the synchronization signal detection result; the position information; and the first and second A third step of temporarily holding the information data in the storage means, reading out the second information data from the storage means to perform error correction, and synchronizing signal detection results, position information, and first information data from the storage means A fourth step in which all the synchronization signal detection results of the synchronization signal reproduced before the synchronization signal indicated by the position information in the error correction block are all errors, Loss of the first information data constituting the information block between the synchronization signal corresponding to the detected synchronization signal detection result and the second information data determined to have an error immediately before or immediately after the synchronization signal And a fifth step of performing error correction of the first information data using a synchronization signal detection result of the synchronization signal for a signal reproduced after the synchronization signal indicated by the position information while performing correction. It is characterized by.

  According to the present invention, all the synchronization signal detection results of the synchronization signal reproduced before the normally reproduced synchronization signal obtained based on the address information reproduced normally first in the error correction block are regarded as errors. Erasure correction of the first information data constituting the information block between the synchronization signal corresponding to the detected synchronization signal detection result and the second information data determined to have an error immediately before or immediately after the synchronization signal I do.

  According to the error correction apparatus of the present invention, the first information data constituting the information block between the second information data determined to have an error immediately before or immediately after the synchronization signal of the input error correction block is determined. Since the erasure correction is performed even when the synchronization signal is detected normally, the erasure correction can be performed even when the error cannot be corrected by erroneously detecting the state of the synchronization signal indicating the error position of the erasure correction as normal. This can make full use of the error correction capability.

  Further, according to the reproducing apparatus and the reproducing method of the present invention, the synchronization signal reproduced before the normally reproduced synchronization signal obtained based on the address information normally reproduced first in the error correction block is obtained. An information block between the synchronization signal corresponding to the synchronization signal detection result determined to be an error and the second information data determined to have an error immediately before or immediately after the synchronization signal Since the erasure correction of the first information data is performed, the correction capability is lowered by using a more accurate synchronization signal detection result without using a synchronization signal detection result different from the actual one. The data can be reproduced satisfactorily.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a main part of a first embodiment of an error correction apparatus according to the present invention. In this embodiment, a circuit portion including the ECC block memory 13 and the error detection / correction circuit 14 in the memory access block 16 shown in FIG. 7 is replaced with an ECC block memory 21, an error detection / correction circuit 22, and a Sync signal (synchronization signal). The control circuit 23 is configured.

  The ECC block memory 21 is supplied with demodulated data obtained by demodulating by the demodulating circuit 12 shown in FIG. 7, and is written in the ECC block unit described above. The error detection / correction circuit 22 performs error detection / correction on the demodulated data read from the ECC block memory 21 in the same manner as the error detection / correction circuit 14 shown in FIG.

  The SYNC signal control circuit 23 indicates that the error detection / correction circuit 22 causes an error correction failure even when the synchronization signal in the reproduction signal is normally reproduced, and the error correction failure occurs in the ECC block. When the information block is immediately after or immediately before the synchronization signal, the write control is performed so that all the synchronization signals on the ECC block memory 21 are erroneous. As a result, the error detection / correction circuit 22 performs error correction again on the ECC block having the synchronization signal that is all erroneous by the write control.

  Here, since the present embodiment is an error correction apparatus that corrects an error with respect to a reproduction signal of an ECC block having the format shown in FIG. 6, first, details of the format of the ECC block shown in FIG. 6 will be described. . FIG. 2 shows an example of a method for generating an ECC block. In the figure, user data 31 of 32 × 2048 bytes, which is first information data such as video or music information, is added with a 4-byte error detection code EDC generated every 2048 bytes, and 32 × 2052 bytes. After that, the data frame 33 is scrambled into a scrambled data frame 34 by a predetermined method.

  Subsequently, the scrambled data frame 34 is a data block 35 having 216 bytes (216 rows) in the row (horizontal) direction and 304 bytes (304 columns) in the column (vertical) direction, and further RS (248, 216, 216) in the column direction. 33), the long distance code (LDC) error correction coding is performed by the Reed-Solomon code 36, and the LDC block 37 having 304 columns and 248 rows is generated. The LDC block 37 is composed of 304 code words, and one code word is composed of 216 information symbols and 32 parity symbols.

  The LDC block 37 is interleaved every 2 × 2 in the column direction of the block to form an LDC cluster 38 of 152 bytes horizontally and 496 bytes vertically (152 columns and 496 rows). On the other hand, the BIS is error-correction-encoded with the Reed-Solomon code of RS (62, 30, 33) and arranged as a picket in the ECC block as described above, thereby generating an ECC cluster 39. The

  As shown in FIG. 6, this ECC cluster 39 inserts data bytes of 152 columns and 496 rows of D0 to D75391 consisting of 3 bytes of main data and parity, and BIS is inserted every 38 bytes (38 columns) in the horizontal direction. In addition, a synchronization signal Sync is added to the head, and an ECC block having a synchronization block configuration is configured with 155 bytes + Sync. Further, as shown in FIG. 6, the BIS includes address information of 9 bytes from the head of each address unit. The address information is uniformly arranged at a constant address unit interval of 4805 (= (38 × 4 + 3) × 31) bytes (not including Sync) before modulation (after demodulation). The address information is error correction encoded with Reed-Solomon code of RS (9, 5, 5). The ECC block is recorded in the horizontal direction and from top to bottom in FIG.

  Next, the operation of the embodiment of FIG. 1 will be described. The error detection / correction circuit 22 detects and corrects the data of the ECC block of the format of FIG. 6 read from the ECC block memory 21. At this time, the error of the synchronization signal Sync and picket code of FIG. If the main data sandwiched between a certain sync signal Sync and an erroneous picket code is erasure-corrected, and error correction after the erasure correction results in an uncorrectable error, the error detection / correction circuit 22 Is sent to the Sync signal control circuit 23.

  In the sync control circuit 23, an error correction failure occurred in the error detection / correction circuit 22, and the location where the error correction failure occurred was an information block of a 38-byte column immediately after the synchronization signal Sync in the ECC block. In this case, or in the case of an information block of a 38-byte column immediately before the synchronization signal Sync, all the synchronization signals Sync on the ECC block memory 21 are replaced with errors.

  Subsequently, the error detection and correction circuit 22 reads the ECC block in which the synchronization signal Sync is replaced with an error from the ECC block memory 21 and performs error detection and correction again. As a result, erasure correction can be performed on the main data of the 38-byte column immediately after or immediately before the synchronization signal Sync in the ECC block. As a result, it is better to assume that the synchronization signal is detected by the synchronization detection circuit 11 as an error. However, for any reason, the error signal is properly corrected even for the synchronization signal SYNC that is erroneously determined to be normal. Is called.

  Usually, the maximum value of erasure correction in the case of having an error pointer is the minimum inter-code distance-1 (the number of parity). In this example, the minimum inter-code distance of the Reed-Solomon code is 33, so 32 erasure corrections. Is possible. When E erasure corrections are performed, the number of corrections n that can be corrected other than erasure correction is ((minimum inter-code distance-1) -E) / 2, and the maximum number of corrections is E + n. If the erasure correction is 0, 16 corrections are possible.

  Here, there are four synchronization signals Sync erroneously determined to be normal even though a burst error has occurred originally, and the picket following the Sync (or the picket immediately before the Sync) is BIS. When it is determined that there is an error by correction, it is determined that there is no error in these four syncs, so the erasure correction pointer does not stand. Therefore, all the errors of the data with burst errors are corrected other than erasure correction. Is error corrected.

  In this case, conventionally, the number E of erasure corrections described above is 0, the number n of corrections that can be corrected other than erasure correction is 16, and the maximum number of corrections by corrections other than erasure correction is 16. Here, since there are four errors which are burst errors, the number of corrections for other data is up to twelve.

  On the other hand, in this embodiment, since all the synchronization signals SYNC on the ECC block memory 21 are replaced with errors, the above four syncs and pickets (or their pickings) determined to have errors by BIS correction following the four syncs. The burst error of the main data during the BIS correction immediately before the four syncs is determined to be erasure corrected (erasure correction number E is 4), and the number n that can be corrected other than erasure correction is ((minimum) Since the inter-code distance is 1) -E) / 2), it is 14 (maximum correction number 18).

  As a result, when there are 13 or 14 errors other than burst errors, for example, when there are 4 burst errors in the past, the number of corrections for other data is 12, so that all cannot be corrected. However, according to the present embodiment, even if the correction cannot be performed by the first correction, all 13 or 14 errors other than the burst error can be corrected by the erasure correction, and the error correction capability can be fully utilized. Can do.

  Next, a second embodiment of the error correction apparatus of the present invention will be described. FIG. 3 is a block diagram showing the main part of the second embodiment of the error correction apparatus according to the present invention. In the figure, the same components as those in FIG. In the present embodiment, when performing error detection / correction on the demodulated data stored in the ECC block memory 21 in units of ECC blocks, the Sync correct / incorrect flag indicating whether the demodulated data before the error correction and the synchronization signal are correct or not is received from the ECC block memory 21. Read and supply to the SYNC signal control circuit 25.

  The SYNC signal control circuit 25 replaces only the sync correct / incorrect flag with the sync error flag by the flag control signal from the error detection / correction circuit 26 out of the inputted demodulated data and the sync correct / incorrect flag before error correction. It is supplied to the error detection and correction circuit 26 together with the previous demodulated data. Based on the input demodulated data before error correction and the Sync error flag, the error detection / correction circuit 26 determines that all the synchronization signals Sync indicating the error position of erasure correction in the demodulated data before error correction are errors. Perform erasure correction.

  Thereby, the error detection / correction circuit 26 should correct the data error other than the burst error by correction other than the erasure correction, and should be regarded as an error in the synchronization signal detection. Even for the synchronization signal SYNC that is erroneously determined to be normal, error correction data that has been subjected to good error correction is generated, supplied to the ECC block memory 21, and written back. The present embodiment also has the same effect as the first embodiment.

  Next, an embodiment of the playback apparatus of the present invention will be described. FIG. 4 shows a block diagram of an embodiment of a reproducing apparatus according to the present invention. In the figure, the reproduction apparatus is composed of a synchronization detection circuit 41, a memory 45, an error correction circuit 46, a subsequent signal processing circuit 47, and an image / audio decoding processing circuit 48. The synchronization detection circuit 41 includes a synchronization detector 42 that detects a synchronization signal in a reproduction signal, a demodulation circuit 43 that demodulates information data in the reproduction signal, and an address detector 44 that detects an address.

  Next, the operation of the present embodiment will be described. For example, a reproduction signal obtained by time-sequentially synthesizing ECC blocks of the format shown in FIG. 6 in units of ECC blocks from a recording medium (not shown) is reproduced by reproduction means (not shown), and the reproduction signal obtained thereby is a synchronization detection circuit. Supplied to the synchronous detector 42 in 41. The synchronization detection circuit 42 detects a synchronization signal (Sync) from the input reproduction signal, supplies a synchronization signal determination result as to whether or not the synchronization signal is normally detected, to the memory 45, and is shown in the memory map of FIG. Store in place.

  Further, the synchronization detector 42 supplies information data following the synchronization signal in the input reproduction signal to the demodulation circuit 43 to demodulate. The information data demodulated and output from the demodulation circuit 43 is stored in a predetermined location shown in the memory map of FIG. 5 in the memory 45, and the BIS information is supplied to the address detector 44 to detect the address. That is, in the ECC block format shown in FIG. 6, picket codes in the right three columns are error correction encoded by BIS, and information symbols of this BIS picket code form address information.

  Since the data position in the ECC block is known only after the address is detected, the information data demodulated and output from the demodulation circuit 43 is stored in a small capacity memory (not shown) and then detected by the address detector 44. The data is read based on the memory address generated based on the detected address information and stored in the memory 45.

  The synchronization signal determination result, information data, and BIS information stored in the memory 45 are sequentially read out by the error correction circuit 46 and subjected to correction processing. First, BIS correction processing is performed, and information data correction processing is performed based on the error position and the determination result of the synchronization signal.

  For example, in FIG. 5, the determination result of the synchronization signal Sync immediately before (left adjacent) the information data D304 in the third row is incorrect, and the BIS information B6 immediately after (right adjacent) the information data D341 is an error due to BIS correction. If it is indicated as a position, the information data D304 to the information data D341 sandwiched between them are erasure-corrected on the assumption that there is a high probability that a burst error has occurred.

  Furthermore, if the BIS information B7 in the third row in FIG. 5 also indicates an error position due to BIS correction, that is, if there is an error in the BIS information B6 and B7 at both ends of the information data D379 from the information data D342, Information data D342 to information data D379 are erasure-corrected on the assumption that a burst error is likely to occur. The corrected information data is rewritten in the memory 45 and then read out and supplied to the subsequent signal processing circuit 47, where subsequent signal processing such as descrambling / deinterleaving is performed, and then via the memory 45. Thus, it is converted into reproduction data and sent to the image / audio decoding circuit 48 to be converted into a reproduction image / audio signal.

  Here, for example, it is assumed that there is a burst error due to a defect in the medium from the top of the ECC block to the third line (the first to third lines of address unit 0 in FIG. 6). In this case, since the BIS information in the first to third lines of the address unit 0 is incorrect due to a burst error, the address information cannot be demodulated correctly. For this reason, where the reproduction information data is in the ECC block. I can't judge. That is, since it cannot be known which address unit information data, it is not transferred to the memory 45.

  Next, if the BIS information of the address unit 1 is normally read, the address of the address unit 1 is detected, and the synchronization signal Sync at the head of the address unit 1 is correctly read, each information of the address unit 1 is stored in the memory 45. Transfers normally. In such a case, normal data of the past (one round before the memory 45) remains in each data of the address unit 0 in the memory 45. In the error correction circuit 46, the BIS information can be restored by correction processing. However, in the conventional method, the synchronization detection result is written in the memory 45, that is, the result of one cycle before the memory 45 is used as it is.

  As described above, when the information data correction processing includes an error in both the synchronization signal and the BIS information in the ECC block format shown in FIG. 5 or FIG. 6, the information data sandwiched between them is lost and corrected. Therefore, if the past data remains in the memory 45, the past detection result left in the memory 45 is normal, so even if it is actually (currently), it is lost. Correction processing by correction is not possible.

  Usually, the maximum value of erasure correction when having an error pointer is the minimum intersymbol distance-1 (the number of parity). In this example, 32 erasure corrections are possible, but when erasure correction is not performed, Up to (minimum inter-code distance-1) / 2, in this example, only 16 can be corrected. Therefore, as in this example, when the detection result of the synchronization signal that is originally NG is treated as normal, the correction processing capability is reduced.

  Therefore, in the present embodiment, the synchronization detection circuit 41 uses the position information of the synchronization signal when the address information is normally reproduced for the first time in the ECC block (that is, the head of the address unit including the address that is normally reproduced). (Synchronization signal detection result) is sent to the memory 45 together with each data and stored in the memory 45. For example, when the address of the BIS information of the address unit 0 cannot be read and the address of the BIS information of the address unit 1 can be read, the head synchronization signal Sync of the address unit 1 is not correctly read, and the position information of the synchronization signal Sync is obtained. , The last two bytes in the memory 45 are written as indicated by 50 in FIG.

  The error correction circuit 45 is read from the memory 45 in which the position information of the synchronization signal Sync that has been correctly read first is written, and based on the position information of the synchronization signal Sync that is normally reproduced first. The previous synchronization signal detection result is not trusted and is treated as all error data, and the error correction operation is performed by trusting the synchronization signal detection result after the position information of the head synchronization signal of the address unit 1 in the memory 45. If the detection result of the head synchronization signal of the address unit 1 is incorrect, information on the subsequent synchronization signal position detected normally is written in the last position of the memory 45.

  As a result, according to the present embodiment, the detection result before one round of the memory is not used, so that the actual medium error (error) state can be obtained without using the detection result of the synchronization signal different from the actual one. Correction processing by erasure correction along the line is possible, and good data can be reproduced without degrading the correction capability.

  In this embodiment, the synchronization signal detection result at the head of the address unit including the address that is normally reproduced is used as the position information of the synchronization signal when it is normally reproduced. However, the synchronization signal is normally obtained. However, information may be held and the address of the information may be calculated and transferred to the memory after the address is detected. This can be achieved by increasing the memory capacity of the aforementioned small capacity memory (not shown).

  It is also possible to fetch data into the memory 45 from a normal synchronization signal (fourth sync of the address unit 1 in FIG. 5) after reading 9 bytes of a picket protected by BIS. In this case, the Sync before the Sync is not trusted, and all are determined to be errors.

  Although the above embodiment has been described as being applied to the Blu-ray ECC block, the present invention is not limited to this, and the first information data such as video or music information is stored every predetermined byte. L information blocks (L is a natural number equal to or greater than 2 and 4 in the above embodiment) and L information blocks, which are obtained by dividing the information block into a predetermined number of bytes (38 in the above embodiment). A synchronization block composed of a synchronization signal arranged at the head of the information transmission direction of each information block and second information data respectively inserted between L information blocks is divided into M rows (M is 2 The above-mentioned natural number is 496) in the embodiment, and the first error correction code by the first Reed-Solomon code is added to the first information data, and the second Information For data applicable to all of the second error correction block which is an error correction code added in the configuration according to the second Reed-Solomon code independently of the first information data. Further, the SYNC signal control circuit may be provided in the error detection / correction circuit, and all the syncs may be handled as errors during correction.

It is a block diagram of the principal part of 1st Embodiment of the error correction apparatus of this invention. It is explanatory drawing of an example of the production | generation method of the ECC block to which this invention is applied. It is a block diagram of the principal part of 2nd Embodiment of the error correction apparatus of this invention. It is a block diagram of one embodiment of the playback apparatus of the present invention. FIG. 5 is a diagram illustrating an example of a memory map of a memory in the playback device of FIG. 4. It is a figure which shows an example of the format of the ECC block applied to this invention. It is a block diagram of an example of the conventional error correction apparatus. It is a figure which shows the format of the ECC block for demonstrating the error correction operation | movement in FIG.

Explanation of symbols

21 ECC block memory 22, 26 Error detection and correction circuit 23, 25 SYNC signal control circuit 41 Synchronization detection circuit 42 Synchronization detector 43 Demodulation circuit 44 Address detector 45 Memory 46 Error correction circuit 47 Subsequent signal processing circuit 48 Image / audio decoding process circuit

Claims (4)

The first information data obtained by dividing the first information data into predetermined bytes, the number of information blocks composed of the predetermined number of bytes (L is a natural number of 2 or more), and the information blocks for each of the L information blocks A synchronization block composed of a synchronization signal arranged at the head of the information block in the information transmission direction and second information data respectively inserted between the L information blocks is divided into M rows (M is 2 or more). (Natural number) arranged, and a first error correction code by a first Reed-Solomon code is added to the first information data, and the second information data is the first information correction code. An error correction apparatus that performs error correction on an error correction block having a configuration in which a second error correction code based on a second Reed-Solomon code is added independently of one information data,
Synchronizing signal detection means for extracting the synchronizing signal from the input error correction block and detecting whether the synchronizing signal is normally detected;
The first and second information data are corrected from the input error correction block using the first and second error correction codes, and the error detected from the synchronization signal detecting means is detected normally. Error correction for performing erasure correction of the first information data constituting the information block between a signal indicating that there is no error and the second information data determined to have an error immediately before or after the signal Means,
Regardless of whether or not the synchronization signal is normally detected by the synchronization signal detection means, synchronization signal control means for converting all of the synchronization signals of the error correction block input to the error correction means with errors. An error correction apparatus comprising: The first information data obtained by dividing the first information data into predetermined bytes, the number of information blocks composed of the predetermined number of bytes (L is a natural number of 2 or more), and the information blocks for each of the L information blocks A synchronization block composed of a synchronization signal arranged at the head of the information block in the information transmission direction and second information data respectively inserted between the L information blocks is divided into M rows (M is 2 or more). (Natural number) arranged, and a first error correction code by a first Reed-Solomon code is added to the first information data, and the second information data is the first information correction code. An error correction apparatus that performs error correction on an error correction block having a configuration in which a second error correction code based on a second Reed-Solomon code is added independently of one information data,
Synchronizing signal detection means for extracting the synchronizing signal from the input error correction block and detecting whether the synchronizing signal is normally detected;
The first and second information data are corrected from the input error correction block using the first and second error correction codes, and the error detected from the synchronization signal detecting means is detected normally. Error correction for performing erasure correction of the first information data constituting the information block between a signal indicating that there is no error and the second information data determined to have an error immediately before or after the signal Means,
As a result of error correction by the error correction means, when receiving a correction result indicating that the first information data constituting the information block immediately before or immediately after the synchronization signal cannot be corrected, the synchronization signal detection Regardless of whether or not the synchronization signal is normally detected by the means, all the synchronization signals of the error correction block input to the error correction means are converted into errors, and the error correction by the error correction means is performed. An error correction apparatus comprising: synchronization signal control means for performing block error correction again. The first information data obtained by dividing the first information data into predetermined bytes, the number of information blocks composed of the predetermined number of bytes (L is a natural number of 2 or more), and the information blocks for each of the L information blocks A synchronization block composed of a synchronization signal arranged at the head of the information block in the information transmission direction and second information data respectively inserted between the L information blocks is divided into M rows (M is 2 or more). (Natural number) arranged, and a first error correction code by a first Reed-Solomon code is added to the first information data, and the second information data is the first information correction code. An error correction block having a configuration in which a second error correction code based on a second Reed-Solomon code is added independently of the information data of 1 is recorded on a recording medium with address information at regular intervals. Before A reproduction apparatus for reproducing the error correction block and the address information from the recording medium,
A synchronization signal detection result indicating whether or not the synchronization signal extracted from the signal read from the recording medium is normally detected is output together with the first and second information data, and is first in the error correction block. Synchronization signal detection means for outputting position information of the synchronization signal reproduced normally based on the address information reproduced normally,
Storage means for temporarily storing the synchronization signal detection result, the position information, and the first and second information data output from the synchronization signal detection means;
The second information data is read from the storage means to perform error correction, and the synchronization signal detection result, the position information, and the first information data are read from the storage means, and the error correction block includes the The synchronization signal detection result of the synchronization signal reproduced before the synchronization signal indicated by the position information is regarded as an error, the synchronization signal corresponding to the synchronization signal detection result determined to be an error, and the error immediately before or after the synchronization signal Performing erasure correction of the first information data constituting the information block with the second information data determined to be present, and for a signal reproduced after the synchronization signal indicated by the position information And an error correction means for correcting an error of the first information data using a synchronization signal detection result of the synchronization signal. The first information data obtained by dividing the first information data into predetermined bytes, the number of information blocks composed of the predetermined number of bytes (L is a natural number of 2 or more), and the information blocks for each of the L information blocks A synchronization block composed of a synchronization signal arranged at the head of the information block in the information transmission direction and second information data respectively inserted between the L information blocks is divided into M rows (M is 2 or more). (Natural number) arranged, and a first error correction code by a first Reed-Solomon code is added to the first information data, and the second information data is the first information correction code. An error correction block having a configuration in which a second error correction code based on a second Reed-Solomon code is added independently of the information data of 1 is recorded on a recording medium with address information at regular intervals. Before From the recording medium a reproducing method for reproducing the error correction block and the address information,
A first step of outputting a synchronization signal detection result indicating whether or not the synchronization signal extracted from the signal read from the recording medium is normally detected together with the first and second information data;
A second step of outputting the position information of the synchronization signal normally reproduced based on the address information normally reproduced first in the error correction block from the signal read from the recording medium;
A third step of temporarily storing the synchronization signal detection result, the position information, and the first and second information data in a storage unit;
The second information data is read from the storage means to perform error correction, and the synchronization signal detection result, the position information, and the first information data are read from the storage means, and the position in the error correction block is read. A fourth step in which all the synchronization signal detection results of the synchronization signal reproduced before the synchronization signal indicated by the information are erroneous;
The first information block constituting the information block between the synchronization signal corresponding to the detection result of the synchronization signal determined to be an error and the second information data determined to have an error immediately before or immediately after the synchronization signal In addition to performing erasure correction of the information data, for the signal reproduced after the synchronization signal indicated by the position information, the error correction of the first information data is performed using the synchronization signal detection result of the synchronization signal. 5. A reproduction method comprising: 5 steps.

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