KR0170653B1 - Decoder of the digital video tape recorder - Google Patents

Abstract

Disclosed is a decoder of a digital video tape recorder capable of correctly performing error correction even if data is lost.

The decoder according to the present invention error corrects the sync block output from the encoder by an internal code error correction code attached thereto, and is an error flag which is a signal indicating the result of error correction and whether the identification code and the error corrected sync block are valid. Internal error correction outputted with; An address generator which generates a recording address corresponding to a position marked by the identifier when the sync block corrected with reference to the error flag provided by the internal code error correction unit is valid; A memory unit for recording the sync block provided by the error correction unit in a storage location designated by a write address provided by the address generator; And an outer code error correction unit for correcting the outer code by an outer code error correction code attached to the sync blocks stored in the memory unit, and outputting an error corrected result.

The decoder according to the present invention has the effect of performing correct external call correction by placing the internally corrected sync block in the correct position with reference to the identification code attached to the sync block.

Description

Digital Video Recorder Decoder

1 is a mapping diagram showing the structure of an error correction block.

2 is a view showing the detailed structure of the identifier shown in FIG.

3 is a block diagram showing a decoder of a digital video tape recorder according to the present invention.

4 is a block diagram showing the detailed configuration of the synchronization detection unit and error correction shown in FIG.

FIG. 5 is a timing diagram showing a signal output from the sync detector shown in FIG.

FIG. 6 is a timing diagram showing a signal output from the internal code decoder shown in FIG.

The present invention relates to a decoder of a digital video taper, and more particularly, to a decoder capable of correctly performing error correction even when data is lost.

A digital videotape recorder compresses and encodes video data and records it on a track of a tape. Data recorded on the track may be lost due to a tape defect, a tape running system defect, etc. In this case, an error correction code is added to recover the lost data.

The recording apparatus of the digital video tape recorder divides the compressed video data into sync blocks which are the minimum units of error correction, and adds an error correction code, an identification code, and a synchronization signal to the divided sync blocks.

At this time, the identifier indicates the position in the error correction block composed of a plurality of sync blocks.

The data recorded on the track is read by the pickup device and the original video data is demodulated by the decoder.

In the conventional decoder, video data demodulated from data recorded on a track is recorded in a memory device for recording video data according to a series of addresses determined according to the order of reading by the pickup apparatus.

In the conventional decoder described above, even when the sync block to be located at the head of the error correction block is lost, the problem is that the sync block which is continuous to this is recorded at the head of the error correction block, resulting in insufficient error correction. there was.

In addition, regardless of the result of the error correction, a faulty sync block is also included in the image data.

SUMMARY OF THE INVENTION An object of the present invention is to provide a decoder which overcomes the above-mentioned problems and arranges the remaining data blocks at the correct position even if some data blocks are lost so that correct error correction is performed.

One embodiment according to the present invention to achieve the above object is

The mapped data block is divided into sink blocks, which are the minimum units for error correction, and each encoder block is output to an encoder that adds an inner code error correction code, an outer code error correction code, and an identification code by a two-dimensional error correction method. In the corresponding decoder,

An internal call error correction for error correcting the sync block outputted from the encoder by an internal code error correction code attached thereto and outputting the error block, which is a signal indicating whether the error corrected identification code and the error corrected sync block are valid. government;

An address generator which generates a write address corresponding to a position marked by the identifier when the sync block corrected with reference to the error flag provided by the internal code error correction unit is valid;

A memory unit for recording the sync block provided by the error correction unit in a storage location designated by a write address provided by the address generator; And

And an outer code error correction unit for correcting the outer code by an outer code error correction code attached to the sync blocks stored in the memory unit, and outputting an error corrected result. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a mapping diagram showing the configuration of an error correction block. In an embodiment of the present invention, an error correction code block (hereinafter referred to as an ECC block) has a size of 166 bytes X 39 bytes of DMS and has a two-dimensional error correction structure by an inner code and an outer code. Since the structure of the two-dimensional error correction structure, the internal code, and the external code is well known in the art, detailed description thereof will be omitted.

In the mapping diagram shown in FIG. 1, one row in the lateral direction is called a sink block which is a basic unit of error correction. Therefore, 39 bytes of sync blocks exist in one ECC block. Each sync block consists of 2 bytes of synchronization signal, 2 bytes of identification code (ID), 146 bytes of pure data or external code data, and 16 bytes of internal code data.

In the reproducing measurement, error correction of the ECC block is performed in the lateral direction by an inner arc first and then error correction in the longitudinal direction by an outer arc. At this time, if each sync block is not arranged at the correct position, error correction in the longitudinal direction by the outer arc is insufficient.

2 is a diagram showing the detailed configuration of the identification symbol shown in FIG.

The identifier (ID) is a code consisting of 2 bytes, and the lower 6 bits of the upper byte indicate the sync block number in the ECC block, and the lower 4 bits of the lower byte can be divided into a pair of 2 bits, each of which is an ECC in the track. The block number and track number in the frame are shown.

As can be seen in FIG. 2, video data of one frame is divided into four tracks and four ECC blocks are recorded on one track.

Since 39 sync blocks exist in one ECC block, 156 sync blocks are recorded in one track.

3 is a block diagram illustrating a decoder of a digital VCT according to the present invention. The apparatus shown in FIG. 3 inputs the reproduction signal reproduced from the tape to input the demodulator 30 and the output of the demodulator 30 to demodulate the channel encoded, and refers to the sync block with reference to the synchronization signal added to each sync block. Error correction unit 34 for performing error correction on the ECC block constituted by the sync detector 32 and the sync block separated through the sync detector 32, and a combination thereof. And a source decoder 36 for inputting the output of 34 to decode the original video data (R, G, B signals or Y, RY, BY signals).

4 is a block diagram showing in detail the configuration of the synchronization detector and error correction shown in FIG. The apparatus shown in FIG. 4 inputs the reproduction data provided from the demodulator 30 of FIG. 3 and installs a synchronization signal to indicate a valid section of the synchronization signal. The synchronization flag SYNC_F, the clock CLK, and the data DATA0 By the output of the synchronous detection unit 32 and the output of the synchronous detection unit 32, the identification flag flag ID_F, the clock CLK, and the internal code indicating the valid section of the error correction flag CORRECT_F and the identification code An internal code decoder 34a for outputting error corrected data DATA1, a plurality of memories 34b, 34c for storing the error corrected data DATA1 through the internal code decoder 34a, and an internal code decoder 34a. Input the output of the data to generate the write / read address of the memory 34b and 34c according to the error correction flag (CORRECT_F) and the identification code flag (ID_F), and the data indicating the valid data interval when reading the memory 34b and 34c. Memory (34b, 34c) after error correction to the flag D_E1 and the internal code The control unit 34d for outputting the data DATA4 and the clock CLK rearranged and outputted through the control unit 34, and the external call decoder 34e for inputting the output of the control unit 34d and performing error correction by an external call. It includes.

5 is a timing diagram showing a sync flag SYNC_F output from the sync detector of FIG. The sync detector 32 shown in FIGS. 3 and 4 installs track data to find a sync signal, and outputs a sync flag SYNC_F signal, a clock CKL, and data DATA0. In the period in which the synchronization signal is located, that is, the first two bytes of each sync block, the synchronization flag SYNC_F is 'low'. In FIG. 5, the VHS signal is a signal showing a section in which a signal is recorded in the track, and the dummy data represents meaningless data at the front and rear ends of the track.

The internal code decoder 34a inputs the output of the synchronization detector 32, and an error correction flag (CORRECT_F) indicating whether the data DATA1 error corrected by the 8 internal code and the error correction result by the internal code are valid. And an identification code flag (ID_F) and a clock signal (CLK) indicating a section of the identification code (ID).

6 is a timing diagram showing an error correction flag (CORRECT_F) signal and an identification code flag (ID_F).

The controller 34d inputs the output of the internal coder 34a to refer to the identification code flag ID_F at the time when the error correction flag CORRECT_F per track changes from 'low' to 'high', and internally corrected data. The identification symbol ID is detected from DATA1 and the write addresses ADD1 and ADD2 of the memories 34b and 34c are generated. That is, the data is written to the memories 34b and 34c only when there is no error in the data provided by the internal code decoder 34a.

The memories 34b and 34c are configured such that when one memory performs a write operation, the other read operation is performed. In other words, internally-corrected data DATA1 should be rearranged and output for external call-correction. While one ECC block is written to one memory, the data recorded in the other memory is read and the external-code decoder is read. To 34d. The read addresses ADD1 and ADD2 of the memories 34b and 34c are generated by the controller 34d.

Since only the error corrected sync blocks are written through the internal code decoder when writing to the memory 34b and 34c, dummy data is outputted at the position of the sync block where the error occurs when reading the memory 34b and 34c. .

DATA2, DATA3, and DATA4 represent data output from the memory 34b, 34c and the control unit 34d, respectively, and the D_E1 signal provided from the control unit 34d represents the valid section of the DATA4 signal.

The external call decoder 34e inputs the output of the control unit 34d, performs error correction by the external call, and outputs the error corrected data DATA4.

As described above, the decoder of the present invention has the effect of performing correct external call correction by placing the internally corrected sync block in the correct position with reference to the identification code attached to the sync block. .

Claims (2)

The encoded data block is divided into sink blocks, which are the minimum units for error correction, and each encoder block is output to an encoder that adds an inner code error correction code, an outer code error correction code, and an identification code by a two-dimensional error correction method. In the corresponding decoder, an error flag is a signal that corrects the sync block outputted from the encoder by an internal code error correction code attached thereto and indicates whether the error corrected result and the identification code and the error corrected sync block are valid. An error code corrector for outputting along with the output; An address generator which generates a write address corresponding to a position marked by the identifier when the sync block corrected with reference to the error flag provided by the internal code error correction unit is valid; A memory unit for recording a sync block provided by the error correction unit in a storage location designated by a write address provided by the address generator; And an outer code error correcting unit for correcting outer code errors by an outer code error correction code attached to the sync blocks stored in the memory unit, and outputting an error corrected result. The decoder of claim 1, wherein the memory unit alternately performs writing and reading operations at intervals at which the data block is written, and has at least two memories corresponding to the size of the data block.