JPH0783275B2 - Error correction code decoding device - Google Patents

Description

The present invention relates to a digital VTR having a structure in which a digital video signal is recorded on a magnetic tape by a rotary head and a digital video signal is reproduced from the magnetic tape by the rotary head. The present invention relates to a decoding device suitable for use in a decoding device for error correcting code.

[Outline of Invention]

According to the present invention, a first error correction code (referred to as an outer code) and a second error correction code (referred to as an inner code) in two different directions of a two-dimensional array of digital data, for example, in a horizontal direction and a vertical direction, respectively. In the decoding device for the error-correcting code that has been encoded with, the output decoded by the decoding device for the inner code 12 is supplied to the large-capacity memory 13, and this memory 13 is used to convert the time series of the digital data into the data for the outer code. By converting the data into a sequence and supplying the output of the memory to the decoding device 14 for the outer code, the memory 13 is used not only for conversion into the data sequence for the outer code, but also for data restoration during deshuffling and variable speed reproduction. Regarding the processing of error information, which can be used in common.

The present invention focuses on the fact that the error information is output from the memory 13 to the decoding device 14 for the outer code, and changes the control of the error information processing by the reproducing operation of the digital VTR. That is, according to the present invention, the data of the decoding result of the inner code and the error flag are supplied to the decoding device of the outer code during the normal reproduction or the slow motion reproduction, and the error is detected by the code of the inner code during the high speed reproduction. It prohibits data writing, writes only playback data with no errors to the buffer memory, and forms a flag that distinguishes between the data that was previously used for playback and the newly played data. is there.

[Conventional technology]

Digital VT for recording / playback of digital video signals
In R, as an error correction code effective for a burst error due to a dropout or the like, a product code is known which performs horizontal and vertical encoding on a two-dimensional array of data.

FIG. 7 shows the structure of a conventional digital VTR reproducing circuit using a product code as an error correction code. Magnetic tape 38
The digital signal reproduced by the rotary head 37 is supplied to the reproduction input section 41 via a rotary transformer (not shown). The reproduction input section 41 is provided with a clock reproduction PLL circuit, a serial-to-parallel conversion circuit, a block synchronization signal detection circuit, an address reproduction circuit, and the like. The output of the reproduction input unit 41 is supplied to the inner code decoder 42, and the inner code decoding process is performed.

The time series of the reproduction data matches the order of the data series of the inner code. Therefore, the inner code decoder 42 does not need to rearrange the data.

Decoder whose reproduced data corrected by the inner code is the outer code
It is supplied to one input of 43 and a multiplexer 44, and is subjected to a decoding process of an outer code by the decoder 43. The output of the outer decoding decoder 43 is supplied to the other input of the multiplexer 44. This multiplexer 44 has a tape speed during reproduction equal to the tape speed during recording during normal reproduction.
The output of the outer code decoder 43 is selected and output, and the outer code decoder 43 is bypassed during variable speed reproduction in which the tape speed during reproduction is different from the tape speed during recording.

At the output of the outer code decoder 43, digital data that has been subjected to error correction processing for each of the inner code and the outer code is obtained. This digital data is written into the large capacity buffer memory 45 via the multiplexer 44. The buffer memory 45 can store, for example, digital data for 3 fields.

Writing to the buffer memory 45 is performed according to the block address added to every two code blocks of the inner code. The buffer memory 45 is provided for data processing during variable speed reproduction in which the inclination of the track formed on the magnetic tape 38 and the inclination of the scanning locus of the rotary head 37 do not match. During variable speed reproduction, the data is reproduced in pieces, and the data stored in the buffer memory 45 also becomes pieces. The buffer memory 45 collectively outputs pieces of data in the same field that are reproduced in pieces. During variable speed reproduction, since the data forming the code block of the outer code is not complete, the multiplexer 44 bypasses the outer code decoder 43 and the outer code is not decoded.

The output read from the buffer memory 45 is supplied to the deshuffling circuit 46. The deshuffling circuit 46 is
In order to return the order of the data series to the original order, the shuffling circuit provided in the recording circuit performs a data rearrangement process reverse to the shuffling circuit. By recording / playback with shuffling and deshuffling, the error is 1
Concentration on the spot is prevented. The deshuffling circuit 46 is composed of a memory. The capacity of this memory depends on the length of the shuffling unit.

The output of the deshuffling circuit 46 is supplied to the error correction circuit 47. The error correction circuit 47 interpolates the error sample data with correct sample data around it. The output of the error correction circuit 47 is supplied to the D / A converter 48,
An analog reproduction video signal is obtained at the output terminal 49.

[Problems to be solved by the invention]

The decoding device of the above-described conventional error correction device has a drawback in that the outer code decoder 43 needs a large capacity memory for rearranging the inner code sequence to the outer code sequence. Further, the deshuffling circuit 46 requires a memory having a capacity corresponding to the unit length of the deshuffling.

Therefore, the applicant has arranged a large-capacity buffer memory between the inner code decoder and the outer code decoder, and by this buffer memory, conversion to the outer code sequence, deshuffling, and data restoration during variable speed reproduction are performed. I applied for a decoding device for error-correcting codes that doubles as.

By the way, the conventional decoding device bypasses the decoding of the outer code during the variable speed reproduction, performs only the decoding of the inner code, and writes only the data determined to have no error due to the decoding of the inner code into the buffer memory 45. Particularly, at the time of variable speed reproduction, since the reproduction data becomes fragmentary, the past data remaining in the buffer memory 45 without being updated increases. Since such past data deteriorates the reproduction image quality, once the written data is read out as described above,
A flag indicating that it is past data was generated.

However, in the case of a configuration in which a buffer memory such as the above-described error correction code decoding device applied above is arranged between the inner code decoder and the outer code decoder, the result of decoding the inner code, as in the conventional case, When the error remains,
If writing to the buffer memory is prohibited, even if only some data in the code block of the inner code has an error, the entire code block is not written, and the error correction capability of the outer code cannot be sufficiently drawn out. .

Therefore, it is an object of the present invention to provide an error correction code decoding device capable of effectively utilizing the correction capability of an outer code during normal reproduction or slow motion reproduction and improving the error correction capability. .

[Means for solving problems]

This invention consists of digital data of a predetermined amount unit.
A digital signal obtained by encoding the first error correction code and the second error correction code in each of the series of digital data located in the first direction and the second direction which are different from each other in the dimensional array at a predetermined speed. An error correction code decoding device for decoding a digital signal recorded on a running recording medium and reproduced from the recording medium, comprising: a second decoding device for decoding a second error correction code;
A memory to which the decoded output of the second decoding device is supplied and which converts a time series of the decoded output into a series of first error correction codes;
A first decoding device for decoding the first error correction code supplied with the output of the memory, a flag memory for storing accompanying information of data written in the memory, and a recording medium running at a predetermined speed for reproduction. At the time of normal reproduction, the decoding output of the second decoding device is written in the memory, and the error flag of the decoding output is written as additional information in the flag memory,
During high-speed reproduction in which the recording medium is run at a speed higher than a predetermined speed for reproduction, only the error-free data in the decoded output of the second decoding device should be written to the memory and the error-free data should be written. Is written as additional information in the flag memory, and when error-free data is read from the memory, the second flag indicating that the data has been read is replaced with the first flag and the flag memory And a memory control means for controlling to write the error correction code.

[Action]

A buffer memory is provided between the inner code decoder 12 and the outer code decoder 14, and the buffer memory converts the inner code sequence to the outer code sequence. Therefore, the data recovery and the rearrangement of the data series at the time of variable speed reproduction can be shared by the buffer memory, the required memory capacity can be reduced, and the hardware scale can be reduced. Further, since the reproduction data can be stored in the buffer during the slow motion reproduction operation, the outer code can be decoded.

During normal reproduction and slow-motion reproduction operation, the data and error flag decoded by the inner code decoder 12 are stored in the buffer memory and the flag memory, and these data and error flag are decoded by the outer code.
It outputs to 14. On the other hand, during high-speed reproduction, only data having no error is written to the buffer memory, the first flag indicating that the data has no error is written to the flag memory, and when this error-free data is read, it is read. The second flag indicating that is written in the flag memory in place of the first flag. By such an operation, the error correction capability of the outer code can be effectively used, and the error correction capability can be improved.

〔Example〕

An embodiment in which the present invention is applied to a decoding device for a digital VTR error correction code will be described below with reference to the drawings. The description of this embodiment will be made in the following order.

a. Recording circuit b. Reproducing circuit c. Configuration of buffer memory 13 d. Processing of error information a. Recording circuit FIG. 3 shows the configuration of the recording circuit of this embodiment. The analog video signal is supplied from the input terminal 1 to the A / D converter 2 to form a digital video signal in which one sample is quantized into, for example, 8 bits, and this digital video signal is supplied to the encoder 3 of the outer code. It The outer code encoder 3 encodes an outer code, for example, a (m + 2, m) Reed-Solomon code.

The digital video data from the encoder 3 for the outer code and the parity symbol for the outer code are supplied to the shuffling circuit 4. The shuffling circuit 4 is provided to change the order of the digital video data so as to prevent concentration of errors even when there are many errors such as variable speed reproduction. The output data of the shuffling circuit 4 is supplied to the encoder 5 for the inner code, and the inner code, for example, (i + 2, i) Reed-Solomon code is encoded. In this embodiment, a product code as shown in FIG. 5 which is conventionally known is used.

That is, the outer code is encoded for every m continuous symbols (samples) of the digital video data, and two parity symbols are generated. The (m + 2) symbols form the outer code block BO. It is formed. The outer code code blocks BO are arranged in i columns, and the inner code is encoded with respect to i symbols that cross the plurality of outer code code blocks BO. Inner code blocks BI composed of (i + 2) symbols are arranged in the horizontal direction in a number of n, and as a whole, [(m + 2) × n] inner code blocks BI form a unit of a product code.

The output data from the encoder 5 of the inner code is the recording output unit 6
Is supplied to. The recording output unit 6 includes a parallel-to-serial converter,
Recording amplifier etc. are included. The recording signal from the recording output unit 6 is transmitted through the rotary transformer (not shown) to the rotary head 7
And is recorded on the magnetic tape 8.

When recording on the magnetic tape 8, as shown in FIG. 6, two inner code blocks BI (diagonal lines indicate parity)
Sync signal SYNC and address AD are added to the beginning of 1
Each synchronization block BS is configured. In practice, the rotary head 7 has a structure of four rotary heads in which two rotary heads are arranged at an angular interval of 180 °. 50H (H: horizontal section) of color video data is recorded on the track formed by the latter half section of one scan of one rotary head pair and the first half section of one scan of the other rotary head pair. I am recording. In the data of 50H, the block of the product code shown in FIG. 5 is formed by the amount of data recorded / reproduced by one rotary head.

b. Reproduction Circuit The signal reproduced from the magnetic tape 8 by the rotary head 7 is supplied to the reproduction input section 11 via a rotary transformer (not shown) as shown in FIG. In the playback input section 11,
A PLL circuit that regenerates a clock synchronized with the regenerated data, a serial-to-parallel conversion circuit, a block synchronization detection circuit, an address regeneration circuit, etc. are provided. The time series of the reproduction data corresponds to the time series of the inner code, and the decoder of the inner code
By being supplied to 12, the inner code is decoded.
The inner code decoder 12 corrects an error of the (i + 2, i) Reed-Solomon code and detects a residual error.

The output data of the inner code decoder 12 is supplied to the buffer memory 13. The buffer memory 13 is composed of a large-capacity buffer memory for storing data and a flag memory for storing error information, as will be described later. In the flag memory, during normal playback and slow motion playback,
An error flag associated with the decoded output data of the inner code decoder 12 is stored. On the other hand, at the time of high speed reproduction, an N / O flag for distinguishing the past data and the new reproduction data is stored in the flag memory.

The reproduced video data and the error flag output from the buffer memory 13 are supplied to the outer code decoder 14. The outer code decoder 14 decodes the (m + 2, m) Reed-Solomon code. Since the time series of the output data from the buffer memory 13 is a series of outer codes, it is not necessary to provide the outer code decoder 14 with a memory for converting the inner code series to the outer code series. In this outer code decoder 14, the error flag read from the buffer memory 13 is treated as error information, and in the outer code decoder 14, one error symbol in one outer code block BO is corrected. Error correction or pointer erasure correction using an error flag.

The output data of the outer code decoder 14 is supplied to the error correction circuit 15. The error correction circuit 15 includes an outer code decoder 14
This is for interpolating error data that cannot be corrected by. The output data of the error correction circuit 15 is taken out to the output terminal 17 via the D / A converter 16. At the time of high speed reproduction in which the speed of the magnetic tape 8 is higher than that at the time of recording,
Since the data forming the outer code block is hardly prepared, only the inner code is decoded, and the outer decoding is not performed. In this case, the error correction circuit 15 alone corrects the error.

c. Configuration of Buffer Memory 13 The buffer memory 13 will be described with reference to FIG. In FIG. 1, a dynamic RAM is used as the buffer memory 13.

In FIG. 1, 21 is a buffer memory for storing digital video signals, 22 is a flag memory for storing error information, and 23 is a memory control circuit. The buffer memory 21 has eight serial-to-parallel conversion circuits 24A, 24.
Input data is supplied via B, ... 24H. Also,
The output data of the buffer memory 21 is taken out via eight parallel-to-serial conversion circuits 25A, 25B, ... 25H.

The input data is 8-bit parallel data of 1 sample data and is supplied to the serial-to-parallel conversion circuits 24A to 24H one bit at a time from the most significant bit. Each of the serial-to-parallel conversion circuits 24A to 24H forms 15-bit parallel data for each bit. Each of the 15-bit parallel output data of the buffer memory 21 is parallel to serial conversion circuit 25A to 2
Each of 5H produces serial data, and 8-bit parallel output data is obtained.

The 1-bit error flag from the latch 26 is supplied to the flag memory 22, and the error flag read from the flag memory 22 is fetched by the latch 27. An error flag from the inner code decoder 12 is supplied to the latch 26 from the terminal 28. The error flag extracted from the latch 27 to the output terminal 29 is supplied to the outer code decoder 14 together with the data read from the buffer memory 21.

The memory control circuit 23 is supplied with the write clock from the terminal 30 and the read clock from the terminal 31. Further, the reproduction mode signal from the terminal 32 is supplied to the memory control circuit 23. The reproduction mode signal becomes, for example, at a high level during normal reproduction operation in which the tape speed during recording is equal to the tape speed during reproduction and slow motion reproduction operation in which the tape speed during reproduction is slower than the tape speed during recording. When the tape speed during reproduction is faster than the tape speed, the level becomes low, for example.

The memory control circuit 23 generates a common address (ADD), a row address strobe signal (RAS), and a column address strobe signal (CAS) for the buffer memory 21 and the flag memory 22, and also a write enable signal for the buffer memory 21.
WE, a write enable signal RWE for the flag memory 22 and a latch pulse are generated. The write clock is synchronized with the input data and the read clock is formed from the reference clock. Therefore, the buffer memory 21 removes the time axis variation.

Further, although omitted in FIG. 1, the synchronization block BS
The reproduction address for each is supplied to the memory control circuit 23, and the write address is determined based on this reproduction address. The memory control circuit 23 controls one or both of the write address and the read address to perform conversion from the inner code sequence to the outer code sequence and deshuffling. Since the address control is commonly performed by the buffer memory 21 and the flag memory 22, each sample data of the output data and the error flag are synchronized.

d. Processing of error information Processing of an error flag input for each sample group in the data from the decoder 12 of the inner code will be described with reference to FIGS. 1 and 2.

FIG. 2A is a timing signal that defines the read cycle (R) and the write cycle (W). Fig. 2B
Indicates the address ADD supplied to the buffer memory 21 and the flag memory 22. For the address, the column address is set first, and then the row address is set. FIG. 2C shows the column address strobe signal RAS, and FIG. 2D
Indicates a row address strobe signal CAS.

In the buffer memory 21, the address ADD is determined, the address strobe signals RAS and CAS are sequentially set to the low level, the column address and the row address are sequentially read, and the write enable signal rises to perform the read operation, and the strobe signal RAS Then, the CAS is sequentially set to the low level, the address is read, and when the write enable signal falls, the write operation is performed. The write operation and the read operation of the flag memory 22 are similar, but are controlled by a write enable signal RWE different from the buffer memory 21.

2E and 2F show examples of the write enable signals WE and RWE in the normal reproduction operation, respectively. Fig. 2E
The write enable signal WE shown in (7) always falls to the low level in the write cycle. Therefore, the buffer memory
The reproduced data to be input is sequentially written in the area 21.

In FIG. 2F, as indicated by 33a and 34a, the write enable signal RWE of the flag memory 22 is set to the low level immediately after reading the error flag of the designated address, and the designated address has an error. Is temporarily written. If there is no error in the data written to the buffer memory 21 in the low level section 33b of the write enable signal WE, an error flag indicating that there is no error is displayed in the flag memory 22 in the low level section 33c of the write enable signal RWE. And is rewritten with an error flag indicating that there is an error already written.

On the other hand, if there is an error in the data written to the buffer memory 21 in the section 34b, the write enable signal RWE is kept at the high level in the section 34c, and an error flag indicating that there is an error already written. It is not rewritten. Thus, during the normal reproduction operation and during the slow-motion reproduction operation in which the data of the outer code block BO is reproduced in several fields, both the data from the inner code decoder 12 and the error flag are stored in the buffer memory 21.
And written in the flag memory 22.

Further, FIGS. 2G and 2H show examples of the write enable signals WE and RWE in the high speed reproduction operation, respectively. In the flag memory 22, the error flag is written after the data is read from the buffer memory 21, and the data at the address is read once and reproduced, as in the normal reproduction operation and the slow-motion reproduction operation described above. It is shown that it was used for processing. Also, the buffer memory
No error data is written to 21.
Data having no error is written in the buffer memory 21, an error flag indicating that there is no error is written in the flag memory 22, and the error flag is rewritten. The data and error flags read from the buffer memory 21 and the Bragg memory 22, respectively, are not subjected to error correction processing by the outer code decoder 14, and an error correction circuit is provided.
It is supplied to 15 and error correction is made.

〔The invention's effect〕

According to the present invention, a large-capacity buffer memory is provided between the inner code decoder and the outer code decoder, and by this buffer memory, data for conversion to the outer code sequence, deshuffling, and variable speed reproduction is provided. In a decoding device for error-correcting code that is designed to perform restoration, when the digital video signal is normally reproduced, the output of the decoder for the inner code is written to the buffer memory, and the corresponding error flag is written to the flag memory for high-speed reproduction. Occasionally, only the error-free data of the output of the inner code decoder is written to the buffer memory, and the flag indicating that there is no error is written to the flag memory, and the error-free data is read from the buffer memory. When this happens, this read line returns a flag indicating that there is no error already written. It was because as rewritten to a flag indicating that is, can be effectively used correction capability of the outer code, it is possible to improve the error correction capability.

[Brief description of drawings]

FIG. 1 is a block diagram showing the structure of a buffer memory according to an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of the buffer memory, and FIG. 3 is a block of a recording circuit according to an embodiment of the present invention. FIG. 4 is a block diagram of a reproducing circuit according to an embodiment of the present invention, and FIGS. 5 and 6 are schematic diagrams showing the formats of an error correction code and recording data in the embodiment of the present invention, respectively. FIG. 7 is a block diagram of a conventional digital VTR reproducing circuit. Description of main codes in the drawings 12: inner code decoder, 13: buffer memory, 14: outer code decoder, 21: buffer memory for storing data, 22: flag memory, 23: memory control circuit.

Claims (1)

[Claims] 1. A device comprising a predetermined amount of digital data 2
A digital signal obtained by encoding the first error correction code and the second error correction code in each of the series of digital data located in the first direction and the second direction which are different from each other in the dimensional array has a predetermined speed. An error correction code decoding device for decoding the digital signal recorded on a recording medium running on the medium and reproduced from the recording medium, comprising: a second decoding device for decoding the second error correction code; A decoding output of the second decoding device is supplied, the memory for converting the time series of the decoding output into the series of the first error correction code, and the decoding of the first error correction code to which the output of the memory is supplied. A first decoding device for performing the above, a flag memory for storing accompanying information of the data written in the memory, and a normal reproduction for reproducing the recording medium by traveling at the predetermined speed. To write the decoded output of the second decoding device to the memory, write the error flag of the decoded output to the flag memory as the additional information, and run the recording medium at a speed higher than the predetermined speed. At the time of high-speed reproduction for reproduction, only data having no error in the decoded output of the second decoding device is written to the memory, and a first flag indicating that the data has no error is added to the accompanying information. As such, when writing to the flag memory and reading the data having no error from the memory, the second flag indicating that the data has been read is written to the flag memory instead of the first flag. An error correction code decoding device, comprising: a memory control unit for controlling.