JPS6338897B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal processing device suitable for use when, for example, an audio signal is converted into PCM and recorded and reproduced by a video tape recorder (hereinafter referred to as VTR).

VTRs are originally configured to record or play back video signals that include a synchronization signal and a blanking period.
cannot be used without making changes to its configuration. In other words, it is necessary to compress the time axis of the PCM signal by a certain amount and to add a synchronization signal so that a data missing period corresponding to a blanking period is formed in the PCM signal.
A PCM signal reproduced from a VTR can be demodulated after its time axis is expanded and the synchronization signal is removed. Conversion (compression or expansion) of the time axis can be performed by making the write frequency and read frequency of the memory device different.

Another problem with using a VTR as a transmission medium is the occurrence of errors due to dropouts. To solve this problem, for example, an error-correctable block code recorded on multiple tracks of a magnetic tape is applied to a single track. It is conceivable to rearrange the code arrangement (interleave or deinterleave) so that the code sequence is correct.

The purpose of the present invention is to perform time axis conversion of PCM signals and
The objective is to rearrange signals using a common memory device. Further, the present invention is as described above.
It is suitable for application to an apparatus that records or reproduces PCM signals using a VTR.

An embodiment of the present invention applied to a PCM signal recording and reproducing apparatus using a VTR will be described below.In this embodiment, an error correction code is exclusively used in a multi-track fixed head system. It uses ORC (Optimal Rectangular Code). This means that no matter how long a burst error occurs, it can be completely corrected if it only occurs on one track, and burst errors on up to two tracks can be corrected if the track number where the error occurred can be detected by another method. It is something.

FIG. 1 is a block diagram of the entire recording and reproducing apparatus. In FIG. 1, 1 is an input terminal for an audio signal, and 2 is a sampling and holding circuit. The sampling output of the sampling hold circuit 2 is converted by the AD converter 3 into parallel 16-bit information bits α ₁ to α ₁₆ as shown in FIG. However, in FIG. 2, α is omitted and only its suffix number is shown.
Information bits from this AD converter 3 are applied to a CRC encoder 4, an ORC encoder 5, and a parallel-to-serial converter 6.

CRC encoder 4 has 4 of α ₁₇ , α ₁₈ , α ₁₉ and α ₂₀
It forms a CRC code consisting of bits. CRC (Cyclic Redundancy Check) is encoded by dividing a code expressed by a polynomial whose coefficients are information bits by a generator polynomial, and adding the remainder to the information bits as a CRC code.In decoding, the CRC code is If the received code containing the generated polynomial is divided by the generator polynomial and the remainder is 0, it is determined that no error has occurred, and if some remainder occurs, it can be detected that an error has occurred. Note that in this specification, calculations are based on (mod2) calculations. That is, (addition) (multiplication) 0+0=0 0・0=0 1+0=1 1・0=0 0+1=1 0・1=0 1+1=0 1・1=1 CRC encoder 4 is a shift register and mod2 adder However, since this example is parallel processing, for example, the generator polynomial G(x) can be realized as (x ⁴ +x ² +
1), the CRC codes α ₁₇ to α ₂₀ can be obtained by performing the following calculation using an adder.

α ₁₇ = α ₂ + α ₆ + α ₈ + α ₁₂ + α ₁₄ α ₁₈ = α ₁ + α ₅ + α ₇ + α ₁₁ + α ₁₃ α ₁₉ = α ₂ + α ₄ + α ₈ + α ₁₀ + α ₁₄ + α ₁₆ α ₂₀ = α ₁ + α ₃ + α ₇ +α ₉ +α ₁₃ +α ₁₅ and the ORC encoder 5 converts the information bits α ₁ to
One block of ORC in a ( ₆ ×5) matrix format as shown in FIG. 2 is formed from a total of 20 bits of α16 and CRC codes _α17 to _α20 . ORC
are generally recorded in parallel by a fixed head so that each row _Z0 to _Z5 forms six tracks. Here, B ₀ = (A, B, C, D, E)' B ₁ = (α ₄ , α ₈ , α ₁₂ , α ₁₆ , α ₂₀ )′ B ₂ = (α ₃ , α ₇ , α ₁₁ , α ₁₅ , α ₁₉ )′ B ₃ = (α ₂ , α ₆ , α ₁₀ , α ₁₄ , α ₁₈ )′ B ₄ = (α ₁ , α ₅ , α ₉ , α ₁₃ , α ₁₇ )′. However, Datsushiyu means a transposed matrix.
Column vectors B ₁ -B ₄ are formed from information bits, whereas column vector B ₀ is defined by B ₀ =TB ₁ +T ² B ₂ +T ³ B ₃ +T ⁴ B ₄ . Here T is is a matrix defined by and T ² , T ³
By determining and T ⁴ in advance, each bit of the column vector B ₀ can be determined in parallel by the following calculation.

A = α ₅ + α ₁₀ + α ₁₅ + α ₁₇ + α ₂₀ B = α ₄ + α ₉ + α ₁₄ + α ₁₉ C = α ₃ + α ₅ + α ₈ + α ₁₀ + α ₁₃ + α ₁₅ + α ₁₇ + α ₁₈ + α ₂₀ D = α ₂ + α ₇ + α ₉ +α ₁₂ +α ₁₄ +α ₁₇ +α ₁₉ E=α ₁ +α ₆ +α ₁₁ +α ₁₃ +α ₁₆ +α ₁₈ Also, the 4 bits (a to e) in the 6th row _Z5 are even numbers for the bits of column vectors B ₀ to _{B 4,} respectively. It is a parity bit. In other words, a = a + b + d + d + EB = α 4 + _{α 4} + α ₄ + α ₄ + α ₊ α ₁₅ + α _{20 C = α 20} C = α ₃ + α ₇ + α ₁₅ + α ₁₅ + α ₁₅ + α ₁₅ + _α15 + α15 + α ₂ + α14 + α ₁₄ + α ₁₄ + Α ₉ + α ₁₃ +α ₁₇ .

The parallel-to-serial converter 6 receives the information bits (α ₁ to α ₁₆ ) from the AD converter 3 , the CRC code (α ₁₇ to α ₂₀ ) from the CRC encoder 4 , and the ORC encoder 5 .
By supplying 10 bits (A to E and a to e), Z ₀ , Z ₁ , Z ₂ . . . as shown in FIG.
...A 30-bit code (hereinafter referred to as 1 word) serialized in the order of _Z5 is obtained. The output of the parallel-to-serial converter 6 is supplied to a memory device 7, which will be described later. The memory device 7 functions as an interleaving circuit that rearranges the array of the serial codes from the parallel-serial converter 6, and also functions as a time axis compression circuit that compresses the time axis of this serial code to form a data missing period. It is. This data missing period is approximately equal to the length of the vertical blanking period of the video signal. The output of the memory device 7 is then supplied to a synchronization signal addition circuit 8, to which synchronization signals similar to the horizontal synchronization signal, vertical synchronization signal, and equalization pulse in the video signal are added. In this way, PCM has the same signal format as the video signal.
The signal is supplied to a recording signal input terminal 10i of a rotating two-head type VTR 9. Having the same signal format as the video signal makes it possible to record and play back PCM signals using the VTR9, which normally has the function of recording and playing back video signals, and makes recording and playback of high-quality audio signals more familiar. This is to make it a reality. In the VTR 9, the PCM signal is recorded on the magnetic tape by a pair of rotating magnetic heads via a recording system in the form of inclined tracks each having a length corresponding to one field. The aforementioned memory device 7
This rearranges the array of serial codes, and this rearrangement is completed within one field period at most. In this example, one rearrangement is completed in 35H (H is one horizontal period). One field is 262.5H, and the period during which data can be inserted is approximately 245H, excluding the vertical blanking period. Therefore 1
There will be seven permutations in the field. Furthermore, the length of one word is selected to be 1/6H, and the recording signal waveform is for two words (60H) as shown in Figure 3.
A 3-bit data synchronization signal DS of [110] is added to each bit (110 bits), and data processing is performed using this data synchronization signal DS as a time base, and 180 bits are PCM signals are inserted. FIG. 4A shows a 35H long serial code from the parallel-to-serial converter 6 in units of tracks (rows) _Z0 to _Z5 , and in this 35H period, 210 words _K1 , _K2 ...
K ₂₁₀ , so there are 1260 tracks (=6300 bits) of code. In the memory device 7, the fourth
The PCM signals are recorded _in the _order shown in _FIG . Next, as shown by broken lines in FIG. 4, the second track Z ₁ is selected from each of the words K ₁ to K ₂₁₀ and arranged in word order.
Similarly, the third to sixth tracks Z ₂ to _{Z 5}
A read operation is performed such that the words K ₁ to K ₂₁₀ are selected and arranged in word order. The output of the memory device 7 is a collection of 210 tracks from each word and arranged in order, as shown in FIG. 4B. Of course, the fourth
The time axis of the rearranged PCM signals as shown in FIG. B is compressed.

During playback, the playback signal output terminal 10 of the VTR9
A PCM signal having the same format as the video signal as well as the recording signal waveform is obtained from o, and is supplied to the memory device 12 via the synchronization signal separation circuit 11. Based on the synchronization signal separated by the synchronization signal separation circuit 11, clock pulses for the memory device 12 and other parts of the reproduction system are formed. In the recording system described above, a clock pulse is formed based on the output of a reference oscillator. As will be described later, the memory device 12 has the function of a deinterleave circuit that rearranges the arrangement of PCM signals to the original order, and a time axis expansion circuit that expands the time axis to make a continuous PCM signal without data missing periods. It has both functions, and the write and read operations are opposite to those of the memory device 7. The VTR signal is separated from the playback signal as a clock pulse in such processing.
By using both a clock pulse formed from a synchronization signal having a time axis variation in VTR 9 and a clock pulse having a constant or approximately constant frequency, the influence of time axis variations such as jitter in the VTR 9 can be eliminated. This memory device 12
If the readout output is shown for 35H, it will be the same as that shown in FIG. 4A. Then, it is converted into a parallel code by a serial/parallel converter 13, and then provided to an ORC decoder 14, which is shown surrounded by a broken line in FIG.

To explain ORC decoding, from the above encoding, the relationship Z ₀ +Z ₁ +Z ₂ +Z ₃ +Z ₄ +Z ₅ =0 Z ₀ ′+TZ ₁ ′+T ² Z ₂ ′+T ³ Z ₃ ′ +T ⁴ Z ₄ ′=0 is obtained. To establish. Now, the error pattern is defined as follows.

Therefore, the error e _i (i=
0, 1, 2, 3, 4, 5) is expressed as e _i = (e _i0 , e _i1 , e _i2 , e _i3 , e _i4 ), and when this error is included, Zi＾ = Zi + e _i represent. Any symptoms that appear when a sequence containing this error is received are called syndromes.
Syndromes S ₁ and S ₂ are defined by the following formulas.

S ₁ =Z ₀ ^'+Z ₁ ^'+Z ₂ ^'+Z ₃ ^'+Z ₄
＾′+Z ₅ ＾′ =(s ₁₀ , s ₁₁ , s ₁₂ , s ₁₃ , s ₁₄ )′ S ₂ =Z ₀ ＾′+TZ ₁ ＾′+T ² Z ₂ ＾′+T ³ ＾ ₃ ＾′
+T ⁴
Z ₄ ^' =B ₀ ^+TB ₁ ^+T ² B ₂ ^+T ³ B ₃ ^+T ⁴ B ₄
^ = (s ₂₀ , s ₂₁ , s ₂₂ , s ₂₃ , s ₂₄ )' Therefore, if no error occurs, both S ₁ and S ₂ will be 0. Therefore, if an error occurs, S ₁ = ₅ 〓 ⁱ⁼⁰ Zi′+ ₅ 〓 ⁱ⁼⁰ e _i ′= ₅ 〓 ⁱ⁼⁰ e _i ′ S ₂ = ₄ 〓 ⁱ⁼⁰ T ⁱ e _i ′ Become. Syndrome S ₁ is obtained by adding all the columns of received (reproduced) codes.

That is, S ₁₀ = A + B + C + D + E + a S ₁₁ = α ₄ + α ₈ + α ₁₂ + α ₁₆ + α ₂₀ + b S ₁₂ = α ₃ + α ₇ + α ₁₁ + α ₁₅ + α ₁₉ + c S ₁₃ = α ₂ + α ₆ + α ₁₀ + α ₁₄ + α ₁₈ + d S ₁₄ = α ₁ + α ₅ + α ₉ + α ₁₃ + α ₁₇ + e In addition, syndrome S ₂ occurs even during encoding.
It can be found as follows in the same way as B ₀ was found.

s ₂₀ = A + α ₅ + α ₁₀ + α ₁₅ + α ₁₇ + α ₂₀ s ₂₁ = B + α ₄ + α ₉ + α ₁₄ + α ₁₉ s ₂₂ = C + α ₃ + α ₅ + α ₈ + α ₁₀ + α ₁₃ + α ₁₅ + α ₁₇ + α ₁₈ + α _{20 s23} =D+ _α2 +α ₇ +α ₉ +α ₁₂ +α ₁₄ +α ₁₇ +α ₁₉ s ₂₄ = E + α ₁ + α ₆ + α ₁₁ + α ₁₃ + α ₁₆ + α ₁₈ Syndrome S ₂ can also be formed with feedback shift registers, but in order to perform parallel processing I'm looking for it. When a burst error that falls within one track is to be corrected and it is assumed that there is a burst error in the i-th track, the following relationship holds true.

S ₁ = e _i ′ S ₂ = T ⁱ e _i ′ (0≦i≦4) 0 (i=5) Here, (S ₂ =0) means that the sixth row Z ₅
Since the parity bit is incorrect, the received sequence is used as output data. Therefore, by forming S ₃ = T ^-i S ₂ and finding i (error track) such as (S ₁ = S ₃ ) and performing the operation Zi′=Zi＾′+S ₁ , the burst error e _i can be corrected. be done.

Corresponding to the above explanation, the ORC decoder 14 has
S ₁ forming circuit 15 and S ₂ and S ₃ forming circuit 16 (S ₁ =
A coincidence detection circuit 17 for detecting S ₃ ) and an error correction circuit 18 are provided. The error correction circuit 18 receives B ₀ (A
20 information bits (α ₁ to α ₂₀ ) excluding Z 5 (a to E) and Z ₅ (a to e) are provided. The formation of S ₃ can be processed in parallel by calculating T ^-1 , T ^-2 , T ^-3 , T ^-4 and T ^-5 in advance and performing the following addition.

Then, the error-corrected information bits α ₁ to _{α 20} are
The signal is supplied to the CRC decoder 19. The CRC decoder 19 outputs information bits _α1 to _α16 and CRC codes _α17 to _α20.
The polynomial with coefficients is divided by the generator polynomial, and if the 4-bit remainder is (P ₁ ~ P ₄ ), then
Each bit can be obtained by the following calculation in the same way as encoding.

P ₁ = α ₂ + α ₆ + α ₈ + α ₁₂ + α ₁₄ + α ₁₇ P ₂ = α ₁ + α ₅ + α ₇ + α ₁₁ + α ₁₃ + α ₁₈ P ₃ = α ₂ + α ₄ + α ₈ + α ₁₀ + α ₁₄ + α ₁₆ + α ₁₉ P ₄ = α ₁ + α ₃ + α ₇ + α ₉ + α ₁₃ + α ₁₅ + α ₂₀ 4-bit output P ₁ of this CRC decoder 19
If _P4 is all "0", it is determined that no error has occurred, and if even one bit is "1", it is detected that an error has occurred. These 4-bit outputs P ₁ to _{P 4} are supplied to the OR gate 20.
The OR gate 20 is also supplied with a mismatch detection output from the match detection circuit 17 which becomes "1" when there is no case where S ₁ =S ₃ , that is, when correction is impossible by ORC. An interpolation circuit 21 is controlled by the output of the OR gate 20. 16-bit information bits α ₁ to _{α 16} are supplied in parallel to this interpolation circuit 21 , its output is supplied to a DA converter 22 , and the DA conversion output is guided to an output terminal 24 via a low-pass filter 23 . .

The interpolation circuit 21 outputs correct information bits as is, and outputs the average value of the correct information bits before and after the erroneous information bits. When it does, it works to hold the previous correct information bit. Of course, in reality
Even with ORC, the probability of being uncorrectable is extremely low.

According to such a digital signal processing device, error correction codes configured to correct burst errors in the row direction when arranged in a matrix can be serialized and recorded on a single track. In this case, the error correction code is not only serialized as Z ₀ Z ₁ Z _{2 .} . . Z ₅ for each word as shown in FIG. 4A, but also serialized as shown in FIG. So Z ₀ ...Z ₀ , Z ₁ ...Z ₁ ,
Since the corresponding tracks (rows) of a plurality of words are rearranged so that they are continuous, the influence of dropouts that are inevitable when using magnetic media can be significantly reduced. In other words, burst errors due to dropouts that do not exceed the length of 210 tracks (35/6H) are
1 in each word when configured as an ORC
This results in a burst error that falls within the track and can be corrected. If the data is serialized as shown in FIG. 4A and no interleaving is performed, for example, an error in two bits spanning Z ₀ and Z ₁ will result in an error in two tracks. However, ORC also handles errors in 2 tracks.
If the track number in which the error occurs can be detected by another method, it can be corrected, but considering the complexity of the configuration, it is desirable that the burst error be contained within one track. Even if the configuration is capable of correcting errors on two tracks, only burst errors on two tracks at maximum can be corrected. However, if the rearrangement is completed within one field as in the above embodiment, it is convenient for editing recorded signals.

Next, the above-mentioned memory devices 7 and 12, which are the gist of the present invention, will be explained. Both can be a common memory device. As mentioned above, since interleaving is completed in 35H, the memory capacity C _M required for interleaving is C _M = 3 x 60 x 35 = 6300 bits = 6.3 K bits. Also, considering interleaving and time axis compression, a minimum memory capacity of _3CM is required, and considering time axis fluctuations such as jitter and drift during playback, a memory capacity of _4CM is selected. That is, as shown in FIG. 5, four RAMs each having a memory capacity of C _M ,
, , are used to control such that when one of them is in a write cycle, the other is in a read cycle, and the frequency of the read clock pulse is made higher than the frequency of the write clock pulse to achieve a predetermined data missing period. At the same time, the writing address and the reading address are controlled to perform interleaving. FIG. 6 shows the operation of such a RAM. Writing is performed sequentially from the beginning of the RAM, and reading is performed during the vertical blanking period including the vertical synchronization signal VD and the 17.5H data missing period that is the period before and after the vertical blanking period. When the RAM is in a write cycle, the RAM is in a read cycle. Note that in order to perform deinterleaving and time axis expansion in the reproduction system, the writing and reading operations in FIG. 6 may be reversed.

FIG. 7 shows an example of the memory device 7. RAM
~ selects the data input terminal, data output terminal, terminal R/W to which the write/read control signal is applied, terminal ADRS and RAM to which the address signal is applied in the 8K static RAM respectively.
It has a terminal CS to which a RAM selection signal is applied. Address selectors 31 to 34 are provided for each of these RAMs, and either a parallel 13-bit write address signal or a read address signal is selected by a write/read control signal from a write/read control circuit 35. and is supplied to the corresponding RAM terminal ADRS. Since one word of the write address signal is 30 bits, it is combined with the parallel 5-bit bit address signal and the parallel 8-bit word address signal since there are 210 words ( _K1 to _K210 ) to complete interleaving. It is something. 36W is a write bit address counter that generates this bit address signal, and 37W is a write word address counter that generates a word address signal. 38 is a write clock pulse generation circuit, which forms a word clock pulse and a bit clock pulse of 1/30 of its repetition period from the clock pulse from the clock pulse generation circuit 39, and the bit clock pulse is generated by the write bit address counter. 3
6W and a word clock pulse is provided to the write word address counter 37W. That is, as shown in FIG. 8, the write bit address counter 36W is supplied with bit clock pulses.
The write word address counter 37W is configured as a 30-decimal counter, and the write word address counter 37W is supplied with a word clock pulse having a frequency of 1/30 of the bit clock pulse.
It is configured as a 210-decimal counter. The carry of the write word address counter 37W is supplied to the RAM selector 40, and the carry signal from the RAM selector 40 is
A RAM selection signal is applied to the terminal CS of the RAM.
Therefore, when 210 words of a PCM signal of 1 word and 30 bits are written to a RAM, for example, a carry occurs from the write word address counter 37W.
This carry causes the PCM signal to be written to the RAM from now on. At the same time, the carry from the write word address counter 37W is supplied to the write/read control circuit 35, and the write/read control signal from this is applied to the terminal R/W of the RAM, thereby defining the write cycle of the RAM.

The read address signal is a parallel 13-bit signal consisting of a parallel 5-bit bit address signal from the read bit address counter 36R and a parallel 8-bit word address signal from the read word address counter 37R. ~34 is given. In order to compress the time axis during reading, the period of the read bit clock pulse is made slightly shorter than the period of the write bit clock pulse, and in order to perform interleaving, the read bit address counter 36R and the read word address Counter 37R is controlled by interleave control circuit 41.

Referring to FIG. 9, the read bit address counter 36R is composed of a 30-decimal counter supplied with bit clock pulses. Bit clock pulses are also provided to a quinary counter 42. The carry is supplied to the clock input terminal CP of the read word address counter 37R and the load terminal LD of the read bit address counter 36R. Read word address counter 37
R is a 210-decimal counter whose carry is applied to the clock terminal CP of the buffer 43 and one input terminal of the AND gate 44. The buffer 43 takes in the 5-bit output of the full adder 45 in parallel when a carry occurs in the read word address counter 37R, and the parallel 5-bit output of this buffer 43 is sent to the preset terminal PS of the read bit address counter 36R. is given and is preset when the above carry occurs. The full adder 45 is supplied with the BCD code corresponding to 5 as one input, and the output of the buffer 43 is supplied as the other input. This buffer 43 is 35H where the interleave is completed.
Cleared every period. Furthermore,
The carry signal of the write bit address counter 36R is supplied to the other input terminal of the AND gate 44, and the output of the AND gate 44 is supplied to the RAM selector 4.
0.

To explain the interleave operation in such a configuration with reference to FIG.
Assume that 210 words of PCM signals shown in FIG. A have been written, and that a read operation is to be performed from the RAM. Initially, the contents of buffer 43 are 0 and the read word address signal specifies _K1 . Then, when the read bit address sequentially specifies five addresses by the bit clock pulse and the reading of the first track _Z0 (5 bits) of word _K1 is completed, the word address is incremented.
The next word _K2 is specified and read from the buffer 43 to the load terminal of the bit address counter 36R.
LD is again loaded with 0 and the first track Z ₀ of word K ₂ is read out. Thereafter, when reading of the first track _Z0 up to word K ₂₁₀ is completed in the same manner, a carry is generated from the read word address counter 37R. By this carry, the output of the full adder 45 is taken into the buffer 43, and the content of the buffer 43 corresponds to 5, which is stored in the read bit address counter 36R.
Preset to .

Therefore, when word _K1 is designated, what is read out is the address that is the address previously read out plus 5, and the next track _Z1 after word _K1 is read out. Similarly, words K ₂ , K ₃ ...
Each next track Z ₁ of K ₂₁₀ is read and a carry is generated from the write word address counter 37R. As a result, the contents of the buffer 43 become (5+5=10) and are preset in the read bit address counter 36R. Therefore, the third track Z ₂ of each word is read out in sequence, and when the reading of track Z ₂ of word K ₂₁₀ is completed, the content of the buffer 43 becomes (5+10=15). As a result, the fourth track _Z3 of each word is read out in sequence. Thereafter, in the same manner, the content of the buffer 43 becomes (5+15=20) and the fifth track _Z4 of each word is sequentially read out, and the content of the buffer 43 becomes (5+20=25) and the fifth track Z4 of each word is sequentially read out. The th track _Z5 is sequentially read out. Since a carry is generated from the read bit address counter 36R every time this sixth track _Z5 is read for each word, the output of the AND gate 44 goes high when the readout of track _Z5 of word _K210 is completed. level, which is applied to the RAM selector 40, so that the next read is performed with respect to the RAM. At the same time, the buffer 43 is cleared. By controlling the address signal during reading as described above, interleaving as shown in FIG. 4 can be performed.

Note that the playback type memory device 12 can also have basically the same configuration as the above-described memory device 7.

According to the present invention described above, time axis conversion (compression or decompression) and rearrangement (interleaving or deinterleaving) can be performed at the same time in a memory device, and both can be performed in separate memory devices as in the past. The circuit configuration can be greatly simplified compared to the case where it is carried out in this manner.

Note that in the above embodiment, ORC and CRC codes are used together to increase the probability of error detection; however, ORC
Of course, similar benefits can be obtained by applying the present invention to cases where only

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
Figures 3, 4, 5 and 6 are diagrams used to explain one embodiment of the present invention, Figure 7 is a block diagram of the main part thereof, and Figures 8 and 9 are FIG. 7 is a block diagram of a portion of FIG. 7; 3 is AD converter, 4 is CRC encoder, 5 is
ORC encoder, 7 and 12 are memory devices,
9 is a VTR, 14 is an ORC decoder, 19 is a CRC decoder, 21 is an interpolation circuit, and 22 is a DA converter.

Claims (1)

[Claims] 1 A PCM signal consisting of a plurality of codes input in a first arrangement order is written to a memory device in response to a first clock pulse, and the plurality of codes are transferred from the memory device to the first clock pulse. in response to a second clock pulse having a frequency different from that of the second clock pulse, the data is read out in an arrangement order different from that in writing and at a different speed; 1. A digital signal processing device comprising a plurality of codes, and outputting a time-axis compressed or expanded PCM signal.