JPH0142069B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory control method, in which a modulated digital signal obtained by processing an analog signal into a digital signal is divided into certain periods, and the signals are arranged in a different order from the original order. A plurality of signals are combined into one block together with a correction signal, and when reproducing the plurality of block signals recorded on a recording medium in block units, the divided modulated digital signals in the block signal are used as a correction signal. To provide a memory control method which allows a memory for restoring the original order to be restored to its original order using a simple configuration control system with a small storage capacity and minimizing a decrease in jitter absorption. purpose.

Conventionally, a modulated digital signal (modulated pulse) obtained by digital signal processing of an analog signal such as a stereo audio signal using a discontinuous level modulation method such as pulse code modulation (PCM) or differential modulation is a composite synchronous signal. Since the occupied frequency band is wide, the digital signals that are present along with the magnetic tape are recorded on a track formed at an angle with respect to the longitudinal direction of the magnetic tape using a magnetic recording/reproducing device (hereinafter referred to as VTR). After decrypting this
It is known that analog signals such as stereo audio signals can be recorded and played back with high quality on a VTR by performing DA conversion and playback.

Figure 1 shows a digital signal recorded using a VTR.
FIG. 2 is a block system diagram showing an example of a reproducing device. In the figure, the analog signal entering input terminal 1 is passed through low-pass filter 2 to prevent aliasing noise.
After the high frequency components are cut off, the sample and hold circuit 3 samples the signal at appropriate time intervals, and the signal is further supplied to the AD converter 4 and converted into the modulated digital signal described above. This modulated digital signal is applied to the memory 5, where writing and reading of data is controlled by pulses from a control circuit 6. The memory 5 divides the modulated digital signal into sections for each period, and rearranges the divided section signals (also referred to as data) in an order different from the original order, together with correction signals to be described later. The signal is taken out and supplied to the adder 8, where it is added to the composite synchronization signal from the TV sync pattern generator 7 to form a digital signal. This digital signal is obtained by replacing the video signal period signal in the composite video signal with the above data, and is recorded on the magnetic tape of the VTR 9.

The data portion of the digital signal reproduced from the VTR 9 is extracted and waveform-shaped in the data acquisition circuit 10, converted into a binary code digital signal, and then applied to the memory 11, where the data is processed by pulses from the control circuit 12. Writing and reading are performed. The data read from the memory 11 is rearranged in the same order as the input data of the memory 5, and this data is
The signal is supplied to the DA converter 13 and converted into the original analog signal. This analog signal passes through a low-pass filter 14 and is output from an output terminal 15. In addition,
Between the memory 5 and the adder circuit 8 (not shown) there is a code generation circuit that generates a data error check code, for example, a CRC code (cyclic code), and between the data acquisition circuit 10 and the memory 11 there is a code generation circuit that generates a data error check code, for example, a CRC code (cyclic code). There is an error detection circuit for detecting check codes.

In the above recording and reproducing apparatus, the output data of the AD converter 4 is not kept as is, but is rearranged in the memory 5, time-division multiplexed with the correction signal, and further synthesized with the composite synchronization signal. The sorting method is generally called interleaving or delayed placement. Second
Figure A shows a case where the output data of the AD converter 4 and the correction signal from the correction signal generator (not shown) (provided on the input side or output side of the memory 5) are combined into a composite synchronization signal in order. With a waveform of n ₀
means the n _0th sampled and AD converted data, and n ₁ , n ₂ , ..., n ₁₁ similarly means the data sampled at predetermined intervals from the n _0th to the 2nd, 3rd, ..., 12th data. P ₀ , P ₁ , P ₂ , and P ₃ mean correction signals generated at each predetermined period. Since the above-mentioned recording and reproducing apparatus uses the above-mentioned interleaving method, the digital signal waveform as shown in FIG. Recorded by VTR9. In addition, in FIGS. 2A and 2B, illustration of the CRC code after the correction signal is omitted. Furthermore, in Figure B, three pieces of data and one correction signal constitute one block and are inserted in each block between adjacent horizontal synchronizing signals. For example, the left side
In the 1H period, there is data n ₀ , data n _-2 from two sampling periods before this, and data n _-4 from four sampling periods before n ₀ , as shown by the following formula.
Of the correction signals Pi generated by the addition of mod.2, P _-3 are time-division multiplexed.

Pi=n _3i n _3i+1 n _3i+2 (1) Also, each data is generally composed of ten or more bits, but due to interleaving, continuous data, for example n ₀ and n ₁ , n ₁ and n In the case of Figure 2B, there is a difference of about 1H in the location where composite synchronization signals such as ₂ , n ₂ and P ₀ are combined, so this kind of interleaving is generally called interleaving with an interleaving length of 1H. I'm here.

The reason for interleaving data in this way is that even if a dropout occurs and some data is missing, the error data is not continuous and is dispersed in small units, making it easier to correct the error data and eliminating dropout. This is because the deterioration of the reproduced signal caused by this can be reduced to the extent that it does not pose a problem in practice. Furthermore, due to the presence of the correction signal Pi, it is possible to restore - data among the data of the generation elements of Pi, as will be described later. In reality, since there are many burst-like dropouts of several H in the reproduced signal of a VTR, it is necessary to ensure an interleave length of about 10-odd H.

However, in the above recording/reproducing device,
Since the reproduced digital signal has time-axis fluctuations due to VTR jitter, wow, and flutter, the memory 11 performs an operation to restore the interleaved data to its original order (hereinafter referred to as "deinterleaving" in this specification). In addition to this, it was necessary to perform a jitter absorption operation, which required a storage capacity section for deinterleaving and a storage capacity section for jitter absorption. Then, as is well known, the error check code is checked by an error detection circuit (not shown), and the data of any one of the generation elements (data) n _3i , n _3i+1 , n _3i+2 of the correction signal Pi, e.g. n _3i is VTR9
If an error occurs due to dropout, the other three n _3i+1 , n _3i+2 , and Pi are correct in the memory 11, so correct and restore n _3i from these by adding mod.2 of the following equation. was.

n _3i = n _3i+1 n _3i+2 Pi (2) Therefore, for example, in Figure 2B, data n ₀ ,
When the three data n _-2 and n _-4 are incorrect, By adding mod.2 of , the data of n ₀ , n _-2 , and n _-4 will be restored, respectively.

However, conventional memory control methods use random access memories (RAM) in memories 5 and 11 that can be freely written and read under the control of external pulses, and the total storage capacity of RAM is generally 2 ^N. Since it is a word (N is a positive integer), in order to simplify the configuration of the memory control system, the storage capacity is divided into ^2x equal parts, and the capacity value (length) of each equal division is 2 ^Nx (These are also mutually equal) Addresses were fixed to the portions, and a number of data h ₀ to h _y (y≦2 ^x ) to be time-division multiplexed within 1H was allocated.
Furthermore, in the conventional memory control system, data error correction using the above-mentioned correction signal Pi was performed after jitter absorption of the playback data and the playback correction signal, respectively. A capacitive portion was also required for the correction signal.

For example, n _3i , n _3i+1 , n 3i _{+ 2} at times t _3i , t 3i+1 , t _3i+2 from the jitter absorption storage capacity part of the memory 11
Suppose that each piece of data is read out sequentially. Here, the intervals between times t _3i , t _3i+1 , and t _3i+2 are between the AD converter 4 and
This is a time interval determined by the sampling period for the DA converter 13, and is extremely long compared to the time (access time) required to write or read data to the memory 11.
A large number of data can be read from the memory 11 at each time interval.

Therefore, the next time t _3j , t _3j+1 , t _3j+2 (j=i+1)
The data to be read n _3j , n _3j+1 , n _3j+2 are
It is possible to read data between time t _3i → t _3j , and if there is any erroneous data among these three data, the error correction signal P _j is further read out from the memory 11, and (2) Erroneous data can be corrected using formulas.

This is generally called lookahead, and if among these lookahead data n _3j , n _3j+1 , n _3j+2 , for example n _3j+1 is incorrect, then (1) to (3 ), n _3j+1 is corrected and restored using n _3j , n _3j+2 and the correction signal Pj by addition modulo 2 (mod.2 addition), and this restored data
n _3j+1 is stored in a separate register. Then, when reading the data n _3j , n _{3j+1 , n 3j+2 from the jitter absorption storage capacity portion of the memory 11 at times t 3j , t 3j+1 , t 3j +2 t} , the data n _3j and n _3j+2 uses the output from the memory 11 as is, and n _3j+1 uses the output of the above register to obtain error-corrected data, that is, a modulated digital signal (usually a PCM signal). That's why. Therefore,
Regarding data n _3i , n _3i+1 , n _3i+2 , previous time t _3h ,
At t _3h+1 and t _3h+2 (where h=i−1), the corrected data was stored in a separate register. When error correction is performed using the above method, a jitter absorbing memory is also required for the correction signal Pi.

FIG. 3 is a diagram schematically showing how to use the storage capacity of the memory 11 controlled as described above, and the total area indicates the total storage capacity of the memory 11. As mentioned above, the total storage capacity includes data n _3i , n _3i+1 ,
It is equally divided into four (=2 ² ) parts for writing and reading n _3i+2 and the correction signal Pi, and the capacitance values (lengths) of these divided storage capacity parts are equal to each other. Furthermore, in FIG. 3, the double-framed area indicates the jitter absorption storage capacity area.

The memory 11 performs deinterleaving, but the delay time required for data n _3i , n _3i+1 , n _3i+2 , that is, the storage capacity value is different, so in the above conventional method, the white bar shape in FIG. This area is used for data deinterleaving, and as shown by diagonal lines in the figure, there is a large amount of unused storage capacity, which is uneconomical. Moreover, as the interleave length becomes longer, the unused storage capacity also increases. Furthermore, as mentioned above, since the correction signal pi also requires a storage capacity section for absorbing jitter, a relatively large capacity memory is required as the memory 11. Especially when the number of types of correction signals increases, the memory capacity increases. This has the disadvantage that a predetermined amount of jitter absorption cannot be obtained unless the capacity is increased.

The present invention eliminates the above-mentioned drawbacks and makes effective use of storage capacity.
One embodiment will be described with reference to the drawings from FIG. 4 onwards.

FIG. 4 schematically shows an example of the relationship between the divided state of the memory storage capacity controlled by the method of the present invention and the data written to or read from the memory. In this embodiment, for convenience of explanation, the total storage capacity of the memory is assumed to be 32 (=2 ⁵ ) words, the number m of data that is allowed to exist within 1H period is 3, and one block is composed of data and correction signals. The number of elements k is 4, the deinterleave length D is 1H,
Further, the memory is divided into four storage capacity parts 16, 17, 18, and 19 with storage capacity values (length) of "11", "10", "9", and "2" as shown in FIG.
The jitter absorbing storage capacity portion of length α shown by the double frame is this divided storage capacity portion 16, 17, 18, 19.
It is assumed that "7" are equally provided in each of the numbers.

The present invention relates to a digital signal reproducing system in which a correction signal constitutes a block together with data.
The storage capacity of a memory such as a RAM that simultaneously performs deinterleaving, error correction, and jitter absorption of reproduced data is not divided equally into 2 ⁿ capacity values as in the past, but is divided into multiple arbitrary lengths as described above. The write address and the read addresses for error correction and jitter absorption are circulated among the plurality of divided storage capacity parts so that the following equation is satisfied.
As shown in the figure, the above-mentioned memory can be controlled with the minimum required storage capacity and with as little reduction in jitter absorption as possible using a memory control system having a simple configuration similar to the conventional one. In other words, when i=0 to (m-1), the write address A _wi is A _wi = A+ _i 〓 ^j=0 (k-1-j)D +j+(i+1)α (4) i=m to (k-1) ), then A _wi =A+ _i 〓 ^j=0 (k-1-j)D+i+mα (5). Also read address for error correction
A _R ′ _i is when i=0 to (m-1) A _R ′ _i =A+ _i 〓 ^j=0 (k-1-j)D+i +(i+1)α-(k-1-i)D ( 6) When i=m~(k-1), set A _R ′ _i =A+ _i 〓 ^j=0 (k-1-j)D +i+mα-(k-1-i)D. The read address A _Ri of the data that is finally read after absorbing the jitter is A _Ri = A'+ _i 〓 ^j=0 (k-1-j) D+i + (i+1) α-{(k-1-i) D+α/2} (where α/2 is a positive integer) (8). In equations (4) to (7), A is the analog conversion value of the output of the ^2N counter 20 when counting clock pulses with jitter as shown in Figure 5, and A' is the analog conversion value of the output without jitter as shown in Figure 5. This is the analog conversion value of the output of the ^2N- ary counter 22 when counting clock pulses.

Next, the operation of the method of the present invention will be explained in more detail with reference to FIGS. 4 and 5. In FIG.
n _3(i+7) , n _3(i+6)+1 , n _3(i+5+2) and correction signal P _3(i+4)
In addition, data is written in the storage capacity portions other than the shaded portions. Thereafter, in FIG. 5, a clock pulse _w having a frequency equal to, for example, the horizontal scanning frequency and having the same time axis variation (jitter) as the reproduced digital signal is applied to the ^2N counter 20 ^, which is equal to the total storage capacity 2N of the memory 11. The output A of the ^2N-ary counter 20 that counts this is sent to the adder 2.
1, where the addition expressed by equation (4) is performed using a signal from a decoder (not shown).
The output of this adder 21 is applied to the memory 11 via the changeover switch SW, and the divided storage capacity portion 16,
17 and 18, data n _3(i+7) , n _3(i+6)+1 , n _3(i+5)+2 multiplexed within a 1H period as shown in FIG. 4, respectively.
are written sequentially with jitter. Subsequently, the adder 21 performs the addition expressed by equation (5), and the output of the addition is used to write the correction signal P _3(i+4) into the divided storage capacity section 19 with jitter as shown in FIG. It will be done.

Here, during the above writing operation, the output A of the ^2N- ary counter 20 is added to the decoder output (not shown) in the adder 21 according to the equation (6) or (7),
The output is applied to the memory 11 via the changeover switch SW which switches alternately, and the jittery data n _{3 (i+4)} , n _{3 ( i+4)+1} , n _3(i+4)+2 , and P _3(i+4) are read out in sequence. Memory 11 writes data n _3(i+7) , reads data n _3(i+4) , and reads data n _3(i+6)+1
write, read data n _3(i+4)+1 , data
Write n _3(i+5)+2 , read data n _3(i+4)+2 ,
The operation is controlled in the order of writing the correction signal P _3(i+4) and reading P _3(i+4) .

Here, the read data with jitter
Among n _3(i+4) , n _3(i+4)+1 , n _3(i+4)+2 , if n _3(i+4) is incorrect due to dropout, for example, n _3(i+4) =n _3(i+4)+1 n3(i+4) +2P _3(i+4) (9) Data n _3(i+4) is corrected and restored by addition of mod2. Then the corrected data with this jitter
n _3(i+4) is written again to the storage capacity portion 16 at the original address from which it was read. Here, the relationship between the data shown in FIG. 4 and the above equation (9) will be explained.

In Fig. 4, the correction operation (9) has already been executed for n _3i , n _3i+1 , and n _3i+2 , so the data after 4 blocks are n _3(i+4) , n _{3 (i+4)+1} , n _3(i+4)+2 and correction signal P _3(i+4) will be explained. Data n _3(i+4) is read from the memory 11, and if the data is correct, it is supplied to a register with an adder circuit (not shown) of MOD2 attached to the memory 11. If the data is not correct, it is used to correct the data later. Leave it alone.

Next, data n _{3 (i + 7)} is written to the memory 11, data n _{3 (i + 4) + 1} is read from the memory 11, and if the data is correct, it is supplied to the register with adder circuit of the MOD 2, and the data is If it is incorrect, leave it as is to correct the data later. Next, data n _{3 (i + 6) + 1} is written to the memory 11, data n _{3 (i + 4) + 2} is read from the memory 11, and if the data is correct, it is supplied to the register with adder circuit of MOD 2. , if the data is incorrect, leave it as is to correct the data later.

After that, the data n _3(i+5)+2 is written to the memory 11, the correction signal P _3(i+4) is read from the memory 11, and if the data is correct, it is supplied to the register with an adder circuit of the MOD2. , if the data is incorrect, leave it as is to correct the data later. Then, the correction signal P _{3 (i+5)} is written into the memory 11.

With the control of the memory 11 and the addition operation of MOD2 as described above, the addition circuit can store data, for example.
If only n _3(i+4) is incorrect, in the register with the adder circuit, n _3(i+4)+1 n _3(i+4)+2 P _3(i+4) = n _{3( i+4)} , and the correct data of data n _3(i+4) is corrected and restored. By writing this data again to the address of the memory 11 indicated as n _{3 (i + 4)} in Figure 4, the data read out from within the double frame line in Figure 4 has already been corrected and restored. The data will be

By performing the above operations every 1H period, all the data n _3i , n _3i+1 , n _3i+2 in the jitter absorption storage capacity area shown by the double frame in FIG. The data has been checked for errors and further corrected. Therefore, 2 ^N -ary counter 22
A stable oscillator output with no frequency fluctuation is applied as the readout clock pulse _R , and the output A' of the ^2N -ary counter 22 obtained by counting this is supplied to the adder 23, which satisfies the equation (8) above. The output obtained by the addition operation is sent to memory 1 via the switch SW.
1 as a readout signal,
The jitter-absorbed data and the error-checked or corrected data are retrieved from the jitter-absorbing storage capacity portion of the memory 11.

As described above, according to the method of the present invention, when data necessary for correction and correction signals are read from the memory, they are read out at a speed with jitter, corrected, and the corrected data is read back into the original memory. Since the data is written to the specified location, the jitter-absorbed data read from the jitter-absorbing storage capacity has already had its errors corrected, so that the desired data can be obtained. Therefore, not only the storage capacity portion shown by diagonal lines in FIG. 3 as in the conventional system, but also the storage capacity portion for absorbing jitter of the correction signal shown by diagonal lines in the double frame in the same figure are no longer necessary. When using a memory with the same storage capacity as a conventional memory, the length of the storage capacity part for data jitter absorption can be made larger than before, which reduces the amount of jitter absorbed due to the presence of correction signals. can be suppressed as much as possible, and if the amount of jitter absorption is the same as the conventional one, a memory with a small storage capacity can be used without complicating the control system.

6A and 6B are diagrams showing an example of changing states of addresses in the divided storage capacity portion of the method of the present invention, respectively. is an example of A=A'=1. As mentioned above, in this example, D=1, m=3, k=4, α=7, and A
When = 0, addresses 10, 20,
Data is written to addresses 29 and 30, and when A=1, data is written to addresses 11, 21, 30, and 31 as shown in FIG. Also, the jitter-absorbed data that is finally read is calculated from equation (8).
When A'=0, it is read from addresses 4, 15, and 25 (or addresses 3, 14, and 24) in FIG. 6A, and A'=1
5, 16, 26 (or 4,
15, 25). Addresses are similarly circulated within the memory. As a result, the total storage capacity of the memory can be reduced without making the memory control system much more complicated than in the past.

In addition, in the above example, D=1, m=3, k=
4, α=7, but it goes without saying that the system of the present invention is not limited to such a case. In addition, although only one type of correction signal, Pi, is used, it can be similarly applied to a digital signal in which a different combination of data or other correction signals created using the correction signal as a generation element are simultaneously present. .

As mentioned above, the memory control method according to the present invention is
A total of memories provided in a digital signal reproducing system in which a modulated digital signal and a correction signal are present together with a composite synchronizing signal, which absorbs time axis fluctuations and corrects errors in the modulated digital signal and outputs the result. A storage capacity portion for deinterleaving that is minimum required for each of a plurality of modulated digital signals whose storage capacities are arranged in different orders, a storage capacity portion for absorbing time axis fluctuations that is equal to each other, and a storage capacity for deinterleaving correction signals. Each of the divided storage capacity parts is divided into a plurality of divided storage capacity parts, and the plurality of divided storage capacity parts are circulated within the memory while keeping their capacity value (length) relationship constant. The operation of writing the above-mentioned signals and correction signals in different orders into each of the deinterleaving storage capacity portions and the operation of reading them at a speed synchronized with the above-mentioned time axis fluctuation are sequentially repeated to read out at least the above-mentioned correction signals. After correcting and restoring the erroneous signal among the signals that have been read, using the correction signal, it is written again to the deinterleaving storage capacity part of the above-mentioned divided storage capacity part, and the read signal excluding the above-mentioned correction signal is Among them, since the error-free signal and the signal rewritten after the correction and restoration were controlled to be read out sequentially from each of the time-axis fluctuation absorbing storage capacity sections, the time-axis fluctuation absorbing storage capacity section for the correction signal was Therefore, if a memory with the same storage capacity as the conventional one is used, the length of the storage capacity portion for absorbing data time axis fluctuations can be made larger than that of the conventional one. If the same amount of time axis fluctuation absorption as before is allowed, a memory with a small storage capacity can be used, and the memory control system can be It has many features such as being able to control without complicating the configuration.

[Brief explanation of drawings]

Fig. 1 is a block system diagram showing an example of a digital signal recording and reproducing apparatus using a VTR to which the method of the present invention can be applied, and Fig. 2 A and B are signals in which a modulated digital signal is superimposed on a composite synchronization signal, respectively. 3 is a diagram schematically showing an example of the capacity division state of the memory of the conventional method, FIG. 4 is a diagram schematically showing an example of the capacity division state of the memory of the present invention, and FIG. 5 is a waveform diagram. The figure is a block system diagram showing an embodiment of the main part of the method of the present invention, and FIGS. 6A and 6B each show the state of change of an embodiment of the address in the divided storage capacity portion of the memory controlled by the method of the present invention. FIG. 1... Analog signal input terminal, 5, 11... Memory, 15... Analog signal output terminal, 220, 22
...2 ^N -ary counter, 21, 23...adder.

Claims (1)

[Claims] 1 A modulated digital signal obtained by digital signal processing of an analog signal using a discontinuous level modulation method is divided into predetermined periods, and a plurality of signals in a different order from the original order are combined into the above modulated signal. The above-mentioned block in a digital signal reproduced from a recording medium on which a digital signal is recorded, in which a correction signal generated from a plurality of digital signals is combined into one block signal, and each block signal is made to exist together with a synchronization signal. An operation for correcting and restoring using a reproduction correction signal when the above-mentioned out-of-order signals are erroneously received in a memory to which the signal is input, an operation for absorbing time axis fluctuations of the block signals, and an operation for making the above-mentioned order different. In the memory control method, the total storage capacity of the memory is
A storage capacity portion for deinterleaving that is minimum required for each of the plurality of modulated digital signals in different orders, a storage capacity portion for absorbing time axis fluctuations that is equal to each other, and a storage capacity for deinterleaving the correction signal. Each of the divided storage capacity parts is divided into a plurality of divided storage capacity parts, and the plurality of divided storage capacity parts are circulated within the memory while keeping their capacity value (length) relationship constant. The operation of writing the above-mentioned signals and correction signals in different orders into each of the deinterleaving storage capacity portions and the operation of reading them at a speed synchronized with the above-mentioned time axis fluctuation are sequentially repeated to read out at least the above-mentioned correction signals. After correcting and restoring the erroneous signal among the signals that have been read, using the correction signal, it is written again to the deinterleaving storage capacity part of the above-mentioned divided storage capacity part, and the read signal excluding the above-mentioned correction signal is A memory control method characterized in that the error-free signal and the signal written again after the correction and restoration are controlled to be read out sequentially from each of the storage capacity portions for absorbing time axis fluctuations.