JPS6052507B2 - PCM signal demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to an apparatus that converts a PCM signal obtained by PCM modulating an audio signal into a signal format similar to a television signal, and records and plays the converted signal using a VTR (video tape recorder). The present invention relates to a PCM signal demodulator suitable for use.

If a PCM signal is converted into a signal format similar to a television signal, a PCM modulation device configured as an adapter for a television signal recording and reproducing device such as a VTR) and video desk
By adding a CM demodulator, there is an advantage that the above-mentioned television signal recording and reproducing apparatus can be used as a PCM signal recording and reproducing apparatus. By the way, such PCM
In a signal recording/reproducing device, the recording medium generally does not run stably when the device is started due to the starting characteristics of the motor, etc., so mutating is applied to the demodulated audio signal until the operation of the device becomes stable. It is necessary to prevent unpleasant noises from occurring. Furthermore, when a long dropout or noise occurs, it is necessary to apply muting to prevent abnormal noise from occurring. The present invention takes the above points into consideration and provides a PCM demodulator suitable for use when a PCM modulator and a PCM demodulator are used as an adapter.

The present invention reliably enters the muting operation (hereinafter referred to as "muting on") before any abnormal noise occurs, and also allows the muting operation to be started in a state where the playback signal is unstable, such as when starting up the device. There is a way to avoid repeated turning off. Hereinafter, one embodiment of the present invention will be explained. FIG. 1 shows its PCM.
An encoder is shown, and FIG. 2 shows its PCM decoder. In FIGS. 1 and 2, 1 represents a VTR.

This VTRI supplies a television signal applied from its recording signal input terminal 11 to a pair of rotating magnetic heads via a recording system, and records one field of the television signal on a magnetic tape as an inclined track. Also, VTR
A television signal formed by a signal reproduced from a magnetic tape passing through a reproduction system is taken out from the reproduced signal output terminal 10 of FIG. This VTR1 generally has a wider transmission band than fixed head systems;
A PC whose signal format is the same as that of a TV signal by TRl
This is for recording and reproducing M signals. The PCM encoder and PCM decoder are configured as an adapter for the VTR1, and when this adapter is loaded into the VTR1, a PCM signal recording and reproducing apparatus can be realized. That is, 2L and 2R are terminals to which left and right signals of the stereo audio signal are respectively supplied.

These left and right signals are transmitted through amplifiers 3L and 3R, respectively.
1 low-pass filter 4L and 4R, 1 sampling and holding circuit 5L, and 5RAD converters 6L and 6R for PCM modulation. This oil converter 6L and 6
Since the digital output of R is a parallel code, it is converted into a serial format by a parallel-to-serial converter 7 and supplied to a time-base compression circuit 8. The time axis compression circuit 8 forms a data missing period that roughly corresponds to the vertical blanking period in a television signal. The shaft can be compressed. In this case, the RAM is controlled so that writing and reading are performed asynchronously. The output of the time axis compression circuit 8 is an error detection code such as CR.
The signal is supplied to a CRC encoder 9 for adding a C code.

The output of the CRC encoder 9 is sent to the data synchronization signal addition circuit 1
0. This de. The data synchronization signal adding circuit 10 adds a data synchronization signal Pd to indicate the first timing after the data missing period. Furthermore, a synchronization signal mixing circuit 11 adds synchronization signals corresponding to the vertical synchronization signal and horizontal synchronization signal in the television signal (these synchronization signals are also referred to as vertical synchronization signals and horizontal synchronization signals).
The output of this synchronizing signal mixing circuit 11 is supplied to the recording signal input terminal 11 of the VTR1. 12 indicates a pulse generation circuit for controlling the timing on the write side, 13 indicates a pulse generation circuit for controlling the timing on the read side,
These pulse generating circuits 12 and 13 are supplied with clock pulses from a reference clock oscillator 14.

Then, from the pulse generation circuit 12, a sampling pulse is sent to the sampling hold circuits 5L and 5R, and the AD
Clock pulses for converters 6L and 6R, clock pulses for parallel-to-serial converter 7, and write clock pulses and write control pulses for time base compression circuit 8 are generated. The frequency of the sampling pulse is, for example, 44.1 [KHz], and one sample value is converted into a PCM signal of one word of 26 bits by a clock pulse of 1.4112 [KHz], and the RA of the time axis compression circuit 8 is
Written to M. Further, the pulse generating circuit 13 generates read clock pulses and read control pulses for the time base compression circuit 8, control pulses for the CRC encoder 9, and a composite synchronization signal supplied to the synchronization signal mixing circuit 11. In the time axis compression circuit 8, the write clock pulse is gated by the write control pulse to continuously write data, and after a slight delay after the start of this write operation, the read clock pulse (for example, 1.764 [MHz]) is gated by the read control pulse. ) is gated to perform a read operation, and after a predetermined time, a read control pulse causes the RAM
Time base compression is achieved by stopping the supply of read clock pulses to the clock, thereby pausing the read operation, and restarting the read operation after a predetermined data missing period. 15 is a data synchronization signal generation circuit;
The data synchronization signal P is generated at a timing corresponding to the horizontal period before the horizontal period in which data is inserted at the beginning of the field period.
d.

The data synchronization signal Pd is formed from readout clock pulses for the time base compression circuit 8, and is, for example, ゜"1" and ゜".
0 is repeated alternately. (101010...
·)belongs to. The frequency of the data synchronization signal Pd at this time is (1.764 [MHZ)] 882 [KHZ]
becomes. The data synchronization signal Pd is alternately repeated between ゜゛1d゛ and ゜゜00゛ (110011001100...
), and the frequency of the data synchronization signal Pd in this case is 441 [KHz]. In order to form such a data synchronization signal Pd, a composite synchronization signal for generating a data synchronization signal from the pulse generation circuit 13 at a predetermined timing, and a read clock pulse for forming the data synchronization signal itself are used to generate the data synchronization signal Pd. The signal is supplied to the synchronization signal generation circuit 15. Figure 3 shows the odd field period of the recorded PCM signal (i.e. 263H1, where H is the horizontal period)
, and includes vertical synchronizing signal D1 equalization pulses EQl and EQ2 like the television signal? vertical blanking period and the bile period before it and after it? A total of 18H of data missing period 1RG is provided, and the remaining 24
During the 5H period, three words of the PCM signal and the CRC code are inserted every 1H period specified in the horizontal synchronization signal book.

Then, the data synchronization signal Pd is inserted in the 1H period immediately before the even field data starts after the data missing period 1RG. As shown in an enlarged view in FIG. 4, the signals inserted in this 1H period start after the period 1BG that includes the horizontal synchronizing signal HD with a pulse width equivalent to 8 bits and the subsequent backport with a pulse width equivalent to 8 bits. , each word is 26
Three words of a bit code are inserted, followed by a 16-bit CRC code, and the 1H period is equivalent to 112 bits. This one word consists of 13-bit left and right audio signals arranged in series, and for simplicity, FIG. 4 shows a case in which ゜1゛ and ゜0゛ are alternated. Furthermore, as shown in FIGS. 5A and 5B, the data missing period 1RG causes a deviation of νH in the odd and even fields, similar to the TV signal, and if the data missing period 1RG in the odd field is 18H, then , in an even field it is 171],
The average of both is set to 17.51.
Next, to explain the demodulation of the reproduced PCM signal appearing at the reproduction output terminal 10 of TRl with reference to FIG. 2, the PCM signal having the same waveform as that shown in FIGS. The signal is supplied to the separation circuit 21.

The vertical synchronization signal VD separated by the synchronization signal separation circuit 21 is supplied to a clock pulse generation circuit 33, which will be described later, and data other than the composite synchronization signal is supplied to the data sampling circuit 22 and the tuning circuit 34. The output of the data sampling circuit 22 is supplied to a CRC decoder 23. The CRC decoder 23 determines whether or not an error has occurred in the information bits of 3 words (78 bits in total) inserted during the 1H period. It is written into the RAM of the time axis expansion circuit 24 in the form of being added to the word. The time axis expansion circuit 24 extends the time axis to remove the data missing period 1RG, and obtains continuous data from which time axis fluctuations have been removed. In this case, the discrimination bit is read out as the first bit of each word by controlling the read address, and the discrimination bit is separated by the gate circuit 25. Then, by the serial/parallel converter 26, one word of 26 bits is converted into a 13-bit parallel code corresponding to the left signal and a 13-bit parallel code corresponding to the right signal.
are converted into parallel codes of bits, respectively, by the DA converter 27.
Supplied to L and 27R. The outputs of the DA converters 27L and 27R are sent to average value interpolation circuits 28L and 28R, which replace one erroneous word of data with the average value of the correct one word of data before and after it, and a mutating circuit 29L.
and 29R, and are supplied to amplifiers 31L and 31R via low-pass filters 30L and 30R, respectively. and output terminals 32L and 32R of amplifiers 31L and 31R.
Demodulated left and right audio signals appear. The clock pulse generation circuit 33 to which the above-mentioned regenerated vertical synchronizing signal VD is supplied has a characteristic PL with a very low cutoff frequency.
It has an L circuit configuration, and follows very low frequency drift, called drift, contained in the reproduced signal, for example 14.112 [MHz], which follows time axis fluctuations of 0.3 [Hz] or less.
] generates a clock pulse.

This clock pulse may have a constant frequency, but if the drift is also corrected, the capacity of the RAM constituting the time axis expansion circuit 24 becomes large, and even if the demodulated audio signal contains drift, it is difficult to hear. Since the above does not have a big effect, it is done as described above. In other words, the clock pulses from the clock pulse generation circuit 33 are supplied to the pulse generation circuit 35 that controls the timing on the read side, and are used to generate read clock pulses and read control pulses for the time axis expansion circuit 24, clock pulses for the serial/parallel converter 26, and clock pulses for the DA converter 26. 27L and 27R
A clock pulse is formed. On the other hand, a pulse generation circuit 36 that controls timing on the write side sends a gate pulse to the data sampling circuit 22, a control pulse to the CRC decoder 23, and a time axis expansion circuit 24.
A write clock pulse and a write control pulse are generated for the write clock.

The write-side pulse generation circuit 36 is supplied with clock pulses from the clock pulse generation circuit 33, but the write-side control pulses are used to control relatively high frequency time axis fluctuations called jitter in the reproduced signal. Therefore, the vertical synchronizing signal VD and horizontal synchronizing signal HD from the synchronizing signal separation circuit 21 are supplied to the pulse generating circuit 36. Further, synchronization pulses corresponding to the horizontal synchronization signal volume and vertical synchronization signal D from the synchronization signal separation circuit 21 and the data synchronization signal Pd from the tuning circuit 34 are supplied to the data synchronization circuit 37, and the output thereof is supplied to the pulse generation circuit 36.
supplied to Further, the discrimination bits separated by the gate circuit 25 are supplied to the pulse generating circuit 35 on the read side, and as mentioned above, when the word read out from the time axis expansion circuit 24 is incorrect, the next correct word is read out. The read address is controlled as follows.

The discrimination bit is then supplied to the error correction control circuit 38,
This controls the average value interpolation circuits 28L and 28R, and a correction is made in which the erroneous word is replaced with the average value of the correct words before and after it. In order to perform such error correction, the PCM encoder performs word-by-word interleaf (rearranging the order) in order to disperse burst errors caused by dropouts and the like that occur in TRl, and the PCM decoder performs word-by-word dinterleaving (order change). (returning the order). The expansion of the time axis in the time axis expansion circuit 24 is the opposite of the time axis compression of the PCM encoder, in which the frequency of the read clock pulse is lower (1.4112 MHz) than the frequency of the write clock pulse (1.764 [MHz)].
z)).

Since this write operation is not performed during the data missing period RG, the write clock pulse is gated by a write gate pulse that becomes "゜0゛" during the data missing period RG of the odd field shown in FIG. 5A. This write gate pulse also serves as a gate pulse for the data extraction circuit 22.
39 is a muting control circuit which will be described later.

The muting control circuit 39 includes the CRC detection output PO from the CRC decoder 23 and the clock pulse generation circuit 33.
The lock detection output Pl indicates the state of the PLL circuit that constitutes the
is supplied, and when a predetermined number or more of CRC detection outputs PO indicating that an error has occurred is generated, a mutating signal Pm that turns on muting circuits 29L and 29R is generated, indicating that an error has occurred. When the PLL circuit of the clock pulse generation circuit 33 is in a locked state even though the CRC detection output PO has disappeared, a muting signal Pm is generated to turn off the muting circuits 29L and 29R. This muting signal Pm is also supplied to the data synchronization circuit 37. Further, to explain in detail one embodiment of the present invention, the interleaf and deinterleave in this embodiment are completed in one field period, and the data (245 x 3 = 735 words) within this period is divided into 8 pieces. The program is divided into 2 blocks, and each block is used as a unit. In other words, each of 7 of the 8 blocks is 92 words long, and the remaining 1 block is 91 words long. .Figure 6A shows this one block (
This shows a PCM signal of 92 words), and each number in FIG. 6 represents one word. First, even if the interleaf is in the original order shown in FIG.
By writing a PCM signal to AM and controlling the word address when reading this PCM signal, first read the odd numbered 46 words, then read the even numbered 4 words.
This is done by reading out 6 words. Therefore, the order of PCM signals recorded and reproduced by TRl is as shown in FIG. 6B. In addition, the CRC code is the 1st, 3rd,
The fifth word is added every three words, but is omitted in FIG. 6 for the sake of simplicity. Further, deinterleaving is performed by controlling the write word address of the RAM of the time axis expansion circuit 24. That is, the PCM signal supplied first is written to address 1, the PCM signal supplied second is written to address 3, and so on. Therefore, by reading out the PCM signal by sequentially specifying word addresses from address 1 to address 2 and 3 in the RAM of the time axis expansion circuit 24, the PCM signal appearing at the output of the time axis expansion circuit 24 is as shown in FIG. The original order shown is restored. Now, if the 7th, 9th, and 11th consecutive three words are erroneous as shown in FIG. 6B, the deinterleaved result is as shown in FIG. The result is an array in which correct words are located before and after , and as described above, it is possible to interpolate the average value of this erroneous word using the correct words before and after it.

Therefore, the length of burst errors that can be tolerated for this average value interpolation is 46 words or less within one block (approximately 15H or less in time). FIG. 7 shows an example of the muting control circuit 39, and also shows the clock pulse generation circuit 33.

The clock pulse generation circuit 33 has an input terminal 41 to which the vertical synchronization signal D is supplied from the synchronization signal separation circuit 21, and 14.
It has an output terminal 42 from which a clock pulse of 112 [MHz] can be obtained, and a phase comparison circuit 43, a low-pass filter 4VCO (voltage controlled variable frequency oscillator) 45, and frequency dividers 46 and 47 are provided between these inputs and outputs. This is the configuration of the PLL circuit. The output clock pulse is frequency-divided by ± in the frequency divider 46, and the 1600 pulses of 8.82 [KHz] are further divided into 7 by the frequency divider 47, so that the frequency becomes 60.
[Hz], and the phase comparator circuit 43 outputs the vertical synchronizing signal V.
The phase is compared with D. To detect whether such a PLL circuit is in lock, the output of frequency divider 46 is applied to a counter 48, and the output of counter 48 is applied to a D flip-flop 49.

The counter 48 is cleared by the vertical synchronization signal VD,
The output of the frequency divider 46 becomes "1" only when 147 outputs are counted. Therefore, if the PLL circuit is in a locked state, the counter 48 is set to "1" by a certain vertical synchronization signal VD. Since 147 outputs of the frequency divider 46 are counted until it is cleared by the next vertical synchronizing signal VD, when it is cleared by the vertical synchronizing signal VD,
The output of the counter 48 becomes "1". If the PLL circuit is not in the lock state, the counter 48 counts a number other than 147, so its output becomes "0". The output of this counter 48 is taken out by a D flip-flop 49 whose clock input is the vertical synchronizing signal VD,
The output 100 is used as the lock detection output P1 corresponding to the lock state of the PLL circuit. The muting control circuit 39 also has an input terminal 50 to which the CRC detection output PO is supplied.
, a clock input terminal 51 to which a clock pulse Cp with a period of 1H is supplied, and a muting signal output terminal 52.
It is equipped with

When the CRC detection output PO generated from the CRC decoder 23 contains an error in the 3-word PCM signal within 1H shown in FIG. 4, the CRC detection output PO is generated during the period 1Y! C), as shown in Figure 8A, ゜“1
゛, and when it is determined that there is no error, it does not become ``゜1゛.''

What about Figure 8 A? It has been determined that there is an error for a period of 3 consecutive days.
This is a case where CRC detection outputs PO are generated. Further, as shown in FIG. 8B, the clock pulse Cp is generated at approximately the middle phase of the period 1BG of every 1H, and the clock pulse Cp is generated from the horizontal synchronization signal separated by the synchronization signal separation circuit 21. be able to. This clock pulse Cp is inputted to the counter 56 by the AND gate 53 only when the CRC detection output PO is "゜1゛".
Further, this counter 56 is cleared by a clock pulse Cp by an AND gate 54 and an inverter 55 when the CRC detection output PO is 660°. The counter 56 is a step counter, and when P clock pulses are continuously supplied through the AND gate 53, a carry output of ゛゜1゛ is generated. In other words, in this example, by performing interleaving and deinterleaving as described above, it is possible to correct (average value interpolation) even errors over 15 consecutive H, so the 15 CRC detection outputs PO
When this occurs, it means that the limit of the correctable range has been reached, and this is detected and muting is performed. The output of the counter 56 is passed through an OR gate 57 and is used as a clear input to a 2-bit counter 58.

The 2-bit output of the counter 58 is supplied to a NAND gate 59, and the output of the NAND gate 59 is led to the output terminal 52 as a humuminating signal Pm. Further, the muting signal Pm and the vertical synchronizing signal VD are supplied to an AND gate 60, and the output of the AND gate 60 is used as the clock input of the counter 58. Further, the muting signal Pm and the aforementioned clock detection output P1 are supplied to an AND gate 61, and the output of this AND gate 61 is passed through an OR gate 57 and used as a clear input of the counter 58. When the muting signal Pm from the mutating control circuit 39 with the above configuration is 640'', the muting circuit 29L
and 29R are muted off as shown in FIG. 2, and when the muting signal Pm is 4"1",
The muting circuits 29L and 29R are muted on, and demodulated audio signals are prevented from appearing at the output terminals 32L and 32R. First, the VTR1 is operating stably, and the lock detection output P1 is 0. If more than one CRC detection output PO is generated in the state shown in FIG.

In this example, since the error is detected on the input side of the time axis expansion circuit 24, muting can be reliably applied before abnormal noise occurs. Therefore, the muting circuit 2 that mutates the PCM demodulated audio signal
Instead of providing 9L and 29R, time axis expansion circuit 2
It is also possible to use a muting means for prohibiting the read operation of No. 4 or a muting means for invalidating the read PCM signal. After mutating on, if the output of the counter 56 becomes "゜0゛" without successive 15H errors, the counter 58 counts the vertical synchronization signal VD supplied via the AND gate 60. .death,
When three of these are counted, the 2-bit output of the counter 58 becomes ゜“r′, and the mutating signal Pm becomes ゜0.
゛, and mutating off occurs.

The reason why muting is turned off after counting three vertical synchronization signals D is because the error is detected on the input side of the time axis expansion circuit 24, so it takes some time before the erroneous PCM signal is completely output. This is because it takes time. Therefore, the normal muting time is the period from when the output of the counter 56 reaches "0" until the three vertical synchronizing signals VD are supplied.
It is a short period of time. Further, when the operation of TRl is unstable such as when starting up, and therefore the reproduced PCM signal is unstable, it is often impossible to separate the vertical synchronization signal D, and no clock input is applied to the counter 58. Even if the vertical synchronization signal D is separated, if the operation of the TR is unstable and the period of the vertical synchronization signal VD is different from the normal synchronization, the lock detection output P1 will become "゜1゛" while counting three times. Alternatively, since the output of the counter 56 becomes ゜6r゛, the counter 58 is cleared.

When TRl is operating stably, even if mutating is turned on and then mutating is turned off (if an error of 15H or more occurs consecutively due to dropout etc.), immediately after this, the error of 15H or more will occur again. There is no possibility that a mistake will occur and result in a mutating on. However, when starting up the VTRl, there is a risk that such muting will turn on and off until the operation is stabilized by the servo system of the TRl, so the lock detection output P1 is used to turn off the mutating. I am trying to move to . As is clear from the above description, according to the present invention, it is possible to prevent abnormal sounds from occurring due to PCM signals containing errors that cannot be completely corrected.

Further, when the reproduced signal is unstable, such as when the VTR1 is started, it is possible to prevent the muting from being turned on and off repeatedly, thereby preventing unpleasant noise from occurring. Therefore, the time for performing the mutating operation can be minimized. If we set the time for the muting operation to correspond to the time from when the VTR is started until the operation is stabilized by the servo system, the time for the muting operation to be performed is set to be longer than necessary in cases where correction cannot be made during normal playback operation. A problem arises in that a muting operation is performed. Furthermore, the present invention is effective when applied to a PCM signal demodulator having an adapter configuration. In other words, when using an adapter configuration, since only recording or playback signals are input/output to a recording/playback device such as a TR, it is difficult to detect when an operation button like that used in a general VTR is pressed. Therefore, it is not possible to apply mutating when starting up the device. In addition, PC
Error detection and error correction of the M signal is not limited to the method of detecting errors using a CRC code and interpolating the average value as in the above embodiment, but also the method of recording the same PCM signal twice and using an error-free PCM signal. Alternatively, a method of correcting the error itself using an error correction code may also be used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a PCM encoder according to an embodiment of the present invention, FIG. 2 is a block diagram of the PCM decoder, and FIGS. 3, 4, 5, and 6 are diagrams of an embodiment of the present invention. FIG. 7 is a block diagram of the main part of an embodiment of the present invention, and FIG. 8 is a waveform diagram used for the explanation. 1 is TRl5L, 5R is a sampling hold circuit, 6
L, 6R are AD converters, 8 is a time axis compression circuit, 9 is CR
C encoder, 21 is a synchronization signal separation circuit, 23 is a CRC
Decoder, 24 is a time axis expansion circuit, 27L, 27R are D
A converter, 29L, 29R are mutating circuits, 39
is a mutating control circuit.

Claims (1)

[Claims] 1. A reproduction (or reception) signal consisting of a PCM signal obtained by PCM modulating an audio signal and a synchronization signal added to each predetermined length of this PCM signal is supplied, and from this reproduction (or reception) signal, the above-mentioned A PCM signal that separates a synchronization signal and substantially prevents abnormal sounds from being generated in a demodulated audio signal with respect to a PCM signal that has an error and cannot be corrected among the reproduced (or received) signals. In the demodulator, the separated synchronization signal is supplied to a phase synchronization circuit, which forms a timing signal for PCM demodulation, and detects phase synchronization between the separated synchronization signal and the timing signal. a state in which the separated synchronization signal and the timing signal are not phase-synchronized in a state in which the PCM signal cannot be corrected or corrected by the outputs of the phase synchronization detection circuit and the error detection circuit; A PCM signal demodulation device that performs the blocking operation in a state in which the PCM signal can be corrected or corrected and in a state in which the separated synchronization signal and the timing signal are in phase synchronization, cancels the blocking operation. .