KR100235614B1 - Digital- vhs codec - Google Patents

Abstract

Disclosed is a digital-VHS codec for digital data storage and playback that can perform massive computations that are impossible with program processing. A time stamp is generated for the digital data, and a plurality of sync blocks are stored in a plurality of tracks. The sync block filters the dummy sync block and outputs a normal sync block. The time stamp is compared with a reference time stamp to form a normal or dummy sink block at regular intervals. An identification number code and system data are generated and stored in the divided sink block. The sync block is shuffled and read a plurality of times at an address corresponding to an identification number code to generate an internal error correction code for the sync block, and an external error correction code to generate a parity sync block. The error occurring in the sync block is corrected, an identification number code and sync data are added to each sync block, formatted for the digital-VHS track format, and stored in the deck and the mounted video tape. The preamble, the sub code, and the main code are received by receiving the digital data in serial form, and the sink data is detected in each sink block in the main code area, and the data is classified in units of sync blocks.

Description

Digital-VHS Codec

The present invention relates to a digital-VHS codec for digital data storage and playback. More specifically, the present invention relates to a digital-VHS codec for digital data storage and reproduction that can perform massive calculations that are impossible with program processing in real time.

Since digital broadcasts using Moving Picture Experts Group (MPEG) 2 have begun, many broadcasters around the world are now or will soon be launching digital broadcasts. Broadcasters' participation in digital broadcasting is the main reason for providing high quality moving images and sound to viewers using digital data with little loss of information, and at the same time, the compatibility of digital information suitable for the multimedia era is the main reason. At this point, many overseas electronics companies are investing heavily in the development of digital data recorders (DRs) that can record and play digital broadcasts. Victor has written and finalized the STD digital-video home system (D-VHS) specification in agreement with Hitachi, Matsushita Electric and Philips Electronics. This is because D-VHS technology will prepare a way to cope with the rapidly changing multimedia as a recording medium in the coming future. D-VHS performs the existing VHS function and records compressed digital data transmitted through digital broadcasting and reproduces the data just before recording. This has great significance as a home digital storage medium utilizing the advantages of high density storage and low cost of existing tape media.

Digital broadcasting has video and audio characteristics such as multi-channel, high-quality picture, surround sound, and voice multiplexing.In terms of information, it can be divided into service information such as program lists and announcements and data broadcasting such as PC software, shopping catalogs, and electronic publishing. have. The ability to store and play back a myriad of diversified information is expected to play an essential role in the future.

D-VHS is a bit stream storage device having a function of storing and outputting compressed or processed data such as digital broadcasting on a tape without processing. Therefore, the bit stream recording apparatus does not need the analog-to-digital converter / digital-analog converter and the compression / reduction function. Of course, these signals are converted into video and audio signals through a conversion device and output as signals that can be recognized by humans.

Other D-VHS features include: first, functioning as a home data server (VCR and V & DR) for the multimedia age; second, integrating innovation from analog to digital signals; and third, for electronic files. Highly stable and cost-competitive by using a generalized ferric oxide tape (SVHS) which functions as a high density storage medium and finally has a proven production system. The recording performance of the D-VHS can store 7 hours of data for an input data rate of 14.1 MBPS and 14 hours for 7 MBPS in LP mode. This represents a storage capacity of 44 gigabytes. Application fields may be used in video servers, safety monitoring devices, data recording storage media, and the like.

An object of the present invention is to provide a digital-VHS codec for storing and reproducing digital data that can perform massive calculations which are impossible with program processing in real time.

1 is a diagram for explaining the structure of a track of a digital-video home system (D-VHS) video tape that can be used in the present invention.

FIG. 2 is a diagram for explaining the configuration of the main data sync block of the track shown in FIG.

FIG. 3 is a diagram for explaining the configuration of a sub code sync block of the track shown in FIG.

4 is a diagram showing the structure of an error correction code (ECC) of the track shown in FIG.

5 shows a track data format recorded on a D-VHS video tape that can be used in the present invention.

6 is a diagram showing a D-VHS digital broadcast data recording outline that can be used in the present invention.

7 is a block diagram showing the configuration of a D-VHS codec according to an embodiment of the present invention.

8A and 8B are flowcharts illustrating a D-VHS encoding method according to an embodiment of the present invention.

9A and 9B are flowcharts illustrating a D-VHS decoding method according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11: imaging tube 12: analog-to-digital converter

13: digital compressor 14: broadcasting station

15 satellite 16 antenna

17: set-top box 171: tuner

172: Digital Extender 173: Digital-to-Analog Converter

18: D-VHS 19: TV

701: time stamp generator 702: memory

703: dummy filter 704: smoothing / de-smoothing buffer

705: time stamp comparator 706, 711: packager

707: Reed-Solomon Encoder 708: Reed-Solomon Decoder

709: Track Formatter / Track Deformatter 710: Sync Pattern Detector

712: memory controller 713: first shuffler

714: second shuffler 715: ID calibrator

716: Error Information Register 717: Scrambler and Descrambler

718: Data Controller 719: ID Generator

720: microcontroller 721: switching pulse generator

722: pre-encoder 730: deck

In order to achieve the above object, the present invention provides M (where L is an integer of 1 or more) to each of L bytes of L (where L is an integer of 2 or more) inputted serially in a transport packet form from a satellite through a set-top box. A time stamp generator for generating a time stamp of bytes; A memory for respectively storing a plurality of sync blocks in the plurality of tracks; A dummy filter for filtering a dummy block in the sync block stored in the memory and outputting a normal sync block; A smoothing / de-smoothing buffer for comparing a time stamp from the time stamp generator with a reference time stamp and forming normal or dummy sink blocks at regular intervals according to the comparison result, and storing normal sink blocks from the dummy filter; A time stamp comparator for comparing a time stamp of the sink block and a reference time stamp from the smooth / de smooth buffer; A first packager for dividing the normal sync block stored in the smoothing / de smoothing buffer into two sync blocks and generating and storing an identification number code and system data in the divided sync blocks; Generates an internal error correction code for the sync block by shuffling and reading a sync block stored in the memory from the packager a plurality of times at a address corresponding to an identification number code stored in the first packetizer, and generating an external error. A Reed-Solomon encoder for generating a correction code to generate a parity sync block; A Reed-Solomon encoder for correcting an error occurring in the sync block stored in the memory; A track formatter / track deformatter for adding identification number codes and sync data to each sync block stored in the memory and formatting the digital-VHS track format for storage on a deck mounted video tape; Receives digital data in bit serial form from the video tape mounted on the deck to classify the preamble, sub code, and main code, and to classify data in sync block units by detecting sync data in each sync block in the main code area. Pattern detector; A second packager for storing the sync blocks detected by the sync pattern detector at regular intervals; And a controller for controlling an access operation to the memory by receiving a data request request from the first packager, the Reed-Solomon encoder, and a track formatter / track deformatter. to provide.

The digital-VHS codec for storing and reproducing digital data according to the present invention can perform massive calculations that are impossible with program processing in real time.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a diagram for explaining the structure of a track of a D-VHS video tape that can be used in the present invention. In a track of a D-VHS videotape, one track includes two first margin regions, three preamble regions, four sub code regions, three first post amble regions, three IB G regions, and 336 main codes It consists of 356 sync blocks comprising an area, two second post amble areas, and one second margin area. Each sync block consists of 896 bits. The main code area consists of a main data sink block. The sub code area consists of sub code sync blocks. One sub code area consists of four sub code sync blocks.

FIG. 2 is a diagram for explaining the configuration of the main data sync block of the track shown in FIG. The main data sink block is a 3-byte identification unique number code that includes a 2-byte sync code for identifying the sync block, 2 bytes for checking the sync block data, and 1 byte of additional information for error correction thereof. ), 99 bytes of main data including system data and bit stream data, and 8 bytes of internal parity for error correction.

FIG. 3 is a diagram for describing a configuration of a sub code sync block of a track shown in FIG. The sub code sync block is composed of a sink, ID, format ID, sub code data, and internal parity. One sub code sync block consists of 18 symbols of sub code data and 4 symbols of internal parity. One symbol consists of 8 bits.

4 is a diagram showing the structure of the ECC of the track shown in FIG. One ECC block consists of 102 data sink blocks and 10 external parity sync blocks. The main code area has 336 main data sink blocks. The 336 main data sink blocks are composed of 306 data sink blocks and 30 external parity sink blocks. The combined main code region of six tracks consists of 18 ECC blocks.

5 shows a track data format recorded on a D-VHS video tape that can be used in the present invention. As shown in FIG. 5, data is stored on a tape in track units, and these are sequentially stored with track number and SB number information assigned in RS encoding to enable error correction during reproduction. The track is composed of a preamble, a sub code, an interamble, main data, and a post amble. The upper 30 SB of the main data has additional information for error correction. RS coding for 18 ECCs is performed on these six tracks.

6 is a diagram showing a D-VHS digital broadcast data recording outline that can be used in the present invention. Reference numeral 11 is an imaging tube and reference numeral 12 is an analog / digital converter Reference numeral 13 is a digital compressor. Reference numeral 14 is a broadcast station, reference numeral 15 is a satellite, and reference numeral 16 is an antenna. Reference numeral 17 is a set-top box and set-top box 17 is composed of a tuner 171, a digital expander 172, and a digital-to-analog converter 173. Reference numeral 18 is D-VHS and reference numeral 19 is television. STD D-VHS has the capability to record data up to 14.1 MBPS for MPEG 2 bit stream data transmitted via digital satellite broadcasting. The STD D-VHS tape can store 44 gigabytes of information, corresponding to about seven hours of information.

D-VHS encoder according to an embodiment of the present invention will be described in detail. 7 is a block diagram showing the configuration of a D-VHS codec according to an embodiment of the present invention.

The D-VHS codec according to the embodiment of the present invention includes a time stamp generator 701, a memory 702, a dummy filter 703, a smoothing / de smoothing filter 704, a time stamp comparator 705, and a first pad. Keyizer 706, Reed-Solomon Encoder 707, Reed-Solomon Decoder 708, Track Formatter. 709, Sync Pattern Detector 710, Second Packager 711, Memory Controller 712 ), First shuffler 713, second shuffler 714, ID corrector 715, error information register 716, scrambler and descrambler 717, data controller 718, ID generator 719 And a micro controller 720.

The time stamp generator 701 is a reference program included in the MPEG 2-bit stream in digital data of L bytes (where L is an integer of 2 or more), which is serially input in the form of a transport packet from a satellite via a set-top box. A 27 MHz clock synchronized to a clock (program clock reference) is input and a 4 byte time stamp is generated at 27 MHz for the TPE to generate 192 byte data and output to the smoothing buffer 704.

The memory 702 stores 306 sync blocks from the first packageizer 706 as one track at a address corresponding to each ID included in the sync block. Six tracks make up a sequence. The memory 702 stores the sync block from the track formatter 709 under the control of the controller 718. The memory 702 may be configured of a dynamic random access memory (DRAM).

The dummy filter 703 filters the dummy block in the sync block stored in the memory 702 and provides the normal sync block to the smoothing and de smoothing buffer 704.

The smoothing / de-smoothing buffer 704 receives 192 byte TPE data including the time stamp from the time stamp generator 701 to determine whether the input time stamp is the same as the reference time stamp by the switching pulse generated by the switching pulse generator. In comparison, the normal sync block is generated in the same case and the dummy sync block is stored in the internal memory bank in the other case. The smoothing and desmoothing buffer 704 temporarily stores the normal sync block from the dummy filter 703 and outputs the normal sync block to the time stamp comparator 705 at a constant speed.

The time stamp comparator 705 reads the time stamp of each SB from the smoothing / de-smoothing buffer 704 and compares the value with a current reference time stamp to control the transmission time point to set the SB to match the transmission time point. Transmit to television 19 via device 17.

The first packetizer 706 divides the normal sync block stored in the smoothing / de smoothing buffer 704 into two sync blocks each having 96 bytes, and a 2-byte ID and 3-byte system for each sync block. Generate and store data. The system data consists of two bytes of main header and one byte of data-AUX. That is, the TPE data stores 96 bytes from address 6 to address 101 of the upper local memory bank in the first packager 706 and the remaining 96 bytes are stored in the lower local memory bank. While the data is being stored in the lower local memory, this indicates the ID of the sync block from address 0 to address 5 of the upper local memory, including the track number, its own SB number, and the current SB data recording system information. The main header is saved.

The first shuffler 713 shuffles 1836 SBs of six tracks stored in the memory 702 to bring the 102 SBs 18 times and is provided to the RS encoder 707. The shuffling method allows neighboring bytes to come from different tracks in order to improve the error correction capability when a burst error of the tape occurs.

The RS encoder 707 generates an internal correction code in the horizontal direction and an external correction code in the horizontal direction for the shuffled 18th 102 SBs from the first shuffler 713 to generate 30 parity sync blocks for each track. That is, 180 parity sync blocks are generated. That is, RS coding is performed in ECC units, and one track is composed of three ECCs. Each ECC shuffles data from six tracks to generate additional information. Note that the main data is sequentially recorded in track units, while the additional information for error correction is recorded in a shuffled form with a size of 30 SB at the top of the track. The RS encoder 707 has a flexible structure for performing all the decoding of the outer, inner, and sub codes. External parity corrects up to 10 symbol errors, and the inner and sub codes have 4 and 2 symbol error correction capabilities, respectively. In addition, the self-erase function allows error correction of up to 10 external ECC. The sub code can correct errors up to 2 symbols. The structure of the sync block stored at this time is the same as in FIG. 2 except for 2 bytes of sync.

The second shuffler 714 shuffles the SBs of the six tracks stored in the memory 702 to bring the 102 SBs 18 times and provides them to the RS decoder 708. The shuffling method is the same as in the first shuffler 712.

The RS decoder 708 performs error correction in units of ECC for the SBs of six tracks shuffled by the second shuffler 712. The RS decoder 708 has a flexible structure for performing all the decoding of the outer, inner, and sub codes. External parity corrects up to 10 symbol errors, and the inner and sub codes have 4 and 2 symbol error correction capabilities, respectively. In addition, the self-erase function allows error correction of up to 10 external ECC. The sub code can correct errors up to 2 symbols.

The track formatter / track deformatter 709 receives the sync data and ID generated from the ID generator 719 and adds the sync data and ID to each sync block of six tracks stored in the memory 702, and each track Form to match the D-VHS track format. That is, the track formatter 709 receives the sub code data from the control unit 718 as shown in FIG. 1 and receives first and second margins, first and second preambles, and first and second post ambles. In addition, IBG data is generated and added to each track and output to the scrambler and inverse scrambler 717, and the reverse function is performed.

The sync pattern detector 710 distinguishes a preamble, a sub code, and a main code from the track in the track having digital data in bit serial form from the deck 730, and finds a boundary of each SB unit in the main code area. As shown in FIG. 1 and FIG. 2, the data format as well as the boundary point is sensed to classify the data in units of SBs, and the data format is provided to the second packager 711 together with the data.

The second packageizer 711 stores the data classified in SB units detected by the sync pattern detector 710. The SB data stored in the second packager 711 is scrambled.

The memory controller 712 generates a storage address and a control signal of the corresponding data required for each block to read and write data from the memory 702 under the control of the controller. That is, when the sink block data is to be stored from the first packetizer 706, the memory controller 712 generates a storage address using the information of the header portion and stores the data together with the control signal. When a data request is received from the track formatter, the memory controller generates corresponding data, an address and a read signal, reads the data, and transfers the data to the track formatter. Of course, at this time, the fast page read operation is performed.

The ID corrector 715 performs error correction when the ID information in the header of each sync block from the second packager 711 is damaged and outputs the scrambler and inverse scrambler 717 to the scrambler and inverse scrambler 717. Used as an initialization value of).

An error information register (EIR) 716 stores error information of each sync block from the RS decoder 709 in order to reduce inefficient operation time, thereby enabling continuous data processing.

A scrambler / inverse scrambler 717 scrambles the formatted data from the track formatter 709 to the pre-encoder 722 and scrambled from the deck 730 to store it in the second packager 711. The data of the SB is scrambled and output to the track formatter / track deformatter 709.

Pre-encoder 722 pre-encodes the scrambled data from the scrambler / descrambler 717 and stores it on a tape mounted on deck 730.

The controller 718 receives a data request request from the first packager 706, the RS encoder 707, and the track formatter 709 to control the memory controller 712 to store a storage address and a control signal of the corresponding data. By providing to 702, the memory 702 distributes time so that the memory 702 can be accessed. It also plays an arbitration role in the event of a conflict. In addition, the controller 718 stores the sub code data generated by the microcontroller 720 in the memory 702 and adds parity information to the track formatter / track deformatter 709.

D-VHS codec operation and D-VHS encoding method according to the embodiment of the present invention configured as described above, that is, digital data storage method will be described. 8A and 8B are flowcharts illustrating a D-VHS encoding method according to an embodiment of the present invention.

As shown in FIG. 6, the MPEG 2 bit stream digital data propagated from the broadcast station 14 through the satellite 15 and the antenna 16 is selected through the tuner 171 of the set-top box 17. It is input to the D-VHS codec 70 through the time stamp generator 701 of the D-VHS codec 70 via a digital interface. At this time, the input data is serially input in the form of a transport packet element (TPE) composed of 188 bytes (step S1).

The time stamp generator 701 receives a 27 MHz clock synchronized to a program clock reference included in the MPEG 2 bit stream, generates a 4 byte time stamp at 27 MHz for the APE, and adds it to the 188 byte TPE. The data is made into 192 byte data and output to the smoothing / inverse smoothing buffer 704 (step S2).

The smoothing / de-smoothing buffer 704 receives 192 byte TPE data including the time stamp from the time stamp generator 701 to determine whether the input time stamp is the same as the reference time stamp by the switching pulse generated by the switching pulse generator. It is judged whether or not (step S3).

In step S3, when it is determined that the input time stamp is the same as the reference time stamp, the smoothing / de smoothing buffer 704 stores the TPE data as a normal sink block in an internal memory bank (step S4). . However, if it is determined that the input time stamp is different from the reference time stamp, the smoothing / de smoothing buffer 704 generates the TPE data as a dummy sink block and stores the TPE data in an internal memory bank (step S5). That is, these input information go through a smoothing process of converting the input channel data into a constant bit rate by a variable input bit rate generated in the process of selecting data of a desired channel from the multiplexed data.

The first packetizer 706 separates the normal SBs stored in the smoothing / de-smoothing buffer 702 into two sync blocks each having 96 bytes (step S6), and a 2-byte ID for each sync block and Three bytes of system data are generated and stored (step S7).

The controller 718 controls the memory controller 712 to provide a storage address and a control signal of the corresponding data to the memory 702. The control unit 718 controls the SB data (102 bytes) of the six tracks stored in the first packager 706 in the fast page method to synchronize the SB data (102 bytes) from the first packager 706 with the ID. Is stored in the address of the memory 702 having the 4-megabit capacity corresponding to the ID (step S8).

In step S9, the controller 718 determines whether or not sync block data of six tracks has been stored in the memory 702. If it is determined in step S9 that the sync block data of the six tracks is not stored in the memory 702, the first shuffler 713 shuffles the SBs of the six tracks previously stored in the memory 702 to generate 102 pieces of data. 18 SBs are taken and provided to the RS encoder 707 (step S91). The RS encoder 707 generates an internal correction code in the horizontal direction and an external correction code in the horizontal direction for the shuffled 18th 102 SBs from the first shuffler 713 to generate 30 parity sync blocks for each track. That is, 180 parity sync blocks are generated and stored again in the memory 702 (step S92).

On the other hand, if it is determined in step S9 that the sync block data of the six tracks is stored in the memory 702, the first shuffler 713 shuffles the SBs of the six tracks newly stored in the memory 702 to generate 102 pieces of data. 18 SBs are taken and provided to the RS encoder 707 (step S10).

The RS encoder 707 generates an internal correction code in the horizontal direction for the shuffled 18th 102 SBs from the first shuffler 713 (step S11), and generates an external correction code in the vertical direction for each Thirty parity sync blocks, i.e., 180 parity sync blocks, are generated for each track and stored in the memory 702 again (step S12). That is, RS coding is performed in ECC units, and one track is composed of three ECCs. Each ECC shuffles data from six tracks to generate additional information. Each sync block generates internal parity and external parity through data shuffling through RS coding. This process takes place for all six tracks.

The controller 718 determines whether or not the recording stop signal is applied (step S13). If it is determined in step S13 that the recording stop signal is applied, all operations are completed. If it is determined that the recording stop signal is not applied, the controller 718 receives sub-code data from the external microcontroller 720. Each SB received and added to each SB stored in the memory 702 is provided to the track formatter / track deformatter 709 to which the subcode data is added.

Accordingly, the track formatter / track deformatter 709 receives the sync data and ID generated from the ID generator 719 and adds the sync data and ID to each sync block of six tracks stored in the memory 702. Each track is formed in accordance with the D-VHS track format (step S14). That is, the track formatter / track deformatter 709 receives the subcode data from the control unit 718 as shown in FIG. 1 and receives first and second margins, first and second preambles, first and second tracks. The second post amble and IBG data are generated and added to each track and output to the scrambler / inverse scrambler 717.

The scrambler / descrambler 717 scrambles the D-VHS formatted data from the track formatter / track deformatter 709 to the pre-encoder 722 (step S15).

Pre-encoder 722 pre-encodes the scrambled D-VHS formatted data from the scrambler / inverse scrambler 717 (step S16), onto a D-VHS tape (not shown) mounted to deck 730. Save (step S17), and the routine returns to step S13.

The D-VHS codec 70 performs shuffling to distribute cluster errors, which are processed in units of one frame. One frame is performed with six sequential data from track 0 to track 5.

Hereinafter, an operation of the D-VHS codec and a D-VHS decoding method according to an embodiment of the present invention, that is, a method of reproducing digital data stored on a tape by the D-VHS.

9A and 9B are flowcharts illustrating a D-VHS decoding method according to an embodiment of the present invention. 9A and 9B, when digital data in bit serial form is input to the sync pattern detector 710 from the D-VHS tape of the deck 730, the sync pattern detector 710 is shown in FIG. As shown in FIG. 2, the preamble, the sub code, and the main code are distinguished from each track (step S91). As shown in FIG. Provided to second packager 711 (step S92).

The second packager 711 stores the data divided by the SB unit sensed by the sync pattern detector 710 (step S93), and outputs the data divided by the SB unit to the scrambler / inverse scrambler 717. The header ID of each SB is separated and provided to the ID calibrator 715. The ID calibrator 715 performs error correction when the ID information in the header of each sync block from the second packager 711 is damaged and outputs the scrambler / descrambler 717 to the scrambler / descrambler 711. Used as an initialization value of).

The scrambler / descrambler 711 descrambles the scrambled data of the SB and outputs it to the track formatter / track deformatter 709 (step S94).

The track formatter / track deformatter 709 deformats the descrambled SB data from the scrambler / descrambler 711 and provides it to the controller 718.

The controller 718 controls the memory controller 712 to provide a storage address and a control signal of the corresponding data to the memory 702. In addition, the control unit 718 controls the SB data of the six tracks from the track formatter / track deformatter 709 by using an ID included in the SB data in a fast page method in synchronization with a system clock. The data is stored at the address 702 (step S95). At this time, the ID data is transmitted to the memory controller 712 to inform the address where it should be stored.

The controller 718 determines whether the SB data of six tracks from track 0 to track 5 are all stored in the memory 702 (step S96),

If it is determined in step S6 that the SB data of all six tracks is not stored in the memory 702, the second shuffler 714 may store six tracks previously stored in the memory 702 as shown in FIG. 4. Shuffle the SBs (step S961), bring 112 SBs 18 times and provide them to the RS decoder 708. The RS decoder 708 performs error correction in units of ECC for SBs of six previously stored tracks (step S962).

If it is determined in step S6 that the SB data of all six tracks is stored in the memory 702, the second shuffler 714 is the SB of the six tracks newly stored in the memory 702 as shown in FIG. (Step S97), 112 SBs are taken 18 times and provided to the RS decoder 708.

The RS decoder 708 performs all the internal ECC for the SBs of the six newly stored tracks (step S98), and performs the external ECC (step S99). In the present invention, after performing all the internal ECC in SB unit, the reason for performing the external ECC is to perform the internal ECC first to distinguish the SB that cannot be corrected by error and to process the eraser to perform an external ECC having excellent error correction capability. This is to correct more errors. In particular, since the internal ECC is performed after the external ECC in the recording process, the reverse process thereof becomes the internal error correction decode (ECD) and the external ECD.

Using fast page mode, data is read in units of SBs, and each SB is first input directly to the RS decoder to perform internal error detection, and their error location and error size information is an error information register (EIR) made of SRAM. It is stored sequentially in the location assigned to. The reason for this is that the RS decoder has a three block size intermittent time to decode one block code to prevent unnecessary time delay and to ensure continuous operation of the SB to perform fast operation.

When the internal error detection process is completed for 112 SBs, error correction is performed using information of the EIR.

The memory controller 712 reads the error location information of the EIR, calculates a memory address, and corrects the error using a read modifier write operation. In the same manner, when the error correction is completed for the remaining 17 ECCs, the error correction process of six tracks considered in RS coding is completed.

The control unit 718 determines whether or not the reproduction stop signal is input (step S100). In operation S100, when it is determined that the reproduction stop signal is input, the operation is completed. When it is determined that the reproduction stop signal is not input, the controller 718 controls the memory controller 712 to control the memory 702. In step S101, the data stored in the data is retrieved at high speed and stored in the first packager 706 (step S101).

The dummy filter 703 retrieves the SB stored in the first packager 706, filters the dummy SB, and provides only the normal SB to the smoothing / de smoothing buffer 704 at a constant speed (step S102). Smoothing / de-smoothing buffer 704 stores the normal SB from the dummy filter 703 (step S103).

The time stamp comparator 705 reads the time stamp of each SB from the smoothing / de-smoothing buffer 704 and compares the value with the current reference time stamp (step S104) to control the transmission time to set the SB to the top. It transfers to the television 19 via the box apparatus 17 (step S105), and returns to step S100.

The digital-VHS codec for storing and reproducing digital data according to the present invention can perform massive calculations that are impossible with program processing in real time.

Although this invention was demonstrated concretely by the said Example, this invention is not restrict | limited by this, A deformation | transformation and improvement are possible within the range of common knowledge of a person skilled in the art.

Claims (12)

Generate a time stamp of M (where M is an integer of 1 or more) bytes to each of the L (where L is an integer of 2 or more) bytes of digital data, which are serially entered in the form of a transport packet from the satellite via a set-top box. A time stamp generator 701 for doing so; A memory 702 for respectively storing a plurality of sync blocks in the plurality of tracks; A dummy filter (703) for filtering the dummy block in the sync block stored in the memory (702) and outputting a normal sync block; Comparing a time stamp from the time stamp generator 701 to a reference time stamp and forming normal or dummy sink blocks at regular intervals according to the comparison result, and smoothing / reverse for storing normal sink blocks from the dummy filter. Smoothing buffer 704; A time stamp comparator (705) for comparing a time stamp and a reference time stamp of the sync block from the smooth and desmoothing buffers (704); A first packager (706) for dividing the normal sync block stored in the smoothing and desmoothing buffer (704) into two sync blocks and generating and storing an identification number code and system data in the divided sink blocks; A Reed-Solomon encoder 707 for generating a parity sync block by generating an internal error correction code for the sync block and generating an external error correction code for the sync block by shuffling and reading a plurality of sync blocks stored in the memory 702. ; A Reed-Solomon decoder 708 for correcting an error caused by shuffling and reading a plurality of sync blocks stored in the memory 702; A track formatter / track deformatter 709 for adding an identification number code and sync data to each sync block stored in the memory 702, formatting the digital-VHS track format, storing it in a deck, and performing the reverse function; Receives digital data in the form of bits from a video tape mounted on the deck, and divides the preamble, sub code, and main code, and detects sync data in each sync block in the main code area to divide data in sync block units. Pattern detector 710; A second packager 711 for storing the sync blocks detected by the sync pattern detector 710 at regular intervals; And a controller configured to receive a data request request from the first packageizer 706, the Reed-Solomon encoder 707, and the track formatter / track deformatter 709 to control an access operation to the memory 702. Digital-VHS codec, characterized in that (718). The time stamp generator 701 receives a clock synchronized with a program clock on a basis of a bit stream, and generates a 4-byte time stamp for a 188-byte transport packet element to generate 192-byte data. Digital-VHS codec, characterized in that for generating. 2. The method of claim 1, wherein a normal sync block is formed when the time stamp from the time stamp generator 701 is the same as a reference time stamp as a result of the comparison between the smoothing and the anti smoothing buffer 704, and a dummy sync block is otherwise formed. Digital-VHS codec, characterized in that. The memory controller of claim 1, further comprising a memory controller 712 for generating a storage address and a control signal of a corresponding data required for each block to read and write data from the memory 702 under the control of the controller 718. Digital-VHS codec, characterized in that it comprises a. 2. The apparatus of claim 1, further comprising a first shuffler 713 for shuffling all sync blocks of all tracks stored in the memory 702, bringing a predetermined number of sync blocks a plurality of times, and providing them to the Reed-Solomon encoder. Digital-VHS codec, characterized in that it comprises. The second shuffler 714 according to claim 1, wherein the second shuffler 714 is used to shuffle all sync blocks of all tracks stored in the memory 702 to bring a predetermined number of sync blocks a plurality of times and provide them to the Reed-Solomon decoder 708. Digital-VHS codec, characterized in that it further comprises). 2. The digital receiver of claim 1, further comprising an identification number code corrector 715 for performing error correction of the identification number code in the header of each sync block from the second packager 711. -VHS codec. 2. The apparatus of claim 1, further comprising an error information register 716 for storing error information of each sink block stored in the memory 702 in order to continuously process each sink block data stored in the memory 702. Digital-VHS codec, characterized in that. The scrambled data of the track formatter / track deformatter 709 is scrambled and stored in a tape mounted on the deck, and the scrambled data from the second packager 711 is stored. Digital-VHS codec, characterized in that it further comprises a scrambler / reverse scrambler (717) for descrambling. The digital-VHS codec according to claim 1, further comprising a pre-encoder (722) for pre-encoding the formatted data from the track formatter / track deformatter (709). The digital-VHS codec according to claim 1, wherein the L byte of digital data and the M byte time stamp are composed of 118 bytes and 4 bytes, respectively. The digital-VHS codec according to claim 1, wherein the set number track is six tracks.