JPH0822673A - Recording device and reproducing device - Google Patents

Abstract

PURPOSE:To reduce a circuit scale of a reproducing device by equalizing a data form obtained from a signal source of a recording device with a data form obtained from a reproducing block of a reproducing device, when a data string in which quantities of data are different for each frame is recorded and reproduced. CONSTITUTION:A tuner 101 receives a broadcasting wave of digital broadcast, performs demodulation processing and the like, and outputs a compressed packet train 106 to a recording block 102 in synchronism with a clock 107 having the prescribed frequency without intermission. A frame reference signal generating circuit 103 generates a frame reference signal, and outputs it to a recording block 102 and a count block 111. The count block 111 consists of a counter 104 and a register 105, counts the clock 107 during one period of a frame reference signal 110, and sends it to the recording block 102. The recording block 102 records the number of this clocks together with the data of the packet train 106.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording device and a reproducing device for recording and reproducing compressed video and audio data.

[0002]

2. Description of the Related Art Currently, a digital VTR for recording video and audio as digital signals on a magnetic tape is under development. Since the video signal has a very large amount of information, if it is recorded on the tape as it is, the amount of the tape used becomes very large, which is not suitable for consumer use. Therefore, data compression is performed to the extent that tape consumption can be reduced to a level that can be used for consumer use. In the currently developed digital VTR, the data compression circuit is completed within one frame so as to reduce the circuit scale. When data compression is performed by this method, the amount of data in one frame of the video signal becomes constant. Further, also in the audio signal, the data amount in one frame is made constant by adding dummy data. That is, in the digital VTR currently under development, the amount of data recorded on the tape within one frame period of the video signal input to the digital VTR is always constant. In other words, the digital VTR records video / audio data on the tape at a constant recording rate in synchronization with the frame signal of the input video signal.

At the time of reproduction, a frame reference signal corresponding to the frame signal of the video signal is generated inside the digital VTR to synchronize the rotary head of the VTR and the tape feed speed with the reference signal. The data recorded on the tape is reproduced from the tape in synchronization with this reference signal. At this time, the amount of data reproduced within one frame period divided by the reference signal is constant. The reproduced audio data is subjected to a predetermined process such as removal of added dummy data, etc., and then converted into an analog audio signal, and then a digital VTR.
Output to the outside. Further, since the video data is subjected to data compression which is completed within one frame, the data is decompressed, converted into an analog video signal and output to the outside.

However, in order to further reduce the amount of data after compression of video and audio, a data compression method called MPEG2 is under development. In this method, especially video signals are compressed using video data of multiple frames,
The data amount of the input video signal differs for each frame. Each frame of the video signal compressed by this method is I
It is composed of a frame called a frame, which is compressed within one frame, and a frame consisting of only difference data between frames called B frame and P frame. Since the I frame is compressed so that it is completed within one frame, the compression rate cannot be increased, and the amount of data after compression is much larger than other B frames and P frames. Further, since the B frame and the P frame are composed only of the difference values from the adjacent frame and the I frame, the data amount of these frames after compression is very small. In this way, the video data compressed by the method called MPEG2 has a different data amount for each frame.

In the MPEG2 system, a packet called a transport packet is defined so that compressed data can be transmitted to another device or recorded on a recording medium. The compressed video data and audio data are divided into a plurality of transport packets and are packetized for transmission or recording. Also, audio data and video data use different transport packets.

According to MPEG2, not only one program is transmitted and recorded but also a plurality of programs and also character information can be transmitted or recorded. The video data and audio data of each program are packetized into transport packets, and the character information is also packetized. These transport packets of a plurality of programs and character information are multiplexed and transmitted and recorded.

At present, in the United States, a "broadcast system which uses terrestrial waves to transmit video and audio as digital signals with the same bandwidth as the current broadcast system" has been developed. In this system, transport packets are packetized according to the MPEG2 system, and each transport packet of video data and audio data of one program or a plurality of programs is multiplexed. The data rate of the transport packet after multiplexing is a predetermined data rate (for example, about 1
9.3 Mbps). In the ATV, a predetermined error correction parity is added to this transport packet, modulation is performed by a predetermined method, and the terrestrial wave is used for broadcasting. This system is currently being implemented using terrestrial waves, but it can also be applied to satellite broadcasting, cable television, and the like. Further, although the current data rate of transport packets is about 19.3 Mbps, a higher transmission rate (for example, about twice as high as that for broadcasting higher quality programs or more programs at the same time). Three
It is also considered to be broadcast at 8.6 Mbps).

The digital VTR currently being developed is
As described above, it is recorded in synchronization with the frame of the video signal. The recording rate of this VTR is the VTR for the current broadcasting system.
Is about 25 Mbps, and the VTR for high-definition broadcasting is about 50 Mbps. Therefore, since the data rate of ATV (about 19.3 Mbps) is higher than the recording rate of VTR, it is possible to record all transport packets. However, in a data string where the amount of data in each frame is different, such as ATV,
When inputting data at a constant data rate, the time required for inputting varies greatly from frame to frame. That is, the frame cycle of this data string changes greatly for each frame. The digital VTR currently under development is designed to record in synchronization with the video signal frame.
If the frame cycle changes for each frame, the VTR
It becomes very difficult to achieve frame synchronization.

A possible method for recording a bit string of an MPEG2 transport packet on the digital VTR will be described. This description takes as an example a VTR for current broadcasting, which has a recording rate of about 25 Mbps. During recording, the VTR independently generates a frame reference signal inside the VTR. This frame reference signal is a signal irrelevant to the data rate of the input MPEG2 transport packet. Therefore, the data amount of the MPEG2 transport packet recorded on the tape within each frame period determined by the frame reference signal is different for each frame. Also, 19.3 Mb
When the data rate of the MPEG2 transport packet of ps is recorded in the VTR of the recording rate of 25 Mbps, dummy data is recorded to complement the data rate corresponding to the difference. Since the amount of data recorded by the VTR in each frame is constant, the amount of data in the MPEG2 transport packet sequence recorded in one frame period of the VTR differs from frame to frame.

Next, a method of reproducing a tape recorded by such a method will be described. The VTR reproduces in synchronization with the internal frame reference signal. The data reproduced from the tape is reproduced at a reproduction rate of about 25 Mbps. When data is output from the VTR playback device, the dummy data added during recording is removed and only MPEG2 transport packet data is output.

FIG. 6A shows a packet sequence of MPEG2 transport packets input to the recording device of the VTR during recording. Transport packet 601 is 1
It is input at a data rate of 9.3 Mbps. As shown in FIG. 6B, the dummy data 602 is added and recorded so that the recording rate becomes about 25 Mbps. At the time of playback, from the top of the tape, as shown in FIG.
It is played back at a playback rate of Mbps. When data is taken out from the VTR playback device, as shown in FIG.
The dummy data 602 will be taken out in a removed state. Further, the data string in FIG. 6C is synchronized with the frame reference signal inside the VTR.

When the data rate input to the VTR recording device is higher than the VTR recording rate, for example, MPE
The data rate of the transport packet train of G2 is 3
The recording rate of the VTR is 25 Mbps at 8.6 Mbps.
, It is not possible to record all this input data. In order to record such high data rate data, a VTR having a higher recording rate is required. In the case of this conventional example, the recording rate corresponding to high-definition broadcasting is about 5
A 0 Mbps VTR will be used.

[0013]

The first problem to be solved by the present invention will be described. Originally, the VTR should be output in the same format as the input. The reason is that the VTR may not record the data input from the signal source but may perform a predetermined process as it is to restore the video and audio. Therefore, when the format of the data directly input from the signal source and the format of the data input from the playback device at the time of playback are different, it is necessary for the circuit that performs the above-mentioned predetermined processing to support multiple formats. This is because the circuit scale of the processing circuit becomes large. When recording and reproducing by the conventional method, as described above,
The format of the data input to the recording device of the VTR shown in FIG. 6A and the format of the data reproduced by the reproducing device of the VTR shown in FIG. 6C are different. Therefore, in the conventional technique, there is a problem in that the circuit scale of a circuit that receives reproduction data from a reproduction device, receives data from a signal source at the time of recording, and performs predetermined processing for restoring video and audio becomes large. Had.

Next, a second problem to be solved by the present invention will be described. MP input to VTR recording device
Data rate of EG2 transport packet is about 3
In the case of 8.6 Mbps, it cannot be recorded in the VTR for the current broadcasting, which has a recording rate of about 25 Mbps. Three
The data rate of 8.6 Mbps may be a case where a plurality of programs are multiplexed. It is also possible that the user only needs to record one of the programs.
However, when the data rate is about 38.6 Mbps due to the multiplexing of a plurality of programs, the conventional technique requires the use of a VTR compatible with high-definition broadcasting because the data rate exceeds the recording rate of 25 Mbps. There wasn't. That is, the conventional technique has a problem that a VTR having a large circuit scale and a very large tape consumption amount must be used.

[0015]

A recording apparatus of the present invention (first
Is a data output means for outputting the compressed video data and audio data in synchronism with a clock having a predetermined frequency, reference signal generating means for generating a reference signal at a predetermined cycle, and the reference signal generating means. Clock counting means for counting the clock within the period of the reference signal generated by the means, the count value counted by the counting means, the video data and the audio data are recorded on the recording medium in synchronization with the reference signal. It is characterized in that a recording means for recording is provided.

The reproducing apparatus (second configuration) of the present invention comprises a reference signal generating means for generating a reference signal at a predetermined cycle,
Reproducing means for reproducing the video data and audio data recorded on the recording medium and the count value in synchronization with the reference signal, a reproducing clock generating means for generating a reproducing clock having a predetermined frequency, and the reproduced count. Reproduction clock counting means for counting the reproduction clock by a value, second reference signal generating means for generating a second reference signal when the reproduction clock counting means reaches a predetermined value, the reference signal and the second reference signal. And a phase error detecting means for detecting the phase error of (1) and an input means for inputting the video data and the audio data reproduced by the reproducing means in synchronization with the reproduction clock.

The recording apparatus of the present invention (third configuration)
A data output means for outputting a plurality of compressed video data and audio data in synchronization with a clock having a predetermined frequency; and a data selection means for selecting arbitrary data from the plurality of video data and audio data. A reference signal generating means for generating a reference signal for each predetermined cycle, a clock counting means for counting the clock within a cycle period of the reference signal generated by the reference signal generating means, and a count counted by the counting means It is characterized by comprising recording means for recording the value and the selected data selected by the selecting means on a recording medium in synchronization with the reference signal.

Further, the reproducing apparatus of the present invention (fourth structure)
Is a reference signal generating means for generating a reference signal for each predetermined period, a reproducing means for reproducing the selection data and the count value recorded on a recording medium in synchronization with the reference signal, and a reproducing means of a predetermined frequency. A regenerated clock generating means for generating a clock, a regenerated clock counting means for counting the regenerated clock by the regenerated count value, and a second reference signal for generating a second reference signal when the regenerated clock counting means reaches a predetermined value. Reference signal generating means, phase error detecting means for detecting a phase error between the reference signal and the second reference signal, pseudo data generating means for generating pseudo data, the selection data reproduced by the reproducing means, and the selection data. A multiplexing unit for multiplexing pseudo data; and an input unit for inputting the selection data and the pseudo data in synchronization with the reproduction clock. To have.

The reproducing apparatus of the present invention (fifth structure)
Is characterized in that, in the reproducing apparatus having the above-mentioned second and fourth structures, the reproduced clock generating means changes the frequency of the reproduced clock according to the phase error obtained from the phase error detecting means.

The reproducing apparatus of the present invention (sixth configuration)
Is characterized in that, in the reproducing apparatus having the second and fourth configurations, the reference signal generating means changes the frequency of the reference signal according to the phase error obtained by the phase error detecting means.

[0021]

The recording device of the first structure counts the number of clocks of the clock input from the signal source together with the data for one frame period for each frame according to the internal frame reference signal,
The number of clocks is recorded together with data on the recording medium for each frame. The recording medium thus recorded can be reproduced by the reproducing apparatus having the second and fifth configurations. The reproducing device reproduces the data in synchronization with the frame reference signal.
The reproduction clock generated by the reproduction clock generating means is counted by the value of the number of reproduced clocks, and the second reference signal is generated when the count result reaches a predetermined value. The phase difference between the frame reference signal and the second reference signal is detected, and the frequency of the reproduction clock generated by the reproduction clock generating means is changed so as to reduce the phase difference. The reproduction data is output from the reproduction means in synchronization with the reproduction clock.

The recording medium recorded by the recording apparatus having the first structure can be reproduced by the reproducing apparatus having the second structure and the sixth structure. The reproducing device reproduces the data in synchronization with the frame reference signal. The reproduction clock generated by the reproduction clock generating means is counted by the value of the number of reproduced clocks, and the second reference signal is generated when the count result reaches a predetermined value. The phase difference between the frame reference signal and the second reference signal is detected. In this embodiment, the reproduction clock generated by the reproduction clock generating means is always generated at a constant frequency. In this embodiment, the frame reference signal and the second
The frequency of the frame reference signal is changed so as to reduce the phase difference of the reference signal. The recording device reproduces data in synchronization with a frame reference signal whose frequency changes depending on the phase difference. The reproduction data thus reproduced is input to the input means in synchronization with the reproduction clock having a fixed frequency.

The recording device of the third structure selects only the data to be recorded among the input data by the data selecting means and records it on the recording medium in the same manner as the recording device of the first structure. The recording apparatus counts the number of clocks of the clock input from the signal source together with the data for one frame period for each frame according to the internal frame reference signal as in the recording apparatus of the first configuration, and the clock number is calculated for each frame. It is recorded together with the data on the recording medium. The recording medium thus recorded can be reproduced by the reproducing apparatus having the fourth and fifth configurations. The reproducing device reproduces the data in synchronization with the frame reference signal. The reproduction clock generated by the reproduction clock generating means is counted by the value of the number of reproduced clocks, and the second reference signal is generated when the count result reaches a predetermined value. The phase difference between the frame reference signal and the second reference signal is detected, and the frequency of the reproduction clock generated by the reproduction clock generating means is changed so as to reduce the phase difference. In order to complement the data removed by the selecting means at the time of recording, the pseudo data generating means generates pseudo data, and the selected data and the pseudo data to be reproduced are multiplexed. These data are input to the input means in synchronization with the reproduction clock.

The recording medium thus recorded can be reproduced by the reproducing apparatus having the fourth and fifth configurations. The reproducing device reproduces the data in synchronization with the frame reference signal. The reproduction clock generated by the reproduction clock generating means is counted by the value of the number of reproduced clocks, and the second reference signal is generated when the count result reaches a predetermined value. The phase difference between the frame reference signal and the second reference signal is detected, and the frequency of the frame reference signal is changed so as to reduce the phase difference. The recording device reproduces data in synchronization with a frame reference signal whose frequency changes depending on the phase difference. Further, in order to complement the data removed by the selecting means at the time of recording, the pseudo data is generated by the pseudo data generating means, and the reproduced selective data and the pseudo data are multiplexed. These data are input to the input means in synchronization with a reproduction clock having a fixed frequency.

[0025]

Embodiments of the present invention will be described with reference to the drawings. The embodiment will be described by taking a digital VTR for recording and reproducing a digital broadcast such as ATV as a digital signal on a magnetic tape.

FIG. 1 shows a block diagram of a first embodiment of the recording apparatus of the present invention. The recording apparatus according to the present embodiment includes a tuner 101 (output means), a recording block 102 (recording means), a count block 111 (counting means), and a frame reference signal generation circuit 103 (reference signal generation means).

The tuner 101 receives a broadcast wave of digital broadcasting, performs a predetermined process such as a demodulation process and an error correction process, and outputs the MPEG2 transport packet sequence 106 to the recording block 102. The MPEG2 transport packet sequence 106 is video data and audio data compressed as described above. The MPEG2 transport packet sequence 106 has a clock 107 of about 19.3 MHz.
, And is output to the recording block 102 without any gap. The frame reference signal generation circuit generates a frame reference signal serving as a reference for the recording operation of the recording block 102 and outputs it to the recording block 102 and the count block 111. In this embodiment, the frame reference signal 110 is 1.001 / 30.
It is a signal that rises every second. 1.001 / 30
The time of second is the time for the recording block 102 to form ten tracks on the tape. That is, the recording block 102 records video data and audio data on the tape in synchronization with the frame reference signal 110. Clock 107
Is input to the count block 111 and the recording block 102.

The count block 111 is a counter 104.
And a register 105. The operation of the counter block will be described with reference to FIG. The frame reference signal 110 is input to the counter 104 and the register 105. The counter 104 counts the clock 107 and outputs the count value 108 to the register 105. As shown in FIG. 2, the counter 104 is reset to 0 when the frame reference signal 110 rises and is incremented by 1 in synchronization with the clock 107. In FIG. 2, when the frame reference signal 110 first rises, the count value 108 is reset from n to 1 and 1
Each time it rises, it is reset from m to 1 the next time it rises. The register 105 holds the count value 108 input from the counter 104 when the frame reference signal 110 rises. Register 1
05 holds the value until the frame reference signal 110 rises next time. In FIG. 2, the register 105 holds the count value n when the frame reference signal 110 first rises,
When it next rises, it holds the count value m. The count value 109 held by the register 105 is the recording block 1
It is output to 02.

The recording block 102 multiplexes the MPEG2 transport packet sequence 106 and the count value 109,
The data is recorded on the tape in synchronization with the frame reference signal from the frame reference signal generation circuit 103. FIG. 3 shows a configuration example of the recording block 102. The recording block 102 includes a memory 301, an ECC circuit 302, a modulation circuit 303, and a control circuit 304. The memory circuit 301 changes the data rate for recording the MPEG2 transport packet sequence 106 input in synchronization with the clock 107 in synchronization with the frame reference signal 110. Control circuit 3
04 is a memory 301 in synchronization with the frame reference signal 110
A control signal for reading the MPEG2 transport packet sequence from is generated and output to the memory 301. The transport packet sequence is input from the memory 301 in synchronization with the frame reference signal 110, and the count value 109 is also input. As described above, the data rate of the MPEG2 transport packet is 19.3 Mbps, and the recording rate of this VTR is 25 Mbps. The ECC circuit 302 generates dummy data to complement the difference in data rate. Further, the ECC circuit 302 adds a parity code for error correction to the dummy data, the input MPEG2 transport packet sequence, and the count value, and inputs them to the modulation circuit 303. The modulation circuit 303 performs a predetermined modulation on the input data string and records it on the tape. In addition, the EC is synchronized with the frame reference signal 110.
In order for the C circuit 302 and the modulation circuit 303 to perform predetermined processing, they generate the necessary control signals. The control circuit 304 also controls the rotation of the rotary head and the tape feed speed control.

In the recording apparatus of this embodiment, the clock 107 is counted within one cycle period of the frame reference signal 110,
Number of clocks 107 of clocks 107 within one frame period
Is recorded on the tape together with the MPEG2 transport packet sequence.

The first embodiment of the reproducing apparatus for reproducing the tape recorded by the VTR of the first embodiment of the recording apparatus of the present invention will be described. FIG. 4 shows a block diagram of this embodiment. The reproducing apparatus according to the present embodiment has a reference signal generating circuit 403.
(Reference signal generation means), reproduction block 401 (reproduction means), reproduction clock generation circuit 404 (reproduction clock generation means), counter 405 (reproduction clock counting means), comparison circuit 406 (second reference signal generation means), phase error It is composed of a detection circuit 407 (phase error detection means) and a decoder 402 (input means).

A reproduction block 401 receives a reproduction digital signal, performs a predetermined demodulation process, corrects an error, and removes dummy data added during recording. The frame reference signal generation circuit 403 generates a frame reference signal 410 having the same cycle as that at the time of recording, and the reproduction block 401 reproduces from the reproduction digital signal tape in synchronization with the frame reference signal 410. The cycle of the frame reference signal 410 is 1.001 / 30 seconds, which is the same as the cycle of the frame reference signal 110 during recording. The MPEG2 transport packet sequence is output from the reproduction block 401 in synchronization with the reproduction clock 411 generated by the reproduction clock generation circuit 404.

The average data rate of only the MPEG2 transport packet train in the reproduced digital signal input to the reproduction block must be equal to the frequency of the reproduction clock 411. Therefore, in the present embodiment, they are made equal by the following method.

The reproduced clock obtained from the reproduced clock generation circuit 404 is input to the counter 405. Counter 4
A count value 409 reproduced from the tape is also input to 05. The counter 405 increments by 1 in synchronization with the reproduction clock 411. When the count value becomes equal to the reproduction count value 409, it is reset to 1. The count value of the counter 405 is input to the comparison circuit 406.
The comparator circuit 406 generates a second reference signal when the count value becomes 1, for example. The number of reproduced clocks reproduced is the number of clocks of the clock 107 in one cycle of the frame reference signal at the time of recording, and the cycle of the frame reference signal 410 obtained from the frame reference signal generation circuit 403 is the cycle of the frame reference signal 110 at the time of recording. Since it is equal to the cycle, if the frequency of the reproduction clock 404 obtained from the reproduction clock generation circuit is close to the clock 107 at the time of recording, the comparison circuit 4
The period of the second reference signal obtained from 06 is almost equal to the period of the frame reference signal 410. The phase error detection circuit 407 includes a frame reference signal 410 and a second reference signal 412.
, And outputs the phase error 413 to the recovered clock generation circuit 404. Regenerated clock generation circuit 404
On the basis of the phase error 43, the frequency of the reproduction clock 411 is increased or decreased so that the phase error becomes smaller. By performing such feedback control, the phase error between the frame reference signal 410 and the second reference signal 412 can always be kept at a small value. By increasing or decreasing the frequency of the reproduction clock 411 by such a method, the MPEG in the reproduction digital signal input to the reproduction block is reproduced.
The average reproduction rate of only two transport packet trains can be made equal to the frequency of the reproduction clock 411.

FIG. 5 shows an example of the structure of the reproduction block 401. The reproduction block 401 includes a demodulation circuit 501, an ECC circuit 502, a memory 503, and a control circuit 504. The control circuit 504 controls the rotation speed of the rotary head in synchronization with the frame reference signal 410, and also generates a predetermined control signal for the operation of the demodulation circuit 501 and the ECC circuit 502. The rotation speed of the rotary head is controlled by the control circuit 50.
Since it is synchronized with the frame reference signal by the control of 4, the reproduced digital signal reproduced from the tape is synchronized with the frame reference signal 410. The demodulation circuit 501 performs a predetermined demodulation process on the reproduced digital signal to perform ECC.
Output to the circuit 502. The data input to the ECC circuit 502 is input in the format shown in FIG.
The data transmission rate in FIG. 6B is about 25 Mbps which is the recording rate of the VTR.

In this data string, the dummy data 602 added at the time of recording is added to the MPEG2 transport packet 601. The ECC circuit 502 corrects the reproduction error, removes the added dummy data 602, and outputs the MPEG2 transport packet 601 to the memory 503. The format of the data input to the memory 503 is the format shown in FIG. FIG. 6C shows about 25M reproduced in synchronization with the frame reference signal 410.
The dummy data 602 is removed from the bps data string. However, the recovered clock generation circuit 404
The frequency of the reproduction clock 411 generated by the above is controlled so as to be equal to the average reproduction rate of the MPEG2 transport packet sequence of FIG. Therefore, although it is written in the memory 503 in synchronization with the frame reference signal 410, it is written in synchronization with the reproduction clock 411.
The data format of the MPEG2 transport packet sequence output from the reproduction block 401 can be set to the format of FIG.

MPE output from the reproduction block 401
The G2 transport packet sequence 408 has a frequency approximately equal to the clock 107 at the time of recording, which is approximately 19.3 Mbps.
Is input to the decoder 402 in synchronism with the reproduction clock 411. The decoder 402 restores the MPEG2 transport packet sequence 408 into a video signal and an audio signal.

The data format of the MPEG2 transport packet sequence obtained from the tuner 101 at the time of recording, which is the subject of the present invention, can be made equal to the data format of the MPEG2 transport packet sequence input by the decoder at the time of reproduction. Therefore, in a recording / reproducing device in which the recording device and the reproducing device are installed in the same device, the decoder 402 is the same when inputting directly from the tuner 101 to the decoder 402 and when inputting from the reproduction block 401 during reproduction. It only has to correspond to the data format.

A second embodiment of the reproducing apparatus for reproducing the tape recorded by the VTR of the first embodiment of the recording apparatus of the present invention will be described. The reproducing apparatus of this embodiment includes a reference signal generating circuit 701 (reference signal generating means), a reproducing block 401 (reproducing means), a reproduced clock generating circuit 702 (reproduced clock generating means), a counter 405 (reproduced clock counting means), and a comparison. Circuit 406 (second reference signal generation means), phase error detection circuit 407 (phase error detection means),
It is composed of a decoder 402 (input means).

The present embodiment is different from the first embodiment relating to the reproducing apparatus in that the reproducing clock generating circuit 702, which is the reproducing clock generating means, is almost the same as the clock 107 at the time of recording at a constant frequency without external control. The reproduction clock 704 is output at the same frequency, and the frame reference signal generation circuit 701 that is the reference signal generation means outputs the phase error 413 output from the phase error detection circuit 407, whereby the frame reference signal generation circuit 701 and the second reference signal 412 are output. That is, the period of the frame reference signal 703 is increased or decreased so as to reduce the phase error. Even with such a configuration, the phase error between the frame reference signal 703 and the second reference signal 412 can be constantly reduced. Therefore, the reproduction clock 70 whose average reproduction rate of only the MPEG2 transport packet sequence included in the reproduced digital signal has a constant frequency.
4 and the data format of the MPEG2 transport packet sequence 408 output from the memory 503 of the reproduction block 401 can be the same as that of FIG. 6A. Therefore, also in this embodiment, as in the first embodiment, the data format of the MPEG2 transport packet sequence obtained from the tuner 101 at the time of recording and the data format of the MPEG2 transport packet sequence input by the decoder at the time of reproduction can be made equal. it can.

In the present embodiment, the recovered clock generating circuit 7
If a high-precision oscillator such as a crystal oscillator circuit is used as 02, the reproduction clock 704 having a predetermined frequency can always be supplied to the decoder 402 regardless of the accuracy of the frame reference signal of the recording / reproducing apparatus.

Therefore, even in the reproducing apparatus of the present embodiment, the data format of the MPEG2 transport packet sequence obtained from the tuner 101 at the time of recording, which is the subject of the present invention, and the MPEG2 transport packet sequence input by the decoder at the time of reproduction. The data formats can be equal. Therefore, in a recording / reproducing device in which the recording device and the reproducing device are installed in the same device, the decoder 402 is the same when inputting directly from the tuner 101 to the decoder 402 and when inputting from the reproduction block 401 during reproduction. It only has to correspond to the data format.

Next, a second embodiment of the recording apparatus will be described. FIG. 8 shows a block diagram of a second embodiment of the recording apparatus of the present invention. The recording apparatus of this embodiment includes a tuner 101 (output means), a recording block 102 (recording means), a count block 111 (counting means), a frame reference signal generation circuit 103 (reference signal generation means), and a data selection circuit 801 (data selection). Means).

In the first embodiment of the recording apparatus, the data rate of the MPEG2 transport packet train output from the tuner 101 is smaller than the recordable recording rate of the recording block 102. However, it is possible that the data rate output from the tuner 101 is higher than the recordable rate because a plurality of programs are multiplexed. In the first embodiment of the recording apparatus, the recording block 102 records because the input data rate is higher than the recording rate even if the user only needs to record one of the multiplexed programs. Can not do it.

Therefore, in this embodiment, the data selection circuit 801 is added to the structure of the first embodiment relating to the recording apparatus. It is assumed that the data rate output from the tuner 101 in this embodiment is about 38.6 Mbps, and the recording rate of the recording block 102 is about 25 Mbps. FIG. 9 (A)
An example of the MPEG2 transport packet sequence 802 output from the tuner 101 is shown in FIG. The example of FIG. 9A is a transport packet sequence for video data and audio data of program 1 and program 2, respectively. The video 1 transport packet 901 is the video transport packet of the program 1, and the audio 1 transport packet 9
02 is an audio transport packet of program 1,
The video 2 transport packet 903 is a video transport packet of program 2, and the audio 2 transport packet 904 is a audio transport packet of program 2. These transport packet trains have a transmission rate of about 38.6 Mbps and a tuner 10
Output from 1 without gap. The recording block 102 cannot record all these data. In this embodiment, the data selection circuit 801 selects the transport packet corresponding to the program that the user wants to record. The packet sequence 803 after selection is shown in FIG. FIG. 9B
The example is when program 1 is selected. The data rate of only program 1 is about 2 which is the recording rate of the recording block 102.
If it is smaller than 5 Mbps, the recording block 102 can record. Memory 30 inside recording block 102
1, the data selection circuit 801 is synchronized with the clock 107.
Only write transport packets selected by. A transport packet is read from the memory 301 in synchronization with the frame reference signal 110, and dummy data is added to complement the difference between the average data rate of the selected transport packet sequence 802 and the recording rate of about 25 Mbps. Will be recorded. The clock counted by the count block 111 is a clock 107 having a frequency of about 38.6 MHz, which counts the number of clocks in one frame period of the frame reference signal generated by the frame reference signal generation circuit 103, and the number of clocks is also the transformer. Recorded with the port packet sequence.

Next, the VT of the second embodiment relating to the recording apparatus.
A first embodiment of the reproducing apparatus for reproducing the tape recorded in R will be described. FIG. 10 shows an example of a block diagram of the reproducing apparatus of this embodiment. The reproducing apparatus of this embodiment includes a reference signal generating circuit 403 (reference signal generating means) and a reproducing block 4.
01 (reproduction means), reproduction clock generation circuit 404 (reproduction clock generation means), counter 405 (reproduction clock counting means), comparison circuit 406 (second reference signal generation means),
Phase error detection circuit 407 (phase error detection means), decoder 402 (input means), and pseudo packet generation circuit 1
001 (pseudo data generating means) and a multiplexing circuit 1002 (multiplexing means).

The present embodiment has a structure in which a pseudo packet generating circuit 1001 and a multiplexing circuit 1002 are added to the reproducing apparatus shown in FIG. The frame reference signal generation circuit 403 generates the frame reference signal 410 at the same cycle as when recording.
The reproduction block 401 reproduces the reproduction digital signal from the tape in synchronization with the frame reference signal 410. The reproduction clock generation circuit 404 generates the reproduction clock 411 at a frequency of about 38.6 MHz, which is the same as the recording clock 107. The counter 405 counts the reproduced clock 411. The count value 409 reproduced from the tape is also input to the counter 405. The counter 405 increments by 1 in synchronization with the reproduction clock 411. When the count value becomes equal to the reproduction count value 409, it is reset to 1. The count value of the counter 405 is the comparison circuit 40.
6 is input. The comparison circuit 406 generates the second reference signal when the count value becomes 1, for example. The phase error detection circuit 407 includes a frame reference signal 410 and a second reference signal 41.
The phase error of 2 is detected. Regenerated clock generation circuit 404
Input the phase error 413 and input the frame reference signal 410
Then, the frequency of the reproduction clock 411 is increased or decreased so as to reduce the phase error of the second reference signal 412. This allows
The frequency of the reproduction clock 411 is the transport packet reproduced from the tape and the data selection circuit 80 during recording.
It is equal to the sum of the data rates of the transport packets removed by 1.

The data format reproduced by the reproduction block 401 is output in the format shown in FIG. When input to the decoder 402 in this state, transport packets are input discretely, so that the data format is different from that when input directly from the tuner 101. That is, the decoder 402 has to cope with both the case where the transport packets are continuously input as in the case of being input from the tuner 101 and the case where the transport packets are discretely input as in this example.

In this embodiment, the pseudo packet generation circuit 100
1 generates a pseudo transport packet sequence 1004 corresponding to the transport packet removed by the data selection circuit 801 during recording. The pseudo transport packet sequence 1004 is a transport packet sequence conforming to MPEG2. The multiplexing circuit 1002 multiplexes the reproduced transport packet sequence 1003 and the pseudo transport packet sequence 1004 and outputs them to the decoder 402. FIG. 11 shows an example of a multiplexed transport packet sequence.
Shown in FIG. 11A shows a transport packet sequence 1003 before multiplexing. Program 1 from playback block 401
Reproduced video 1 transport packet 1
Each of the transport packets 101 and the voice 1 transport packet 1102 is discretely output. The multiplexing circuit 1002 multiplexes the pseudo transport packet 1103 in the gap of the transport packet sequence 1003.
The multiplexed transport packet is reproduced clock 41.
It is input to the decoder in synchronization with 1 without a gap. The decoder 402 decodes the video 1 transport packet and the audio 1 transport packet of the program 1, and restores them into a video signal and an audio signal.

According to the recording apparatus of the second embodiment and the reproducing apparatus of the present embodiment relating to the recording apparatus, an arbitrary MPEG2 transport packet is selected and recorded and reproduced even when input at a data rate higher than the recording rate. By complementing the transport packets that were not selected at some time and inputting them to the decoder, the data format when inputting directly from the tuner to the decoder can be made the same as the data format that is input from the playback block during playback. Need only support one data format. Also, by making the complementary pseudo transport packet a packet conforming to MPEG2, the decoder does not malfunction.

Next, the VT of the second embodiment relating to the recording apparatus.
A second embodiment of the reproducing apparatus for reproducing the tape recorded in R will be described. FIG. 12 shows an example of a block diagram of the reproducing apparatus of this embodiment. The reproducing apparatus according to this embodiment includes a frame reference signal generating circuit 1203 (reference signal generating means), a reproducing block 401 (reproducing means), and a reproduced clock generating circuit 1.
202 (regenerated clock generation means), counter 405 (regenerated clock counting means), comparison circuit 406 (second reference signal generation means), phase error detection circuit 407 (phase error detection means), decoder 402 (input means), and pseudo. It is composed of a packet generation circuit 1001 (pseudo data generation means) and a multiplexing circuit 1002 (multiplexing means).

The frame reference signal generation circuit 1201 generates the frame reference signal 1203 at the same cycle as when recording.
Further, the frame reference signal generation circuit 1201 has a function of increasing or decreasing the cycle of the frame reference signal 1203 due to the phase error 413. The reproducing block 401 reproduces the reproduced digital signal from the tape in synchronization with the frame reference signal 1203.

The reproduction clock generation circuit 1202 generates the reproduction clock 1204 at the same frequency of about 38.6 MHz as the clock 107 at the time of recording. Unlike the first embodiment, the regenerated clock generator circuit regenerates the regenerated clock 12 at a constant frequency.
04 is generated. The counter 405 is the reproduction clock 120.
Count 4. The count value 409 reproduced from the tape is also input to the counter 405. Counter 4
05 is incremented by 1 in synchronization with the reproduction clock 411. When the count value becomes equal to the reproduction count value 409, it is reset to 1. The count value of the counter 405 is input to the comparison circuit 406. The comparison circuit 406 generates the second reference signal when the count value becomes 1, for example.
The phase error detection circuit 407 detects the phase error between the frame reference signal 1203 and the second reference signal 412. The frame reference signal generation circuit 1201 inputs the phase error 413 and increases or decreases the cycle of the frame reference signal 1203 so as to reduce the phase error between the frame reference signal 1203 and the second reference signal 412. As a result, the frequency of the reproduction clock 1204 becomes equal to the sum of the data rates of the transport packet reproduced from the tape and the transport packet removed by the data selection circuit 801 during recording.

The difference between this embodiment and the reproducing apparatus of the first embodiment shown in FIG. 10 is that the reproducing apparatus shown in FIG. 10 increases or decreases the frequency of the reproducing clock 411 so that the phase error becomes smaller. The reproduction clock 1204 is used in this embodiment.
That is, the reproduction data rate is increased / decreased by keeping the frequency constant and increasing / decreasing the cycle of the frame reference signal.

Also in this embodiment, as in the first embodiment, the frequency of the reproduction clock 1204 is the transport packet reproduced from the tape and the data selection circuit 8 at the time of recording.
Equal to the data rate of both transport packets dropped by 01. Therefore, even if this embodiment is used, the same effect as that of the first embodiment can be obtained.

According to the recording device and the reproducing device of the present invention, it is possible to record and reproduce a data string in which the data amount is different in each frame of the video signal.

In the description of the embodiments of the present invention, the device for receiving the broadcast wave by the tuner inside the recording device and recording the MPEG2 transport packet has been described as an example, but the output means is not from the tuner but from another device. Even when a circuit for inputting an MPEG2 transport packet as a digital signal and outputting it internally is equipped, the same effect can be obtained by using the recording device of the present invention. Further, in the description of the embodiments of the present invention, a device for decoding an MPEG2 transport packet and restoring a video signal and an audio signal by a decoder inside the playback device has been described as an example, but the device as an input means is not a decoder but another device. Even when equipped with a circuit that outputs MPEG2 transport packets as digital signals,
The same effect can be obtained by using the reproducing apparatus of the present invention.

In the description of the present invention, the data rates of the MPEG2 transport packet train obtained from the output means (tuner) are about 19.3 Mbps and about 38.6 Mbps.
Although the case of ps has been described as an example, it is possible to record / reproduce MPEG2 transport packet sequences of other data rates using the present invention.

Although the MPEG2 transport packet sequence has been described as an example in the description of the present invention, a data sequence compressed by another method can also be recorded and reproduced by using the recording device and the reproducing device of the present invention.

The period of the frame reference signal in the recording device and the reproducing device of the present invention is 1.001 / 30 seconds, but this period is just a period for synchronizing the VTR. Therefore, the cycle of the frame reference signal may be another cycle as long as the VTR can be synchronized. For example, 1/25 seconds, about 1/300 seconds, etc. can be considered.

The clock counting means in the present invention counts the number of bits of the MPEG2 transport packet within one cycle period of the frame reference signal as the number of clocks from the output means (tuner), but counts the number of bytes or the number of transport packets. However, a method of recording on tape is also conceivable.

[0062]

As described above, according to the reproducing apparatus (Claims 2 and 5 and 6) for recording with the recorder (recording apparatus according to claim 1) of the first embodiment of the recording apparatus and reproducing the tape. Since the data format of the data output from the tuner of the recording device and the data format of the data reproduced from the reproduction block during reproduction can be the same,
The decoder of the reproducing apparatus only needs to support one data format, and the circuit scale of the decoder can be reduced. Further, according to the reproducing apparatus (Claims 4 and 5 and 6) for recording with the recorder (recording apparatus of Claim 3) of the second embodiment relating to the recording apparatus and reproducing the tape, the recording block can be recorded. Even if the data has a data rate higher than the appropriate recording rate, it is possible to record and reproduce by selecting only the necessary data. Further, at the time of reproduction, the data format of the data output from the tuner of the recording device is made the same as the data format of the data reproduced from the reproduction block by complementing the data removed at the time of recording with the pseudo data. Therefore, the decoder of the reproducing apparatus only needs to support one data format, and the circuit scale of the decoder can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a recording apparatus of the present invention.

FIG. 2 is an explanatory diagram of an operation of a count block of the recording apparatus of the present invention.

FIG. 3 is a block diagram showing a configuration example of a recording block in the recording apparatus of the present invention.

FIG. 4 is a block diagram showing a first embodiment of a reproducing apparatus of the present invention corresponding to the recording apparatus of the first embodiment.

FIG. 5 is a block diagram showing a configuration example of a playback block in the playback device of the present invention.

FIG. 6 is an explanatory diagram of a data format inside a recording device and a reproducing device according to an embodiment of the present invention.

FIG. 7 is a block diagram showing a second embodiment of the reproducing apparatus of the present invention corresponding to the recording apparatus of the first embodiment.

FIG. 8 is a block diagram showing a second embodiment of the recording apparatus of the present invention.

FIG. 9 is an explanatory diagram of a data format inside a recording device and a reproducing device corresponding to the recording device of the second embodiment.

FIG. 10 is a block diagram showing the reproducing apparatus of the first embodiment corresponding to the recording apparatus of the second embodiment.

FIG. 11 is an explanatory diagram of a data format inside a reproducing device corresponding to the recording device of the second embodiment.

FIG. 12 is a block diagram showing a reproducing apparatus of the second embodiment corresponding to the recording apparatus of the second embodiment.

[Explanation of symbols]

101 tuner 102 recording block 103, 403, 701, 1201 frame reference signal generation circuit 104, 405 counter 105 register 106, 408 MPEG2 transport packet sequence 401 reproduction block 402 decoder 404, 702, 1202 reproduction clock generation circuit 406 comparison circuit 407 phase Error detection circuit 801 Data selection circuit 1001 Pseudo packet generation circuit 1002 Multiplexing circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H04N 5/91 5/92 (72) Inventor Hidetoshi Takeda 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Within the corporation

Claims (6)

[Claims] 1. A data output means for outputting compressed video data and audio data in synchronism with a clock having a predetermined frequency, a reference signal generating means for generating a reference signal at a predetermined cycle, and the reference signal generation. Clock counting means for counting the clock within the period of the reference signal generated by the means, and the count value counted by the counting means and the video data and audio data on the recording medium in synchronization with the reference signal. A recording apparatus comprising: a recording unit for recording. 2. A reference signal generating means for generating a reference signal at a predetermined cycle, and a reproducing means for reproducing video data and audio data and a count value recorded on a recording medium in synchronization with the reference signal. A reproduction clock generating means for generating a reproduction clock having a predetermined frequency; a reproduction clock counting means for counting the reproduction clock by the reproduced count value; and a second reference when the reproduction clock counting means reaches a predetermined value. Second reference signal generating means for generating a signal, phase error detecting means for detecting a phase error between the reference signal and the second reference signal, and the video data reproduced by the reproducing means in synchronization with the reproduction clock. And a input device for inputting audio data. 3. Data output means for outputting a plurality of compressed video data and audio data in synchronization with a clock having a predetermined frequency, and data for selecting arbitrary data from the plurality of video data and audio data. Selecting means, reference signal generating means for generating a reference signal at a predetermined cycle, clock counting means for counting the clock within the cycle period of the reference signal generated by the reference signal generating means, and the counting means A recording device comprising: a recording unit that records the counted value and the selection data selected by the selection unit on a recording medium in synchronization with the reference signal. 4. A reference signal generating means for generating a reference signal at a predetermined cycle, a reproducing means for reproducing the selection data and the count value recorded on a recording medium in synchronization with the reference signal, and a predetermined means. A regenerated clock generating means for generating a regenerated clock of a frequency, a regenerated clock counting means for counting the regenerated clock by the regenerated count value, and a second reference signal when the regenerated clock counting means reaches a predetermined value. Second reference signal generating means, phase error detecting means for detecting a phase error between the reference signal and the second reference signal, pseudo data generating means for generating pseudo data, and the selection reproduced by the reproducing means. A multiplexing means for multiplexing data and the pseudo data; and an input means for inputting the selection data and the pseudo data in synchronization with the reproduction clock. Reproducing apparatus, characterized in that the. 5. The reproducing apparatus according to claim 2, wherein the reproduced clock generating means changes the frequency of the reproduced clock according to the phase error obtained by the phase error detecting means. 6. The reproducing apparatus according to claim 2 or 4, wherein the reference signal generating means changes the frequency of the reference signal according to the phase error obtained by the phase error detecting means.