JP4462237B2 - Digital signal processor - Google Patents

Description

The present invention relates to an apparatus for recording signals of different signal formats, and more particularly to a digital signal processing apparatus for recording a compressed signal.

A recording / reproducing apparatus that transmits a bit-compressed signal and records the received compressed signal as it is is described in, for example, Japanese Patent Laid-Open No. 4-79588. As the advanced compression technique, for example, a method called MPEG (Moving Picture Expert Grope) is known. The MPEG method is a method for transmitting a differential signal with respect to a reference frame using correlation between frames. For this reason, the amount of data (number of bits) for each frame is different.

As a method for transmitting a data signal compressed by the MPEG method, a transport stream and a program stream are further known. The transport stream is mainly used when digitally broadcasting a signal compressed by the MPEG method. On the other hand, the program stream is used when a signal compressed by the MPEG method is recorded and reproduced on a storage device such as an optical disk.

However, a method for recording and reproducing a program stream signal reproduced by an optical disk, a hard disk device or the like by a video tape recorder has not been disclosed yet.

An object of the present invention is to provide an apparatus capable of decompressing a signal having a signal format different from that of a signal compressed by a variable rate compression method represented by MPEG. Furthermore, when a signal compressed by a variable rate compression method represented by MPEG or the like is reproduced from a storage device capable of controlling the reproduction speed such as a disk device, an apparatus capable of efficiently recording with a video tape recorder is provided. There is. Furthermore, another object of the present invention is to provide an apparatus capable of efficiently recording a compressed signal reproduced by a VTR or a compressed signal broadcast digitally on a hard disk, an optical disk or the like.

According to the present invention, in an apparatus for decompressing a transport stream including a compressed signal obtained by compressing a video signal, a reference signal synchronized with the video signal, and a program stream including the compressed signal, the first synchronized with the video signal based on the reference signal. A clock signal generating means for generating one clock signal; a clock signal generating means for generating a stable second clock signal; a switching means for switching between the first clock signal and the second clock signal; Expansion means for expanding based on the clock signal output from the switching means, and when expanding the compressed signal included in the transport stream, the first clock signal is used to expand the compressed signal included in the program stream. In this case, the second clock signal is used.

Further, in a signal processing apparatus for recording a variable rate program stream compressed signal reproduced from a disk-shaped medium on a tape-shaped medium, clock signal generating means for generating a stable clock signal, and reproduced variable-rate compressed signal The decompression means for decompressing the program stream using the stable clock signal, the conversion means for converting the program stream into a transport stream, and the relative time information of the arrival time of the packet signal in the packet signal constituting the transport stream And a transport stream is recorded on the tape-like medium while the reproduced variable rate compressed signal is decompressed by the decompression means.

Furthermore, in a device for inputting a transport stream including a compressed signal obtained by compressing a video signal and a reference signal synchronized therewith, and recording the compressed signal on a disk-shaped medium, a clock signal synchronized with the video signal based on the reference signal A clock signal generating means for generating a data stream, a converting means for converting a transport stream into a program stream, and a buffer means for temporarily storing the program stream, so that an output signal of the buffer means is recorded on a disk-like medium. I made it.

According to the present invention, for example, when a transport stream that is a compressed digital broadcast reception signal or a compressed playback signal of a bitstream recording / playback apparatus is decompressed, it is based on a reference signal included in the transport stream. A clock signal is generated, and the compressed signal is expanded using the clock signal. For example, when a program stream signal that is a compressed signal reproduced from a disk-shaped medium is expanded, the compressed signal is generated using a stable clock signal. Since the decompression is performed, both the transport stream and the program stream can be decompressed without causing excess or deficiency of data.

Furthermore, since the compressed signal reproduced from the storage device capable of controlling the reproduction speed such as a disk device is reproduced while decompressing the signal compressed by the variable rate compression method, it can be recorded on a tape-like medium. Data can be played back without excess or deficiency.

Furthermore, since the transport stream reproduced from the tape-like medium is converted into a program stream and the recording rate of the disk-like medium is set to be higher than the average reproduction rate, it is reproduced from the tape-like medium. The compressed signal can be efficiently recorded on the disk-shaped medium.

An embodiment of the present invention will be described with reference to FIG. In FIG. 1, 10 is a storage device,
20 is an interface circuit, 30 is a memory, 40 is a decoder, 50 is an interface circuit, 60 is a receiver, 70 is a bit stream recording / reproducing device, 80 is a bus,
Reference numeral 90 is an antenna, 100 system controller, and 110 is a digital signal processing device. FIG. 2 shows an embodiment showing details of the decoder 40 and the interface circuit 50. In FIG. 2, 410 is a buffer circuit, 420 is a decompression circuit, 430 is a display control circuit, 440 is a crystal oscillator, 450 and 460 are switching circuits, 51
0 is a tuner circuit, 520 is a demodulation circuit, 530 is an error correction circuit, 540 is a selection circuit, 550 is a clock generation circuit, 560 is a conversion circuit between a program stream and a transport stream, 570 is a time stamp addition / removal circuit, 580 It is a switching circuit.

In this embodiment, it is assumed that the storage device 10 is, for example, an optical disc drive device and can reproduce at least a video signal and an audio signal compressed by the MPEG system as a program stream. The storage device 10 may have a recording function for video signals and audio signals compressed by MPEG. Furthermore, not only an optical disk drive device but also a hard disk drive (magnetic disk drive) device may be used.

First, the signal reproduced from the storage device 10 is decompressed by the decoder 40 and received by the receiver 60.
The case of viewing at will be explained. The signal reproduced from the storage device 10 is input to the interface circuit 20. The interface circuit 20 inputs the regenerated signal to a predetermined packet length and inputs it to the memory 30 via the bus 80. The decoder 40 includes at least a buffer circuit 410 and a crystal oscillator 440. In this case, the switching circuit 450 is connected to the terminal A and the switching circuit 460 is connected to the terminal B, and the oscillation clock of the crystal oscillator 440 is used as a reference clock. As an expansion circuit 420
To decompress the compressed signal. In decompression, the signal from the memory 30 is stored in the buffer circuit 410 of the decoder 40 via the bus 80 as necessary, and the buffer circuit 410
The decompression circuit 420 decompresses the signal from. Buffer circuit 4 in the decoder 40
When the amount of data stored in 10 exceeds a predetermined value, the input of data from the memory 30 is temporarily stopped. Conversely, when the amount of data in the buffer circuit 410 falls below a predetermined value, the memory Data is input from 30. By doing so, the data from the storage device 10 can be decompressed without excess or deficiency based on the clock signal from the crystal oscillator 440. With the above operation, the system controller 100 performs control of the bus 80, writing to and reading from the memory 30 and the buffer circuit 410, switching control of the switching circuits 450 and 460, and the like.

The video signal and audio signal expanded as described above are display-controlled by the display control circuit 430 and input to the receiver 60 so that the user can appreciate them.

Next, a case where the program is viewed while the signal received by the antenna 90 is expanded by the decoder 40 will be described. Although not shown in FIG. 1, the program includes at least a video signal and an audio signal, and the program is compressed and transmitted from a broadcasting station (
Broadcasting) and receiving it by the antenna 90. Further, it is assumed that a so-called transport stream of the MPEG system is transmitted for transmission.

A signal received by the antenna 90 is input to the interface circuit 50. The interface circuit 50 includes a tuner circuit 510 and a demodulation circuit 520 as shown in FIG.
Error correction circuit 530 and the like. The tuner circuit 510 adjusts the reception band so as to receive a signal including a program to be viewed. The demodulator circuit 520 demodulates the received signal, and the error correction circuit 530 corrects errors that occur during transmission. The error-corrected signal is a so-called transport stream signal.
The transport stream signal error-corrected by the error correction circuit 530 can include a plurality of programs. The video signal, audio signal, program guide information, conditional access information, etc. of the program to be viewed as necessary. Are selected by the selection circuit 540. The interface circuit 50 generates a reference clock signal based on clock reference information called a program clock reference (PCR) or a system clock reference (SCR) that is required to be added to the transport stream. A clock signal generation circuit 550 is provided. Since the above reference information is synchronized with the program selected for reception, by inputting the packet signal of the program selected by the selection circuit 540 to the clock generation circuit 550, the clock signal synchronized with the program selected for reception is obtained. Obtainable. A clock signal synchronized with the reception-selected program generated by the clock signal generation circuit 550 is input to the decoder 40. In this case, the switching circuit 580 is at terminal A, the switching circuit 460 is at terminal B, and the switching circuit 450
Is connected to terminal B.

The transport stream packet of the program selected by the selection circuit 540 is converted into a program stream packet by the conversion circuit 560 and input to the decoder 40 via the bus 80 in the same packet signal format as that reproduced from the storage device 10.

In the decoder 40, the switching circuit 450 is connected to the terminal B, the switching circuit 460 is connected to the terminal B, the clock signal input from the interface circuit 50 is selected, and the video signal input from the bus 80 via the buffer circuit 410, The audio signal is expanded by the expansion circuit 430. Since the clock signal used here is synchronized with the selected program, even if the video signal and audio signal packet of the program are input unilaterally from the antenna 90, there will be no excess or deficiency of data. The demodulated video signal and audio signal are display-controlled by the display control circuit 430 and input to the receiver 60.

Next, a case where a signal input from the antenna 90 is recorded by the bit stream recording / reproducing apparatus 70 will be described. Also in this case, the received program is expanded by the same operation as described above, and can be viewed on the receiver 60. In the interface circuit 50, relative time information (time stamp) indicating the arrival time of the packet is added to each packet of the bit stream of the program selected by the selection circuit 540 by the time stamp addition / removal circuit 570. The packet to which the time information is added is input to the bit stream recording / reproducing apparatus 70. The bit stream recording / reproducing apparatus 70 records the packets to which the time stamp is added as a lump on the recording medium. The bit stream recording / reproducing apparatus is, for example, a video tape recorder.

At the time of reproduction, a packet signal to which time information is added is reproduced from the recording medium of the bitstream recording / reproducing apparatus 70. The reproduced packet signal is output from the bit stream recording / reproducing apparatus 70 with the same packet interval as when the packet interval is received according to the added time information, and is input to the interface circuit 50. The signal input from the bit stream recording / reproducing device 70 to the interface circuit 50 during reproduction is the same signal as the signal input from the interface circuit 50 to the bit stream recording / reproducing device 70 during recording, and the packet interval is the same. Accordingly, the time stamp addition / removal circuit 570 removes the time stamp and uses the clock reference information included in this bit stream to generate the clock generation circuit 55.
A clock signal synchronized with the program reproduced at 0 can be obtained. After that
By operating in the same manner as when the signal input from the antenna 90 is expanded and viewed, the signal from the bitstream recording / reproducing device 70 can be expanded without excess and shortage and can be viewed on the receiver 60. .

Next, the operation in the case where the signal from the storage device 10 is recorded in the bit stream recording / reproducing device 70 will be described. In this case, the program stream signal reproduced from the storage device 10 is transmitted to the interface circuit 20 and the bus 80 as described above.
Is input to the memory 30. Further, it is input from the memory 30 to the decoder 40 via the bus 80 and decompressed. At the same time, the program stream signal from the memory 30 is input to the interface circuit 50. When the signal from the storage device 10 is recorded in the bit stream recording / reproducing device 70, the clock signal is input from the decoder 40 to the interface circuit 50. In this case, the switching circuit 450 is connected to the terminal A, the switching circuit 460 is connected to the terminal A, and the switching circuit 580 is connected to the terminal B. In the interface circuit 50, the program stream input from the bus 80 is converted into a transport stream by the conversion circuit 560. The converted transport stream is similar to the case where the signal received from the antenna 90 is recorded.
A time stamp is added by a time stamp adding circuit 570 and input to the bit stream recording / reproducing apparatus 70. As described above, the reproduction signal from the storage device 10 can be recorded in the bit stream recording / reproducing device 70.

The operation when reproducing the signal from the storage device 10 recorded as described above is the same as the operation when reproducing the signal when the signal from the antenna 90 is recorded.

Next, when the storage device 10 has a recording function, a signal received by the antenna 90 or a program reproduced by the bitstream recording / reproduction device 70 is stored in the storage device 10.
An example of the case where recording is performed will be described. Also in this case, the program received by the antenna 90 or the program reproduced by the bit stream recording / reproducing device 70 can be recorded on the storage device 10 while being viewed by the receiver 60 as described above. As for the program received by the antenna 90, the transport stream packet signal of the program selected by the selection circuit 540 is input to the conversion circuit 560. Similarly, when reproduced by the bitstream recording / reproducing apparatus 70, the transport stream packet signal from which the time stamp has been removed is converted into the conversion circuit 560.
Is input. In the conversion circuit 560, the transport stream packet is converted into a program stream packet. The converted program stream packet is temporarily stored in the memory 30 via the bus 80. The program stream packet temporarily stored in the memory 30 is sent to the interface circuit 20 via the bus 80.
Is input. The interface circuit 20 has a buffer circuit (not shown),
After a predetermined amount of data is accumulated in the buffer circuit, the data is written into the storage device 10. The average write data rate of the storage device 10 needs to be greater than the average data rate of the program being received or reproduced. That is, the interface circuit 2
When a predetermined amount of data is not stored in the buffer circuit in 0, the storage device 10
Stops writing and writes data to the storage device 10 at a high speed following the portion already recorded when a predetermined amount of data is stored.

With the above operation, the received or reproduced signal can be efficiently written in the storage device 10.

In the above description, the playback signal from the storage device 10 and the bit stream recording / playback device 70 has been described as a program. However, the present invention is not limited to a program consisting of a video signal and an audio signal. It may be a signal.

In the embodiment shown in FIG. 1 and FIG. 2, for example, the antenna 90 is shown by using a diagram such as a parabolic antenna that receives satellite broadcasting. However, the antenna 90 is not limited to this, and may be an antenna that receives terrestrial waves. Furthermore, the present invention can be applied to a case where a signal is input through an optical cable, a coaxial cable, or a telephone line.

  Next, an embodiment related to a technique related to time stamp addition will be described.

FIG. 3 is a schematic diagram showing an example of a signal received by the antenna 90 in the embodiment shown in FIG. In the embodiment shown in FIG. 3, a case where four programs are transmitted through one transmission channel is shown. Also, the transmission channel is shown for n transmission channels (1) to (n). In FIG. 3, V1, V2, V3 and V4 are video signals of four programs, A1, A2, A3 and A4 are audio signals of four programs, PG is a signal indicating program guide information, and VECM and AECM are respectively It is a control signal indicating a viewing right relationship. And
Each represents a signal of one packet.

The above four programs generally have different transmission rates. In addition, when viewed instantaneously, the amount of data increases or decreases. In order to control this efficiently, each piece of information is packetized and time-division multiplexed as shown in FIG. The details of the signal in the packet shall conform to the MPEG transmission standard.
Although not shown in detail in the schematic diagram shown in FIG. 3, a signal in each packet is encrypted as necessary, and header information such as an error correction code and a synchronization signal is added.

In the embodiment shown in FIGS. 1 and 2, the signals shown in FIGS. 3 (1)... (N) are input from the antenna 90, and the tuner 510 selects one of the transmission channel signals. Here, it is assumed that FIG. 3A is selected. The selected signal shown in FIG. 3A is demodulated by the demodulation circuit 520, error-corrected by the error correction circuit 530, and input to the selection circuit 540. In the selection circuit 540, it is assumed that the program indicated by time 1 is selected from the four programs time-division multiplexed. At this time, the program guide information PG and the viewing right control signals VECM and AECM are separated and output simultaneously with the video signal V1 and the audio signal A1. FIG. 4 (2) shows a signal obtained by dividing the program. 4 (1) is the same as FIG. 3 (1).
Is rewritten.

In the embodiment shown in FIG. 2, the case where the signal from the tuner 510 is expanded by the expansion circuit 420 will be described first. As described above, the program selected signal shown in FIG. 4B is converted into a program stream by the conversion circuit 560 and input to the decompression circuit 420 via the bus 80 and the buffer circuit 410. In the case of an encrypted signal, although not particularly shown, it is decrypted by an encryption / decryption circuit in the decompression circuit 420. This is performed based on the viewing right control signals VECM and AECM signals shown in FIG. That is, if the subscribing household has the right to view the currently selected program, the encryption is decrypted, and if there is no viewing right, the encryption is not decrypted, and it is clearly stated that there is no right to view or the viewing Information indicating how to obtain the right is output to the receiver 60. The output of this information is what is called OSD.

It should be noted that the decryption of the cipher is error-corrected by the error correction circuit 530 and then selected by the selection circuit 540.
Can be done before the program is selected. Even in that case, the present invention can be similarly applied.

The decrypted signal is decompressed by the decompression circuit 420 according to, for example, the MPEG standard. MP
When decompressing a signal compressed with the EG standard, it is necessary to synchronize the transmitted signal with the data to be decoded. For example, when the transmitted signal and the decompressed data are not synchronized, and the decompression speed is faster than the transmission speed, the data is insufficient and cannot be decompressed. For this reason, in the MPEG standard, as described above, clock reference information called PCR or SCR is added to a packet. At the time of decompression, the clock generation circuit 550 restores the decompression clock signal based on this clock reference information, and inputs it to the decompression circuit 420 to perform decompression.

In order to record the selected signal shown in FIG. 4 (2) in the bit stream recording / reproducing apparatus 70, as described above, a device that can reproduce while maintaining the time interval of the input packet with the time stamp added thereto is provided. There is a need to.

As shown in FIG. 4B, there are portions where packets exist continuously, and there are portions where there are intervals of several packets. In order to record in the bit stream recording / reproducing apparatus 70 while maintaining the time interval of this signal, recording at a rate higher than the rate of the input signal is required. As shown in FIG. 4 (2), there is a period in which the packet is not sent. Therefore, if the packet can be packed and recorded and returned to the original time interval at the time of reproduction, the recording rate is made smaller than the input signal rate. it can. FIG. 4 (3) shows a packet packed and recorded at the time of recording, and is output from the time stamp addition / removal circuit 570 to the bit stream recording / reproducing apparatus 70 so that the original time interval can be restored at the time of reproduction. Signals are shown.

The time stamp addition / removal circuit 570 adds information (time stamp) indicating the time when a packet arrives to the input signal as header information. Information other than the time stamp may be further added as necessary as the header information. Further, in order to add header information such as a time stamp to the input signal of the time stamp addition / removal circuit 570 shown in FIG. 4B, it is necessary to increase the packet transmission rate. FIG. 4 (3) schematically shows this. That is, FIG.
In contrast to the transmission time of one packet shown in (2), one packet is transmitted in a short time in (3).

FIG. 5 shows an embodiment of a circuit for adding a time stamp. Reference numeral 600 denotes a clock signal input terminal for counting time stamps, reference numeral 601 denotes a packet signal input terminal shown in FIG. 4 (2), reference numeral 602 denotes a signal output terminal to which a time stamp is added, 61
0 is a counting circuit, 611 is a latch circuit, 620 is a memory, 630 is a packet head detection circuit, 631 is a control circuit for the memory, 640 is a multiplexing circuit, and 650 is a delay circuit.

The packet signal shown in FIG. 4B is input from the terminal 601, and the memory 620,
Input to the packet head detection circuit 630. In the packet head detection circuit 630,
The head of the packet of the input signal is detected, and the detection signal is latch circuit 611,
The data is input to the control circuit 631 and the delay circuit 650. On the other hand, the clock signal input from the terminal 600 is input to the counting circuit 610 and continuously counts the clock signal. The output signal of the counting circuit is input to the latch circuit 611. The latch circuit 611 latches the input count value with the packet head signal from the packet head detection circuit 630. The latched count value is input to the multiplexing circuit 640. This count is
This is packet time stamp information.

A control signal for the memory 620 is generated based on the packet head detection signal input to the control circuit 631. A clock signal input from the terminal 604 is used as a write clock of the memory 620. For this, a signal that matches the packet signal frequency input from the terminal 601 is used. A clock signal input from the terminal 603 is used as a read clock of the memory 620. The clock signal frequency is selected to be higher than the write clock frequency input from the terminal 604. As an example, when the write clock frequency is 30.3 MHz, the read clock frequency is 49.152 MHz. This read clock becomes the bus clock frequency of the signal sent from the interface circuit 50 shown in FIG. 2 to the bit stream recording / reproducing apparatus 70. At this time, if the clock signal of the counting circuit 610 input from the terminal 600, that is, the clock signal frequency for time stamp is set to the same frequency as the clock signal frequency input from the terminal 603, for example, the time stamp clock signal and the terminal 603 are used. Can be the same as the bus clock signal input from. However, the present invention does not limit the time stamp clock frequency to the same as the bus clock signal frequency.

After a packet is input to the memory 620, it is read from the memory after a predetermined time. Since the read clock signal frequency is set higher than the write clock signal frequency, the transmission time of the output packet is made shorter than the transmission time of the input packet signal as shown in FIGS. be able to. Therefore, even in a portion where packets are continuously transmitted, a period for adding header information including time stamp information can be obtained as shown in FIG. An output signal of the memory 620 is input to the multiplexing circuit 640.

The delay circuit 650 delays the packet head detection signal, and outputs a gate signal indicating a position where a time stamp signal is added in accordance with the packet signal output from the memory 620. The gate signal is input to the multiplexing circuit 640. The multiplexing circuit 640 adds the time stamp information from the latch circuit 611 according to the gate signal and outputs the signal shown in FIG.

The signal shown in FIG. 4 (3) is input to the bit stream recording / reproducing apparatus 70. FIG. 6 (1) shows the signal corresponding to FIG. 4 (3) again, and P1, P2,. As described with reference to FIG. 4, there is a gap between the packets of the input signal shown in FIG. 6 (1), but recording is performed with the packet signal intervals being filled as shown in FIG. 6 (2). For example, it can be lower than the rate of the input packet signal. For this reason, the recording rate in the tape transport system can be lowered. Although FIG. 6 shows a diagram in which the input signal (1) and the output signal (2) are output with a delay of one track period, this is shown for convenience and is not limited to one track period. The time required for signal processing may be delayed.

At the time of reproduction, the signal reproduced from the tape transport system is a signal in which packet signals P1, P2,... Are packed as in FIG. FIG. 6 (3) shows the reproduced signal. FIG. 7 is a block diagram showing an embodiment of a time axis adjusting circuit in the bit stream recording / reproducing apparatus 70 for restoring the interval between the reproduced packet signals P1, P2,. FIG. 6 (4) shows the signal after the interval between the reproduction packet signals P1, P2,.

In FIG. 7, reference numeral 710 denotes a memory, 700 denotes an input terminal of the memory 710, 720 denotes a memory, 701 denotes an input terminal of a read clock of the memory 720, 702 denotes a write clock input terminal of the memory 720, and 703 denotes a signal whose time axis is adjusted. 751 is a counting circuit, 704 is a clock signal input terminal of the counting circuit 751, 73
0 is a time stamp gate circuit, 740 is a control circuit, 750 is a time stamp reading circuit, and 752 is a coincidence detection circuit.

The reproduction signal shown in FIG. 6 (3) inputted from the terminal 700 shown in FIG.
0 is input. Signals output from the memory 710 for each packet signal P1, P2,... Are input to the memory 720 and the time stamp reading circuit 750.
The reading control of the memory 710 and the writing and reading control of the memory 720 are performed by a control signal from the control circuit 740. The time stamp reading circuit 7
50 also receives a control signal from the control circuit 740, outputs a signal indicating the position of the time stamp signal to the signal from the memory 710, and reads the time stamp signal at the correct position. The read time stamp signal is input to the coincidence detection circuit 752.

A clock signal having the same frequency as that inputted from the terminal 600 shown in FIG. 5 is inputted from the terminal 704 and inputted to the counting circuit 751. The counting circuit 751 counts the input clock signal and outputs the count value to the coincidence detection circuit 752. The coincidence detection circuit 752 outputs a coincidence signal when the two inputted signals coincide with each other, and inputs the coincidence signal to the control circuit 740.

The control circuit 740 reads the packet signal from the memory 720 based on the coincidence signal. FIG. 6 (4) shows the read signal. The reading is terminal 701.
This is performed based on the read clock signal input from. At the same time, the memory 7
A new packet is input from 10 and written to the memory 720 based on the write clock input from the terminal 702. The frequency of the clock signal input from the terminal 701 may be determined so as to correspond to the signal rate between the interface circuit 50 and the bit stream recording / reproducing device 70.

As shown in FIG. 6 (4), the time-adjusted packet signals P1, P2,... From the memory 720 are output from the terminal 703 at the same time interval as the signal shown in FIG.

As a result, signals with the same packet interval as shown in FIG. 4 (3) are input to the interface circuit 50. The time stamp addition / removal circuit 570 removes the header information and outputs it. As a result, the same signal as the signal from the tuner 510 can be restored.

The block diagram which shows one Example of this invention. The block diagram which shows one Example of this invention. The schematic diagram of the input signal concerning the present invention. The schematic diagram of the signal which concerns on this invention. The block diagram which shows one Example of this invention. The schematic diagram of the signal which concerns on this invention. The block diagram which shows one Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Accumulator 20, 50 ... Interface circuit 40 ... Decoder 70 ... Bit stream recording / reproducing device 420 ... Decompression circuit 440 ... Crystal oscillator 550 ... Clock generation circuit 560 ... Conversion circuit 570 ... Time stamp addition / removal circuit 610, 751 ... Count Circuit 630 ... packet head detection circuit 640 ... multiplexing circuit 750 ... time stamp reading circuit 752 ... coincidence detection circuit

Claims (2)

In a digital signal processing apparatus for processing a digital compressed signal obtained by compressing a video signal or an audio signal,
A program stream input means for inputting a program stream including a digital compressed signal obtained by compressing a video signal or an audio signal ;
Transport stream input means for inputting a transport stream including a digital compressed signal obtained by compressing a video signal or an audio signal and a reference signal synchronized with the video signal or the audio signal;
First clock signal generating means for generating a first clock signal synchronized with a digital compressed signal input from the transport stream input means based on the reference signal;
Second clock signal generating means for generating a second clock signal using a reference clock signal ;
Switching means for switching and selecting the first clock signal and the second clock signal;
Adding means for adding time information indicating the output time of the packet signal to the packet signal constituting the digital compressed signal based on the clock signal selected by the switching means;
Conversion means for converting the program stream into the transport stream;
Have
The switching means selects the first clock signal when recording the digital compressed signal included in the transport stream input from the transport stream input means, and the transport stream converted by the conversion means Selecting the second clock signal when recording
A digital signal processing device.   The digital signal processing apparatus according to claim 1, wherein
  Expansion means for expanding the digital compression signal based on the clock signal selected by the switching means;
  The switching means selects the first clock signal when decompressing the digital compressed signal included in the transport stream input from the transport stream input means, and the program input by the program stream input means Selecting the second clock signal when decompressing the stream;
  A digital signal processing device.

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