JPS6226100B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION When an audio signal or a video signal is recorded and reproduced by a magnetic recording/reproducing device, the present invention uses a memory device to correct time axis fluctuations included in the reproduced signal from the magnetic recording/reproducing device. The present invention relates to a time axis correction device. The present invention allows audio signals to
It is suitable for use in an audio signal recording and reproducing apparatus based on the PCM method, which performs PCM modulation and uses a VTR (video tape recorder) as a transmission path.

Such a signal recording/reproducing apparatus is schematically shown in FIG. In FIG. 1, reference numeral 1 indicates, for example, a rotating two-head type VTR. This VTR 1 receives the video signal given from its recording signal input terminal 1i.
The video signal is supplied to a pair of rotating magnetic heads via a recording system consisting of an FM modulator, etc., and one field of the video signal is recorded on the magnetic tape as an inclined track. Also, playback signal output terminal 1o of VTR1
In this case, a video signal is obtained by passing the signal reproduced from the magnetic tape through a reproduction system consisting of an FM demodulator or the like. This VTR 1 generally has a feature of a wider transmission band than a fixed head type, and is used to record and reproduce a PCM signal whose signal format is the same as that of a video signal.

That is, 2L and 2R are terminals to which left and right signals of the stereo audio signal are supplied, respectively, and these left and right signals are supplied to low-pass filters 3L and 3R, sampling and hold circuits 4L and 4R, and AD conversion, respectively. PCM modulation is performed by passing the signal through the receivers 5L and 5R. Since the digital outputs of the AD converters 5L and 5R are parallel codes, they are converted into a serial format by the parallel-serial converter 6.
The signal is supplied to an encoder 7 for adding an error detection or error correction code. The error-correctable PCM signal from the encoder 7 is supplied to a time-base compression circuit 8 , and the output of the time-base compression circuit 8 is supplied to a synchronization signal addition circuit 9 . The time axis compression circuit 8 and the synchronization signal addition circuit 9 convert the PCM signal into the same signal form as the video signal.The former creates a data missing period corresponding to the vertical blanking period in the video signal, and the latter creates a A synchronization signal corresponding to the vertical synchronization signal and horizontal synchronization signal in is added. The output of this synchronizing signal addition circuit 9 is supplied to the recording signal input terminal 1i of the VTR 1.

That is, FIG. 2 shows one field period (262.5H, where H is the horizontal period) of this recording signal, and no data is inserted in the vertical blanking period including the vertical synchronization signal VD and the periods before and after it. for example
A PCM signal is inserted during the 245H period. At this time, one sample value of the left and right audio signals and an error detection or error correction code for them are treated as one unit, and a horizontal synchronization signal HD is located for each unit. In this case, the horizontal sync signal HD
is said to be three times the frequency of the original horizontal synchronization signal of the television signal. This horizontal synchronization signal HD has a role as a timing signal that becomes a time base during reproduction.

During reproduction, a reproduction signal similar to that shown in FIG. 2 is supplied to the time axis expansion circuit 11 via the synchronization signal separation circuit 10. A continuous PCM signal appears at the output of the time axis expansion circuit 11 and is supplied to the decoder 12. The decoder 12 detects and corrects errors such as burst errors due to dropouts in the VTR 1, and the serial-to-parallel conversion circuit 13 converts the code into a parallel code. And DA conversion circuit 1
4L and 14R and low pass filter 15L and 1
By passing through the 5R system, the output terminal 16L
A left signal is obtained at the output terminal 16R, and a right signal is obtained at the output terminal 16R.

The time axis compression circuit 8 and the time axis expansion circuit 11 are
This is realized using RAM or multiple shift registers. Further, the recording system is provided with a reference oscillator (not shown), and from the output of the reference oscillator, sampling pulses to the sampling hold circuits 4L and 4R are generated.
Clock pulses for AD converters 5L, 5R, parallel-to-serial converter 6, encoder 7, and time base compression circuit 8 are formed. On the other hand, in the reproduction system, clock pulses for the time base expansion circuit 11, decoder 12, serial/parallel converter 13, and DA converters 14L and 14R are formed using the synchronization signals HD and VD separated from the reproduction signal as time bases.

Here, since the reproduced signal includes time axis fluctuations, a clock pulse having a timing synchronized with the reproduced signal is extracted, and the reproduced signal is once written into the memory device of the time axis expansion circuit 11 using this first clock pulse. As the time axis is extended, the signal is read out using a second clock pulse from which stable time axis fluctuations are removed. In this case, if the drive mechanism of the VTR 1 operates extremely stably, a signal with a fixed frequency such as a crystal oscillator can be used as the second clock pulse, but a general-purpose
In VTRs, the drive mechanism is simplified, so not only relatively high frequency time axis fluctuations such as jitter, but also low frequency time axis fluctuations called drift, for example 0.3Hz or less, are included in the playback output. However, if a fixed frequency second clock pulse is used, the capacity of the memory device must be increased, otherwise overflow or underflow may occur. Therefore, in the above-mentioned PCM audio signal recording and reproducing apparatus, there are two timing systems, namely, a first timing system synchronized with relatively high frequency time axis fluctuations, and
A first system for forming a clock pulse and a second system for forming a second clock pulse that follows only low-frequency time axis fluctuations are provided. When these timing systems are composed of phase locked circuits called PLL circuits, the closed loop cutoff frequency of the first PLL circuit is selected to be high, and the closed loop cutoff frequency of the second PLL circuit is selected to be low. When the time axis is expanded and corrected using the first and second clock pulses, low frequency time axis fluctuations remain in the output signal, but in the case of an audio signal, Such low-frequency time axis fluctuations are not harmful to the sense of hearing and pose no problem.

In the present invention, as described above, data is written to and read from a memory device using a first clock pulse that follows relatively high fluctuations in the time axis and a second clock pulse that follows low frequency fluctuations in the time axis. This is aimed at correcting the fluctuation, and in particular, the first and second clock pulses are formed by one PLL circuit, thereby simplifying the configuration of the timing system.

An embodiment in which the present invention is applied to a reproducing system of the above-mentioned PCM audio signal recording and reproducing apparatus will be described below. Here, the time axis expansion circuit 11 is composed of a memory device 20 and a memory control circuit 21 such as a circuit for controlling writing and reading thereof. Data from which the synchronization signal has been removed (regenerated PCM signal) is supplied to the memory device 20 from the synchronization signal separation circuit 10, and a composite synchronization signal from the synchronization signal separation circuit 10 is supplied to the synchronization signal reproduction circuit 22. From this, the frequencies of the vertical synchronizing signal VD and the horizontal synchronizing signal HD are reduced to 1/3, and horizontal synchronizing signals HD' having the same frequency as the original signals are respectively extracted. Since the vertical synchronizing signal VD has a 1/2H shift between a certain field and the next field to perform interlacing, it is passed through a 1/2 frequency divider 23 and is the standard of the PLL circuit 24 shown surrounded by a broken line. It is considered as an input signal. This 30 Hz reference input signal is supplied to a phase comparator 25, and its phase is compared with a signal obtained by dividing the frequency f _c output of a voltage-controlled variable frequency oscillator 26 by a 1/N frequency divider 27. The error output of the phase comparator 25 has harmonic components removed by a low-pass filter 28, and is sent to the variable frequency oscillator 2.
It is applied as a control voltage of 6.

Such a PLL circuit 24 has a closed loop cutoff frequency of
0.2 to 0.3 (Hz), and has the characteristic of following only the drift component below the closed loop cutoff frequency. Therefore, the variable frequency oscillation circuit 26
The output is one in which the time axis fluctuation components in the audible frequency band included in the reproduced PCM signal are suppressed. In order to choose a low closed-loop cutoff frequency in this way, the frequency of the reference signal must be 30° lower than the horizontal frequency.
Lower Hz is advantageous.

Then, the counter of the 1/N frequency divider 27 of the PLL circuit 24 outputs a second clock pulse having a frequency f _sb (=f _c /n) divided by 1/n to the output terminal 28b. Further, the output of the variable frequency oscillator 26 is supplied to a 1/m frequency divider 29 composed of a counter. This 1/m frequency divider 29 has a synchronization signal regeneration circuit 2.
2 is supplied as a reset pulse, and the frequency f _tb (=
A first clock pulse of f _c /m) is obtained. In this case, since the time axis fluctuation included in the reproduced PCM signal is suppressed, if the output of the variable frequency oscillation circuit 26 is used as the first clock, the bit synchronization of the reproduced PCM signal will not be achieved. there is a possibility. However, the frequency of VTR time axis fluctuations is mostly distributed below several hundred Hz.
Also, since the high frequency component is about 3 kHz, the PLL is operated at a frequency f _c that is sufficiently higher than the frequency of the first and second clock pulses, and the 1/m frequency divider is set to the frequency of the time axis fluctuation. By resetting every horizontal synchronization signal HD with a frequency (15.75kHz) that is sufficiently higher than that of the PCM signal, the first clock pulse that follows the time axis fluctuation contained in the output of the reproduced PCM signal is formed, and the memory write The side bit synchronization signal can be synchronized with the reproduced PCM signal.

With the above configuration, the frequency f of the variable frequency oscillator 26
_cOther frequencies and frequency division ratios are selected as follows, for example.

f _c : 14.112 [MHz] f _tb : 1.764 [MHz] f _sb : 1.4112 [MHz] m: 8 n: 10 N: 470400 The first clock pulse obtained at the output terminal 28a is supplied to the memory control circuit 21. The reproduced PCM signal is written to the memory device 20 in synchronization with the first clock pulse, and is output to the output terminal 28b.
A second clock pulse from the memory device 20 is supplied to the memory control circuit 21, and a reproduced PCM signal is read out from the memory device 20 in synchronization with the second clock pulse. The reproduced PCM signal obtained by the time axis expansion circuit 11 in this manner is continuous data without data missing periods, and time axis fluctuations harmful to the auditory sense have been removed.

FIG. 4 shows an example of a specific configuration of the PLL circuit 24. In the same figure, 30 is a monostable multivibrator that forms a reset pulse synchronized with the reference signal from the 1/2 frequency divider 23. This reset pulse resets the sawtooth wave generation circuit 31, and the reference signal A sawtooth wave synchronized with is supplied to the sampling and hold circuit 32. A sampling pulse formed by a monostable multivibrator 33 is supplied to the sampling hold circuit 32 from the output of the 1/N frequency divider 27. Therefore, an error signal having a level corresponding to the phase difference between the reference input signal and the output of the variable frequency oscillator 26 is obtained from the sampling and hold circuit 32.

According to the present invention described above, one PLL circuit 24
The first clock pulse for writing follows relatively high frequency time axis fluctuations in the reproduced signal, and the second clock pulse for reading follows relatively high frequency time axis fluctuations in the reproduced signal.
The circuit configuration can be simplified compared to the case where these clock pulses are formed using separate PLL circuits. Of course, the use of such first and second clock pulses has the advantage that the capacity of the memory device for time axis correction can be relatively small.

Furthermore, the present invention can be applied to devices other than the above-mentioned PCM audio signal recording and reproducing apparatus. For example, even in the case of video signals, low-frequency time axis fluctuations of 0.3 Hz or less have a very small effect on the playback screen, so applying the present invention can provide similar benefits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a PCM audio signal recording and reproducing apparatus to which the present invention can be applied, FIG. 2 is a waveform diagram of the recording signal, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is a block diagram of a part of it. 1 is a VTR, 2L and 2R are input terminals for left and right stereo signals, 8 is a time axis compression circuit, 11 is a time axis expansion circuit, 20 is a memory device, and 24 is a PLL circuit.

Claims (1)

[Scope of Claims] 1. An input signal including a synchronization signal and a data signal with time axis variation is supplied, and among the input signals, the data signal with the time axis variation is stored in a memory device based on a first clock pulse. A time axis correction device for correcting time axis fluctuations of the data signal by writing and reading the data signal from the memory device based on a second clock pulse, the circuit for extracting a synchronization signal from the input signal; , a first pulse generating circuit that is supplied with a reference signal based on the extracted synchronization signal and forms the second clock pulse that follows only relatively low frequency component fluctuations among the time axis fluctuations; and a second pulse generating circuit for forming the first clock pulse from the output of the first pulse generating circuit in synchronization with a timing signal having a frequency higher than the frequency band of the time axis fluctuation based on the synchronizing signal. A time axis correction device characterized by: 2. The first pulse generation circuit includes a variable frequency oscillation circuit that oscillates at a frequency higher than the frequency of the second clock pulse, and a first frequency division circuit that divides the oscillation output of the variable frequency oscillation circuit. a phase comparison circuit that compares the phase of the frequency division output of the first frequency division circuit and the reference signal; and a phase comparison circuit that removes harmonic components from the error output of the phase comparison circuit and supplies the resultant signal as a control signal to the variable frequency oscillation circuit. and a PLL circuit whose closed loop cutoff frequency is set below the audible frequency band, and extracts the divided output of the first frequency dividing circuit as the second clock pulse, and The second pulse generating circuit includes a second frequency dividing circuit that divides the oscillation output of the variable frequency oscillation circuit of the PLL circuit and is reset by the timing signal. 2. The time axis correction device according to claim 1, wherein the frequency-divided output is extracted as the first clock pulse.