JPH01305785A - Jitter correction device - Google Patents

Abstract

PURPOSE:To precisely detect a time base error by using a part ot FM carrier as a substitute for reference burst. CONSTITUTION:A signal (d) having been regenerated by a magnetic head 15 is supplied to a time base error correction circuit 30 as an input with a jitter component. A carrier gate pulse GP for horizontal synchronization is generated from a video signal (e) after passing through a demodulation circuit 16 by a negative polarity.positive polarity separation circuit 41, and the FM carrier FMC corresponding to signal (d) peak value is extracted and separated by a carrier gate 42, and is made to function as the reference burst signal. The FMC is improved in SN ratio by letting pass through a BFP 43. A delay pulse generation circuit 45 inputs the signal (e), and generates a pulse DP delayed from the trailing edge of a horizontal sync signal. A jitter detection circuit 44 is set at the trailing edge of DP and is reset at the zero-cross point of the cycle of FMB where an FM wave becomes maximum amplitude by the signal DP and FMB, and generates a trigger Jp. The error correction circuit 30 inputs various kinds of sync signals 50 and the trigger Jp, and substitutes them for a normal sync signal by a negative polarity.positive polarity synchronous substitution circuit 60, and an output which has the same time base as that at the time that it was supplied to an input terminal and is free from the jitter is obtained at an output terminal 30a.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is a jitter correction device suitable for application to a video tape recorder, in particular a jitter correction device for a video signal including a horizontal synchronization signal embedded in the signal such as a MUSE signal. Regarding equipment.

[Prior Art] When a video tape recorder is used to record a video signal and an attempt is made to play back the video signal, a problem arises due to fluctuations in the tape running system.
As a result, a time axis error, ie, jitter, occurs in the video signal.

Therefore, in the reproduction system, it is necessary to detect this jitter and correct the time axis.

As this reference signal (reference phase signal) for jitter detection, a synchronization signal inserted into normal video No. 18 is often used.

However, video signals used in high-definition television systems, such as MUS for satellite broadcasting,
In the case of a video signal that includes a horizontal synchronization signal embedded within the signal, such as the E signal, the synchronization signal contained therein cannot be used as it is as a phase reference signal. The reason for this is explained below.

In other words, in the MUSE system proposed as a high-definition television system, as shown in Figure 4, the horizontal synchronization signal is a positive polarity type (positive polarity ternary synchronization type) embedded in the video signal, and this Detection of positive polarity synchronization is based on the assumption that the horizontal jitter of the MUSE signal is extremely small.

Therefore, when recording and reproducing data while leaving the synchronization signal as a positive polarity signal, it is extremely difficult to obtain from the synchronization waveform (FIG. 8) a jitter detection signal sufficient to accurately perform jitter correction during reproduction.

For this reason, the following method has been proposed as a jitter detection means for the MUSEfg issue.

First, the MUSE signal is time-base compressed, and a horizontal synchronization signal and a reference burst signal are inserted into the vacant period. During playback, a so-called burst insertion unit extracts a highly accurate time error signal from the reference burst signal, generates a write clock trigger signal from this signal, and performs jitter correction by correcting the write timing of the playback video signal. The second construction method is MUSE (, small amplitude in No. 3,
This is a so-called pilot signal superimposition method in which a single frequency pilot signal is superimposed, the pilot signal is processed, and this is used as a write clock for a time error correction memory.

[Problems to be Solved by the Invention] By the way, in the case of the burst insertion section creation method, which is the first jitter correction means, there is a drawback that the circuit configuration becomes complicated.

This will be explained with reference to FIG.

In the figure, a MUSE signal supplied to a terminal 11 is time-base compressed in a time-base compression circuit 12, and then a burst bias, which is a reference phase number 13, is added in addition to the horizontal synchronization signal in a synchronization burst addition circuit 13. The signal is then subjected to FM modulation by an FM modulator 14, and recorded on a video tape by a magnetic head 15.

The reproduced MUSE signal is modulated by l''Ml in the demodulator 16 and then supplied to a time base error correction circuit (TBC) 17 which functions as a jitter correction means.

On the other hand, the FM demodulated MUSE signal is also supplied to the write clock forming means 18. Here, a burst signal is extracted, a variation with respect to a reference phase is detected, and a write clock Wck corresponding to the variation on the time axis is generated.

Since the write timing of the MUSE signal is controlled by this write clock Wck, if a clock having a regular time axis is used as the read clock, TBC1
From 7 onwards, MU S E 4M number with the same time axis will be output.

Thereafter, the added horizontal synchronization signal and burst signal are removed in the synchronization/burst removal circuit 19, and then the time axis is expanded in the time axis expansion circuit 20, and the signal is returned to the input MUSE signal.

As described above, according to the first jitter correction means, since the synchronization signal and Burst Toy No. 3 are inserted into the MUSE signal, signal processing such as compressing or expanding the time axis of the MUSE signal is inevitably required.

In addition to the increase in circuit scale caused by this,
Problems such as an increase in time band and an increase in recording area due to time compression processing also arise.

In the case of the pilot signal superimposition method, which is the second jitter correction means, since it is a superimposed recording of MUSE (No. 3) and pilot (No. 3), both No. amplitude accuracy is required.

However, when attempting to obtain such amplitude accuracy, there is a problem in that a sufficient carrier amplitude cannot be obtained and the S/N of the reproduced MUSE signal decreases. Furthermore, a decrease in the S/N of the pilot signal tends to cause a time base error when detecting the base phase signal, resulting in an increase in residual jitter.

The present invention was devised to solve these problems, and proposes a sick correction device that does not increase the circuit scale or generate residual jitter.

[Means for Solving the Problems] In order to solve the above-mentioned problems, in the present invention, when recording and reproducing a video signal including a horizontal synchronization signal embedded in signal processing, a part of the horizontal blanking period is used during recording. Or all of them are replaced with the prominent horizontal synchronization signal, and the FM of the video signal
During modulation, the FM carrier phase corresponding to the leading edge of the replaced salient horizontal sync signal is reset to a constant value, and during playback, the burst carrier obtained by gating the FM carrier in the sync chip corresponding portion is used as the reference burst. , the time axis error during playback is detected.

[Function] When recording a video signal, part or all of the horizontal blanking period including positive polarity synchronization of the recorded video signal is replaced with a prominent horizontal synchronization signal (negative horizontal synchronization signal). after that,
The leading edge position of the horizontal synchronization signal and the position of the FM carrier portion corresponding to the synchronization peak value are synchronously recorded every horizontal cycle.

During playback, the carrier section corresponding to the sync chip is gated as a reference burst using the FM demodulated horizontal synchronization signal, and after passing through a band-pass filter for noise removal, a specific zero cross corresponding to the reference burst is detected based on the horizontal synchronization trailing edge. Points are extracted.

Since the extracted zero-crossing points reflect time axis fluctuations during playback, the time axis is corrected based on this.

Since the time axis of the trailing edge of horizontal synchronization is very stable, if a reference burst is extracted using this as a reference, the time axis error of ILR raw video No. 13 can be detected with high accuracy.

[Embodiment] Hereinafter, an example of the sick correction device according to the present invention will be described in the case where it is applied to the above-mentioned MUSE signal recording/reproduction processing system.
, No. 113 and subsequent sections will be described in detail. .

FIG. 1 shows an MU including a jitter correction device according to the present invention.
FIG. 2 is a system diagram showing an example of the recording/reproducing system 10R and IOP of SE-2.

As is well known, the MUSE signal is a line sequential type '1゛C1(
'rime Con+presscd integra
As shown in FIG. 2, the video signal includes a positive ternary synchronization signal
is inserted.

The MUSE signal a supplied to the terminal 21 is supplied to the same signal detection circuit 22, and a positive synchronization signal I (D) is detected, and the protruding synchronization generation circuit 23 is driven based on this synchronization signal.

As the protruding synchronization signal, there are a negative synchronization signal and a positive synchronization signal, and in the embodiment, a case where a negative synchronization signal is used is exemplified.

When the negative synchronization generating circuit 23 is driven, the negative synchronization signal PH as shown in FIG.
Created in sync with. Further, in this example, the negative synchronization signal PH is generated as No. 18 corresponding to the entire horizontal blanking period as shown in the figure.

The negative polarity synchronization signal PH is subjected to synchronization replacement with the input MUSE signal a in the synchronization replacement section 24 . That is,
A synchronization change is performed. Therefore, MU after synchronous replacement
The SE signal becomes as shown in FIG. 2B.

On the other hand, this MUSE signal is F in the FM modulator 14.
At the beginning of the horizontal blanking period, the FM carrier is reset by a reset pulse RP (FIG. 2C) described below.

That is, the carrier is reset every horizontal period so that the leading edge position of the negative synchronization signal and the position of the FM carrier A7 corresponding to the synchronization peak value are synchronized.

Therefore, the negative synchronization signal pH is also supplied to the reset pulse forming circuit 25, and the negative synchronization signal 1. ) In front of I-1 H
A reset pulse RP corresponding to is generated.

On the other hand, the FM modulation circuit 14 is configured as an external reset type, and the reset pulse RP resets the intended position of the carrier corresponding to the sync chip to a constant phase (0° or 180') every horizontal cycle.

An example of FM allocation during FM modulation is shown in FIG. 2B. According to this example of FM allocation, the carrier corresponding to the sync depth is 8 MHz. This frequency is just an example, and as shown by the broken line in FIG. 2B, an FM carrier higher than the video signal (for example, 13 MHz) can also be used as the sync chip compatible carrier.

By such a reset process, the leading edge (falling part) of the horizontal synchronizing signal PH and the phase of the FM carrier are synchronized.

Here, the number of cycles of the FM wave corresponding to the horizontal synchronization signal part depends on the FMM wave number, but as mentioned above, if the FMM wave number is replaced so that it becomes 13 M 1-1 z, for example, it will be as short as about 700 nsec. FM carrier FM of about 9 cycles even within the horizontal blanking period
C (Fig. 2 D) can be obtained. As a result, if the CN ratio during playback is 30 dB or more, the FM carrier FM
C can be detected with an accuracy within 5 n5ec.

The obtained FM video a (epsilon C) is recorded on a video tape by the magnetic head 15.

During reproduction, first the F reproduced by the magnetic head 15
The M video signal light (E) in the same figure is sent to the FM demodulation circuit 16 and the carrier gate circuit 42. The FM demodulated video signal e can then be supplied to the time base error correction circuit (TBC) 30 as an input video signal having a jitter component.

Therefore, first, the FM demodulated video signal e is supplied to the synchronization separation circuit 41, and the horizontal synchronization signal PH is extracted from the video signal e, from which the horizontal synchronization carrier gate pulse GP is generated (the same Figures F, G).

This gate pulse GP is supplied to the carrier gate circuit 42, and the FM wave (FM carrier FMC corresponding to the horizontal synchronization peak value) in the horizontal periodic signal section of the reproduced FM image signal d is extracted and separated (FIG. 1[ ).

The separated FM carrier serves as a reference burst signal. By passing this through the narrow band pass filter 43, the S/N ratio is roughly improved (FIG. 1).

On the other hand, the demodulated video signal e is further processed by a delay pulse forming circuit 45.
A delayed pulse DP (J in the same figure) which is delayed by a predetermined time from the trailing edge of the horizontal synchronizing signal PH is formed.

This delayed pulse DP is transmitted through the narrow band pass filter 4 described above.
The jitter detection circuit 44 is sent together with the FM carrier FMB, which is the output from the FM carrier FMB, from the RS flip-flop. Then, it is set at the falling edge of the delay pulse DP,
It is reset by the zero-crossing point of the cycle of FM carrier FMB that includes this rising point.

Therefore, a jitter detection signal JP as shown in FIG. 2K is obtained from this jitter detection circuit 44.

Here, the delayed pulse D is based on the trailing edge of the horizontal periodic signal.
P is formed because the influence of carrier leak during FM demodulation on the horizontal periodic signal PH is significantly smaller at the trailing edge than at the leading edge.

That is, even if there is a carrier leak, the phase of the leak component becomes more stable as it moves from the leading edge, which is the phase reset point, toward the trailing edge.

The specific zero crossing point of the FM carrier mentioned above is the FM
The zero-crossing point of the cycle where the wave reaches its maximum amplitude. The reason why the FM carrier near the maximum amplitude is used in this way is to improve the S/N ratio and avoid the influence of noise on detection accuracy.

Therefore, if such a signal is used, jitter detection accuracy can be improved.

Jeddah detection (G No. JP is the write clock generation circuit 32
is supplied as a write trigger signal, and the write/write clock W c k is generated in synchronization with this "jitter detection signal JP. This means that the write clock W c k
will also have the same jitter as the reproduced video signal.

On the other hand, 50 is a synchronization signal generation circuit that stably generates various synchronization signals, and a reference signal (drive pulse) to the capsun drum servo circuit 51 is supplied from this circuit. In addition, a clock pulse serving as a reference for the read clock is also formed, and the read clock Rck generation circuit 33 is driven in synchronization with this clock pulse.

Then, the read clock Rck is the memory 3 for TBG.
1.

Since the read clock Rck has a regular time axis,
If the video signal is read out based on this readout clock Rck, a video signal whose time axis has been corrected and whose jitter has been completely corrected can be obtained. This time-base corrected video signal is replaced by a regular synchronization signal (positive synchronization signal) in a negative/positive synchronization replacement circuit 60.

Through this series of processing, the video signal obtained at the terminal 30a, that is, the MUSE signal, is output as a jitter-free signal having the same time axis as when it is supplied to the input terminal 21 of the recording system 10R. .

No. 31 shows an example of the TBC 30.

In the figure, reproduced video No. 13e is converted into a digital video signal with a predetermined number of pits by a Δ/D converter 61, and then written onto the memory 3 by the above-mentioned write clock Wck having an input clock.

The written digital video signal has a regular time axis of fT.
After that, the signal is read out by the readout clock Rck, and then synchronized FJ is executed in the synchronization replacement circuit 60, converted into an analog video signal in the D/A converter 62, and band-limited by the low-pass filter 63. . Therefore, from the output terminal 30a, the normal M
A USE signal is output.

The above-mentioned sick detection signal JP is supplied to a write clock generation circuit 32 having a PLL configuration, and a write/input clock Wck corresponding to the reproduced sick is generated.

64 is a voltage controlled oscillator (VC○), and the write clock Wck output from this is divided by 1/n by a clock reducer (frequency division counter) 65 to form one clock per horizontal period. This signal is supplied to the phase comparator 66 together with the jitter detection signal JP.

As a result, the write clock Wck is output as a clock whose phase is synchronized with the sick detection signal JP.

Therefore, the digital video image 3 written in the memory 31
The number retains the playback jitter as is.

The B input clock Wck is roughly supplied to the memory address counter 67. The counter 67 can be supplied with the jitter detection signal JP as a phase reference signal for the write start pulse.

The counter 67 receives a stable read clock Rc output from the read clock generation circuit 33, which is roughly described above.
k and a read clock which is counted down to 1/n by a counter 68 are supplied to the memory 31.
An address signal is formed for the address signal.

The above-mentioned salient synchronization signal may be a positive horizontal synchronization signal (No. 8). The transition period of synchronization No. 13 may be a part of the horizontal blanking period.

In addition, in the above, the MUSE signal was exemplified as a video signal that has an extremely narrow horizontal blanking period and includes a horizontal synchronization signal embedded in No. 5, which has positive polarity synchronization.
The present invention can also be applied to a jitter correction device for video signals other than signals.

[Effects of the Invention] As described above, according to the present invention, even when recording and reproducing a video signal having an extremely narrow horizontal blanking period and positive synchronization, a part of the FM carrier is replaced by a reference burst. By using the FF instead of the FF, the time axis error can be detected accurately without complicating the circuit configuration.

Also, FM video (No. 5 has a high frequency, so 1 (t
Since the cycle period is short, the time axis error detection accuracy is increased, so it is possible to output a reproduced video signal with less residual jitter.

Since there is no need to sacrifice the S/N of the video signal for jitter detection, the S/N does not decrease and residual jitter does not occur.

Therefore, the jitter correction device according to the present invention is extremely suitable for application to a video recorder for recording and reproducing the MUSE signal as described above.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a video tape recorder incorporating a jitter correction device according to the present invention, FIG. 2 is a timing diagram showing waveforms of each part in FIG. 1, and FIG. 3 is an example of a time axis error correction circuit. In the block diagram, FIG. 4A is a diagram showing the allocation of one horizontal line of the MUSE signal, FIG. 4B is a diagram showing the HD waveform within the HD period, and FIG. FIG. 2 is a block diagram showing an example. 10R...Recording system 10P...Reproduction system 23...Negative polarity synchronous generation circuit 24...Positive polarity/negative polarity synchronous replacement circuit 25...Reset pulse forming circuit 30...TBC 32...Write clock generation Circuit 33...Read clock generation circuit 42...Carrier gate circuit 44...Sick detection circuit 45...Delayed pulse forming circuit 60...Negative polarity/positive polarity synchronous replacement circuit

Claims (1)

[Claims] (1) When recording and reproducing a video signal that includes a horizontal synchronization signal embedded in the signal, part or all of the horizontal blanking period is replaced with a salient horizontal synchronization signal during recording, and when FM modulating the video signal, The FM carrier phase corresponding to the leading edge of the replaced salient horizontal synchronization signal is reset to a constant value, and during playback, the burst carrier obtained by gating the FM carrier in the sync chip corresponding portion is used as a reference burst, and playback is performed. A jitter correction device characterized in that a time axis error in time is detected.