JPS6148170A - Data reproducing device - Google Patents

Abstract

PURPOSE:To attain sure data sampling by resetting a frequency divider which divides an output frequency of a controlled oscillator with a reproduced VD so as to eliminate instable operation of the controlled oscillator. CONSTITUTION:A 1/n frequency divider 14 frequency-divides the output of the voltage controlled oscillator 13 in the same frequency as that of a reproduced horizontal synchronizing signal. On the other hand, a monostable multivibrator circuit 21 outputs a prescribed length of pulse by using the reproduced VD and the 1/n frequency divider 14 is reset by the said pulse. It is desired most to set the timing of the reset just after the joint of the recording signal of a circular track is reproduced. Even if one horizontal frequency signal is missing at recording, malfunction of the voltage controlled oscillator 13 is eliminated and no 1/2H screw compensation circuit is required, the circuit constitution is simplified and data is sampled surely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a data reproducing device and to a data reproducing device that reproduces a data signal recorded together with a synchronizing signal based on the synchronizing signal. It is.

[Prior art]

In this specification, as an apparatus of this type, a conventional still image recording/reproducing apparatus records a video signal for one field on a circular track using a rotating magnetic sheet and repeatedly reproduces the same to obtain a still image. I will explain what is used. FIG. 1 is a diagram showing a recording pattern of a circular track in this type of device.If the image information recorded on one circular track includes field image information, in the NTSC system, 262.5 I'T This will record the signal for 1 minute. Here, H represents one horizontal opening period.

Is it something like the above? In accordance with one format, digital binary data is inserted in place of these video signals.
A method of storing information required by users has been proposed.

Figure 2 shows the shape of the recorded signal at that time.
A is a horizontal synchronization signal section, B is a sync data section, and C is an information data section.

The data is reproduced based on the horizontal synchronization signal, but 11
? 1262.5) Since only I minutes are recorded, the reproduced horizontal synchronizing signal always has a +H skew at the field switching section.

FIG. 3 is a timing chart of this reproduced horizontal synchronizing signal, and is used to explain the above-mentioned →·)I skew.

In order to remove this skew, in a normal regenerator,
A +H skew compensation '7.1 circuit is provided.

Figure @4 is a block diagram of an example of a conventional general data reproducing system Q-. 1 is a drive motor, 2 is a rotating magnetic sheet, and 3 is a reproducing head.The recording signal of the magnetic sheet 2 reproduced by the reproducing head 3 passes through a reproducing amplifier 4, and then is input to the baseband region by an amplifier 5. demodulated.

The demodulated signal contains the above-mentioned +H skew because it is broken by repeating one field, and is led to the skew distortion corrector 8 for correcting this. In this skew distortion corrector 8, an original signal and a +H delay signal (6 is a +-H delay line) are alternately generated from a PG (pulse generator) head 19 through a pulse shaper 20, and a magnetic sheet 2 is generated. The switch circuit 7 cuts each field using a PG pulse synchronized with the rotation. The reproduced signal from which the +H skew has been removed in this way is transferred to the horizontal inter-pitch signal separation circuit 9.
and the clamp circuit 15. The horizontal synchronization signal separated by the horizontal synchronization signal separation circuit 9 is introduced as one input of a phase detector 10, and the output of this phase detector 10 is passed from an LPF (low pass filter) 11 to an amplifier 12, and is then input to a voltage controlled oscillator. 130 control signal. The output of this voltage controlled oscillator 13 (oscillation frequency 1nfH is l/
n frequency divider 14 and data sampling circuit IT. A signal with a frequency fu equal to that of the horizontal synchronization signal is obtained from the 1/n frequency divider 14, and this is transmitted to the phase detector 10.
becomes the other input.

In other words, PLL (phase locked loop)
From the voltage controlled oscillator 13, a signal of n times the frequency (fitf) synchronized with the regenerated horizontal synchronizing signal is output. The data signal S and the information data signal O are separated by a sink data separation circuit 16, and the information data signal S is sent to the voltage controlled oscillator 1.
The thus obtained reproduced data signal is temporarily stored in, for example, the memory circuit 18, and subjected to error correction, detection, etc., or is displayed on a monitor based on this data.

However, the magnetic sheet 10 rotation drive motor 1 shown in FIG. 4 usually has some degree of uneven rotation, and cases such as those shown in FIGS. 5(a) and 5(b) may occur during recording. These figures are explanatory diagrams of two examples of recording patterns caused by rotational fluctuations of the drive motor 1.

FIG. 5(a) shows an example in which the time for one rotation of the drive motor is shorter than one field, and overwriting is performed in the sheet rotation direction for a certain amount of time from the start of filling. Figure 5 (b) is an example of the opposite case to (a) above, that is, the motor rotation time is longer than the length of one field. No writing is performed, but the interval of the reproduced horizontal synchronization signal changes. In particular, it does not occur in case (b), but (a)
In this case, there is a high possibility that the horizontal synchronization signal written immediately after the start of writing will disappear due to a failed write, and in this case, even if +H skew distortion correction as shown in Figure 4 is performed, Since each horizontal synchronization signal is always missing, a problem arises in that the interval between the reproduced horizontal synchronization signals changes greatly.

FIG. 6 shows an operational waveform diagram of each signal. In FIG. 6, A is the output of the 1/n frequency divider 14 in FIG.
H is the frequency, and B is the reproduction horizontal synchronization signal output.

C is the output of the phase detection circuit 10, which generates an output pulse for a period corresponding to the phase difference between A and 8. D
is the output waveform obtained by passing this through the LPFll, and the voltage controlled oscillator 13 is controlled by this. In this, B
The absence of the second pulse corresponds to the disappearance of the horizontal periodic signal immediately after the start point in FIG. The oscillation frequency of the controlled oscillator 13 fluctuates greatly in response to this, and as a result, the sampling pulse in the data sampling circuit 17 cannot be synchronized with the data bit.
Sampling errors occur and the data cannot be read correctly.

More precisely, if recording is ideally possible as shown in FIG. As shown in the operating waveform diagram C in FIG. 7, the horizontal synchronizing signal also appears immediately after the switching time t0.

Here, A is the horizontal synchronization signal separated from the original signal, and B is the horizontal synchronization signal separated from the +H delayed signal. In this case as well, the same amount of malfunction occurs in the phase detector 10 at the time of switching.

〔the purpose〕

The present invention has been made in consideration of the above-mentioned point of view, and it is possible to stably sample data by eliminating the unstable operation of the controlled oscillator near the switching point, which is a drawback of the conventional example described above. The purpose is to provide a data reproducing device that can.

〔Example〕

The present invention will be explained below based on the drawings. FIG. 8 is a block diagram of an embodiment of the main circuitry of a playback device according to the present invention, and the same or similar components as in the conventional example shown in FIG. 4 are designated by the same reference numerals. In this case, an attempt is made to reset a divider that outputs a frequency-divided signal of the output of a voltage controlled oscillator to be compared with a reproduced horizontal synchronizing signal by 91 degrees using a reproduced vertical synchronizing signal (VD).

In FIG. 8, 14 is a 1/n divider which divides the output of the voltage control generator 13 into the same period as the reproduced horizontal synchronizing signal. On the other hand, 21 is a mono multi-circuit, and this circuit outputs a pulse of a fixed length by the reproduction VD, and the l/n division period 14 is reset by this pulse. It is most desirable to set the timing of this reset immediately after reproducing the joint of the recorded signal on the circular track. Therefore, even if one of the horizontal periodic signals is missing during recording, the voltage controlled oscillator 13 will not malfunction, and there is no need for a +H skew compensation circuit, simplifying the circuit configuration and simplifying data processing. [Effect] As explained above, according to the present invention, since the divider that divides the frequency of the output of the controlled oscillator is reset by the reproduction VD, the instability of the controlled oscillator is reduced. The movement is gone,
This has the effect that data sampling can be performed reliably and the circuit configuration can be simplified at the same time.

[Brief explanation of drawings]

1 is a diagram showing a circular recording track pattern, FIG. 2 is a recording signal format diagram, FIG. 3 is a timing chart showing a reproduction horizontal synchronization signal, and FIG. 4 is an example of a conventional data reproduction device 6. The block diagram of FIG.
1 and 7 are conventional operation waveform diagrams of each signal,
The figure is a block diagram of an embodiment of the main circuit 411 of the data reproducing apparatus according to the present invention. 1... Drive motor 2... Rotating magnetic sheet 3... Playback head 4... Playback amplifier 5... Demodulator 8... ... Skew distortion corrector (+H skew compensation circuit) 10 ... Phase detector 11 ... Low pass filter (LPF) 12 ...
...Amplifier 13...Voltage controlled oscillator 14...1/n frequency divider 1G...Sink data n circuit 17...
...Data sampling circuit 18...Memory circuit 19...PC head 20...Pulse shaping circuit

Claims (1)

[Claims] A device for obtaining a reproduced data signal from a circular track on a recording medium on which information signals including a horizontal synchronizing signal, a vertical synchronizing signal, and a data signal are recorded, the controlled oscillator being phase-synchronized with the reproduced horizontal synchronizing signal. sampling the reproduced information signal by the output of and reproducing the data signal;
Comparing the phases of the reproduced horizontal synchronizing signal and a signal obtained by dividing the control oscillator output by a frequency divider, controlling the control oscillator according to the phase difference, and resetting the frequency divider with the reproduced vertical synchronizing signal. A data reproducing device characterized by comprising: