JPH0131353B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase error detection device for detecting a phase error of a reproduced horizontal synchronizing signal in a recorded information reproducing apparatus.

Recorded information reproducing devices such as VTRs (video tape recorders) and VDPs (video disk players) detect how much the phase of the reproduced horizontal synchronization signal deviates from the reference signal, and then performs a process according to the phase error. A servo control device is provided that controls the rotational speed of the reproduction bed and disk as desired and accurately corrects time lag in reproduced images.

In such a horizontal synchronization signal phase error detection device for servo control, if the horizontal synchronization signal is missing due to dropout, the servo will operate to accelerate the rotation speed even if the rotation speed is normal. Furthermore, if unnecessary pulses such as noise-like pulses or equivalent pulses are present between the horizontal synchronization signals, the phases of these unnecessary pulses and the reference signal will be compared, producing an erroneous phase difference signal, which will reduce the speed. The disadvantage is that the servo operates to slow it down, which causes the servo to become significantly distorted.

Therefore, the present invention removes these unnecessary pulses and generates a pseudo synchronization signal by dropout when no horizontal synchronization signal is present, so that good phase error detection is always achieved and a large disturbance in the servo system is avoided. It is an object of the present invention to provide a reproduction horizontal synchronization signal phase error detection device for a lost recorded information reproduction device.

The reproduction horizontal synchronization signal phase error detection device of the present invention uses a reference signal having the same frequency as the horizontal synchronization signal, has a pulse width slightly larger than the pulse width of the reproduction horizontal synchronization signal, and has a pulse width of the reference signal during this pulse period. A gate pulse that includes the generation timing is generated, and when there is a reproduced horizontal sync signal during the existence period of this gate pulse, this reproduced horizontal sync signal (or its inverted signal) is passed through, and when there is no reproduced horizontal sync signal, the gate pulse is passed. It is characterized in that a pulse (or its inverted signal) is allowed to pass through, and the output of this passing signal is used to detect the phase difference with the reference signal.

The present invention will be explained below using the drawings.

FIG. 1 is a circuit block diagram showing one embodiment of the present invention, in which a reproduced horizontal synchronizing signal A that includes noise-like pulses and equivalent pulses and is partially missing due to dropout becomes one input of a NAND gate 1.
This gate output G becomes a trigger input to a monostable multivibrator (hereinafter abbreviated as MMV) 2.
The output H of the MMV2 is phase-compared with a reference signal B in a phase comparator 3, and an error signal is output and used as a predetermined servo control signal. The NAND gate 1 and MMV2 constitute a pulse generating means for generating a signal to be compared with the reference synchronization signal.

As this reference signal B, for example, the duty of 15.75KHz obtained by dividing the output of the oscillator 4, which has twice the frequency of the horizontal synchronization signal, by 1/2 is 50%.
A pulse signal of 1 is used. This duty is 50%
The reference pulse signal B becomes the trigger input of the MMV 6 and one input of the NOR gate 7. this
The output C of MMV6 is used as the other input to NOR gate 7. The output D of the NOR gate 7 is applied to the integration (delay) circuit 8 and integrated (delayed).
This output E becomes the positive phase input of the level comparator 9.
The reference voltage V ₁ is used as the negative phase input,
When the input E becomes higher than this reference voltage _V1 , a high level pulse signal F is obtained. The configuration is such that this pulse signal F is input to the other gate of the NAND gate 1.

FIG. 2 is a waveform diagram of each part in the block of FIG. 1, and in both figures, the same reference numerals indicate waveforms of equivalent parts. The 1/2 frequency divider 5 generates a pulsed reference signal B having the same frequency (15.75KHz) as the horizontal synchronization signal and a duty of 50%. The phase difference is determined successively, but in the present invention, first, the NOR of the output C of the MMV6, which is triggered at each falling timing of this reference pulse B, and the reference pulse B is NORed. As obtained by the gate 7, a pulse train D of a constant width is obtained which rises after a certain period of time from the generation timing (rise) of each reference signal and falls at the generation timing of the next reference signal. Each pulse of this pulse train D is integrated (delayed) by the next-stage integration (delay) circuit 8 to obtain a substantially triangular wave pulse E, which then reaches the reference level.
A pulse train F is generated which becomes high level when the level of the triangular wave pulse becomes higher than this level compared to _V1 . Therefore, by appropriately setting the integration time constant of the integration (delay) circuit 8 and the comparison level _V1 of the comparator 9, each rise (occurrence timing) of the reference pulse B can be included within the high level period. Thus, a gate pulse train F having a pulse width slightly larger than the pulse width of the horizontal synchronizing signal is obtained.

Therefore, it can be seen that by applying this gate pulse F to the NAND gate 1 which receives the reproduction synchronization signal as one input, a waveform as shown in FIG. G becomes the NAND output. That is, if a reproduced horizontal synchronizing signal exists during the existence period of the gate pulse F, this horizontal synchronizing signal is inverted and output, and during that time, due to dropout or the like, the reproduced horizontal synchronizing signal is changed to the dotted line b.
When the gate pulse has not disappeared, as in the case of , the gate pulse is inverted and output. Therefore, the output of MMV2 triggered by the rise of this gate output coincides with the generation timing of the reproduced horizontal synchronizing signal as shown in FIG. H, and the comparator 3 performs a regular phase comparison. If the reproduction horizontal synchronization signal is missing, the rising timing of gate output G, which is the inverted output of gate pulse F, will coincide with the rising timing.
Since the output of MMV2 rises, the output of MMV2, which is slightly delayed from the timing of the original reproduction horizontal synchronization signal, becomes the input of phase comparator 3, and an approximate phase comparison can be performed even without the complete reproduction horizontal synchronization signal. It will be possible to do it.

Furthermore, as shown in a in Figure A, even if unnecessary noise such as pulse-like noise or equivalent pulse exists, as long as it does not exist during the existence period of gate pulse F, these unnecessary pulses are blocked and removed by gate 1. It is something that

As described above, since unnecessary pulses are removed and pseudo pulses are generated even if the horizontal synchronizing signal is absent due to dropout or the like, there is an advantage that servo control can be performed accurately and stably without significant disturbance.

The above block diagram only shows one embodiment.
Of course, various modifications are possible without being limited to this. For example, the polarity of the signal in each part may be made different, and the type of each gate and the comparison input of the comparator may be appropriately controlled and used accordingly.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
2A to 2H are operation waveform diagrams of each part in the block of FIG. 1. Explanation of the symbols of the main parts, 1, 7...gate,
2, 6...MMV, 3...Phase comparator, 9...Level comparator.

Claims (1)

[Claims] 1. A phase error detection device in a recorded information reproducing device that detects a phase difference between a reproduced horizontal synchronizing signal and a reference synchronizing signal having the same frequency as the horizontal synchronizing signal to generate a control signal for a predetermined servo circuit. means for generating the reference synchronization signal, the reference synchronization signal having a pulse width slightly larger than the pulse width of the reproduced horizontal synchronization signal, and the reproduction horizontal synchronization signal within the pulse width; means for generating a gate pulse having a generation timing; and when the reproduction horizontal synchronization signal exists during the existence period of the gate pulse, a signal having the same generation timing as the generation timing of the reproduction horizontal synchronization signal; and pulse generating means for outputting a signal having the same generation timing as the end timing of the gate pulse when the reproduced horizontal synchronizing signal does not exist during the existence period of the gate pulse; and the output signal of the pulse generating means and the 1. A phase error detection circuit in a recorded information reproducing apparatus, comprising: phase comparison means for detecting a phase difference with a reference synchronization signal.