JPH0475708B2 - - Google Patents
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- Publication number
- JPH0475708B2 JPH0475708B2 JP58141724A JP14172483A JPH0475708B2 JP H0475708 B2 JPH0475708 B2 JP H0475708B2 JP 58141724 A JP58141724 A JP 58141724A JP 14172483 A JP14172483 A JP 14172483A JP H0475708 B2 JPH0475708 B2 JP H0475708B2
- Authority
- JP
- Japan
- Prior art keywords
- flop
- flip
- field
- output
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000002131 composite material Substances 0.000 claims description 13
- 230000000737 periodic effect Effects 0.000 claims description 11
- 238000000926 separation method Methods 0.000 claims description 11
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 6
- 230000000903 blocking effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Description
【発明の詳細な説明】
(イ) 産業上の利用分野
本発明はVTRにおけるサーボ回路の制御の誤
動作を防止するフイールド判別装置に係わる。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a field discrimination device that prevents malfunctions in controlling a servo circuit in a VTR.
(ロ) 従来例
一般に映像情報の磁気記録再生を行うVTRに
おいて、記録時磁気テープ１にはテープは左方向
に走行しているとき、ビデオヘツドは斜め左上に
向つて各映像トラツクＡ、A′、Ｂ、B′……に映
像信号を記録すると共に、コントロールトラツク
には第２図に示すように前記フイールド毎にコン
トロール信号を垂直同期分離した信号を用いてビ
デオトラツク幅に相当するピツチで記録する。(B) Conventional example In a VTR that generally records and reproduces video information magnetically, when the magnetic tape 1 is running to the left during recording, the video head moves diagonally to the upper left to track each video track A, A'. , B, B'..., and record the control signal on the control track at a pitch corresponding to the video track width using a signal obtained by separating the control signal in vertical synchronization for each field, as shown in Fig. 2. do.
ここでＡ、A′という情報からＢ、B′という情
報のつなぎ録りを行おうとするとき、前記コント
ロール信号は、垂直同期信号の1/2の周期で発生
し、該垂直同期信号の位置が所定の位置に存在
し、又A′とＢとのフイールド関係が第１と第２
もしくは第２と第１フイールドのように継つた場
合は、再生画面上画質的な乱れは全く除去するこ
とができる。 When trying to record information B and B' from information A and A', the control signal is generated at half the period of the vertical synchronization signal, and the position of the vertical synchronization signal is exists at a predetermined position, and the field relationship between A' and B is the first and second field.
Alternatively, if the second and first fields are continuous, any disturbance in image quality on the playback screen can be completely eliminated.
ところがA′とＢとのフイールド関係が同一フ
イールドで継つた場合、A′とＢとでＨ水平周期
信号の連続性が1/2Ｈずれることになり、テレビ
画面上部で曲りを生ずるスキユー歪が発生する。 However, if the field relationship between A' and B continues in the same field, the continuity of the H horizontal periodic signal between A' and B will shift by 1/2H, causing skew distortion that causes distortion at the top of the TV screen. do.
そこで従来第３図に示す如く、つなぎ録りの際
には、フイールド合せをすることが要求されるこ
とから、複合同期信号供給手段１から垂直同期分
離回路２に複合同期信号（第１フイールドの場合
第４図イ、第２フイールドの場合第４図ニ）を加
えると、1/2Ｈ阻止回路３を介して水平周期信号
発生回路４から水平周期連続信号（第１フイール
ドに対しては第４図ロ、第２フイールドに対して
は第４図ホが現われる。 Conventionally, as shown in FIG. 3, it is required to match the fields during continuous recording, so the composite synchronization signal (first field In the case of FIG. 4A, and in the case of the second field, FIG. 4D) is added, the horizontal periodic continuous signal (for the first field, the Figure B and Figure 4 E appear for the second field.
従つて前記第４図ロ及びハに示された電圧を
ANDゲート５に、一方第４図ホ及びヘに示す電
圧が複合ゲート６に加えられるので、その出力が
Ｓ−Ｒフリツプフロツプ７に加えられ、その出力
端子８から第４図トに示した出力即ち第１図に示
した第１フイールドに対応する期間はハイ（Ｈ）
レベル、第２フイールドに対応する期間はロ−
（Ｌ）レベルの判別出力が現われる。この信号を
用いて、サーボ系を制御し、またコントロール信
号を記録することにより、つなぎ撮り時に発生す
るスキユー歪をなくすことが可能となる。 Therefore, the voltages shown in FIG.
The voltages shown in FIG. 4E and F are applied to the AND gate 5, while the voltages shown in FIG. The period corresponding to the first field shown in Figure 1 is high (H).
level, the period corresponding to the second field is low.
(L) Level discrimination output appears. By using this signal to control the servo system and recording the control signal, it is possible to eliminate skew distortion that occurs during continuous shooting.
ところが第４図ヘの破線で示すように、垂直同
期分離回路２において外来ノイズや弱電界による
影響で、所定の位置からずれた位置に垂直同期信
号が現われると、前記ゲート６からの出力が現わ
れず、これに伴つて第２フイールドの期間になつ
てもS′−Ｒフリツプフロツプ７が反転しないの
で、第４図トの破線で示す通り、第２フイールド
の期間でもハイ（Ｈ）レベルの出力が端子８から
現われ、従つて垂直同期信号を1/2に分周するこ
とができなくなる。 However, as shown by the broken line in FIG. 4, when the vertical synchronization signal appears at a position shifted from the predetermined position in the vertical synchronization separation circuit 2 due to the influence of external noise or a weak electric field, the output from the gate 6 appears. As a result, the S'-R flip-flop 7 does not invert even during the second field period, so the high (H) level output remains even during the second field period, as shown by the broken line in FIG. It appears from terminal 8, so it becomes impossible to divide the vertical synchronizing signal into 1/2.
斯る信号がサーボ回路（図示せず）に導かれる
と、キヤプスタン及びシリンダサーボ系が大きく
乱れて誤動作し再生時の画面の乱れの原因とな
る。 When such a signal is guided to a servo circuit (not shown), the capstan and cylinder servo systems are greatly disturbed and malfunction, causing screen disturbances during playback.
(ハ) 発明の目的
本発明は、従来のつなぎ録り時のフイ−ルド判
別出力をフイールド毎に確実に反転させ、サーボ
系の乱れによる誤動作を除去し、再生時の画面の
乱れを防止することを目的とする。(c) Purpose of the Invention The present invention reliably inverts the field discrimination output for each field during conventional continuous recording, eliminates malfunctions due to disturbances in the servo system, and prevents screen disturbances during playback. The purpose is to
(ニ) 発明の構成
本発明は、複合同期信号供給手段と、垂直同期
分離回路と、1/2Ｈ阻止回路と、水平周期信号発
生回路と、前記垂直同期信号分離回路及び水平周
期信号発生回路の各出力側に接続した第１及び第
２の論理積手段と、該第１及び第２の論理積手段
の出力側を一方は直接、他方は遅延回路を介して
Ｓ−Ｒフリツプフロツプの入力端子にそれぞれ接
続し、該Ｓ−Ｒフリツプフロツプの出力端子と前
記ANDゲートの出力端を第３のANDゲートの入
力に接続し、その出力をＴーフリツプフロツプの
入力端子に接続し、該Ｔーフリツプフロツプの出
力端子よりフイールド判別パルスを導出する構成
である。(D) Structure of the Invention The present invention provides a composite synchronization signal supply means, a vertical synchronization separation circuit, a 1/2H blocking circuit, a horizontal periodic signal generation circuit, and a combination of the vertical synchronization signal separation circuit and the horizontal periodic signal generation circuit. First and second AND means connected to each output side, and one output side of the first and second AND means connected directly to the input terminal of the S-R flip-flop, and the other side connected to the input terminal of the S-R flip-flop through a delay circuit. The output terminal of the S-R flip-flop and the output terminal of the AND gate are connected to the input terminal of a third AND gate, and the output thereof is connected to the input terminal of the T-flip-flop. The configuration is such that a field discrimination pulse is derived from the output terminal of a flip-flop.
(ホ) 実施例
図面に従つて本発明を説明すると、第５図は本
発明のVTRのフイールド判別装置を示すブロツ
ク図、第６図は同装置のダイミングチヤートを示
し、第５図において、第３図における素子と同一
のものについては同一図番を付してある。(E) Embodiments The present invention will be explained with reference to the drawings. FIG. 5 is a block diagram showing a field discriminating device for a VTR according to the present invention, FIG. 6 is a dimming chart of the same device, and in FIG. Elements that are the same as those in FIG. 3 are given the same figure numbers.
第５図において、９は遅延回路、１０はAND
ゲートで、その入力側に前記ANDゲート５及び
複合ゲート６の出力側が接続されており、１１は
Ｔ−フリツプフロツプで、Ｔ端子に前記垂直同期
分離回路２の出力側が、Ｒ端子に前記ANDゲー
ト１０の出力側が接続され、該Ｔ−フリツプフロ
ツプ１１のＱ端子に出力端子１２が設けられてい
る。 In Figure 5, 9 is a delay circuit, 10 is an AND
The output side of the AND gate 5 and the composite gate 6 are connected to the input side of the gate, and 11 is a T-flip-flop, the output side of the vertical synchronization separation circuit 2 is connected to the T terminal, and the output side of the AND gate 10 is connected to the R terminal. An output terminal 12 is connected to the Q terminal of the T-flip-flop 11.
次に本発明の動作について、第６図のタイミン
グチヤートを用いながら説明する。第６図におい
てイは第２フイールドに相当するフイールドパル
ス、ロは第１フイールドに相当するフイールドパ
ルス、ハはＲ−Ｓフリツプフロツプ７のＱ出力、
ニはＴ−フリツプフロツプ１１のＴ端子入力、(ホ)
はANDゲート１０の出力、(ヘ)はＴ−フリツプフ
ロツプ１１の出力を示す。 Next, the operation of the present invention will be explained using the timing chart shown in FIG. In FIG. 6, A is the field pulse corresponding to the second field, B is the field pulse corresponding to the first field, C is the Q output of the R-S flip-flop 7,
D is the T terminal input of T-flip-flop 11, (E)
indicates the output of the AND gate 10, and (f) indicates the output of the T-flip-flop 11.
前記タイミングチヤートにおいて、最初の３垂
直期間は正常入力を示し、タイミングa2では第１
フイールドパルスを検出すべきところ、第２フイ
ールドパルスとなつてしまつた場合、タイミング
b5では第２フイールドパルスを検出すべきとこ
ろ、第１フイールドパルスを検出してしまつた場
合を示してある。 In the above timing chart, the first three vertical periods show normal input, and at timing a2 , the first
If the field pulse should be detected but becomes the second field pulse, the timing
b 5 shows a case where the first field pulse was detected when the second field pulse should have been detected.
今第５図において入力端子１３に複合映像信号
が加わり、複合同期信号供給手段１から得られた
複合同期信号から垂直同期分離回路にて垂直同期
信号を導出し、複合ゲート６に加える。一方前記
複合同期信号回路１の出力は1/2Ｈ阻止回路３に
よつて等化パルス期間における1/2Ｈ信号を除去
し、水平周期信号発生回路４から、水平周期連続
信号を導出し、ANDゲート５に加え、一方垂直
同期分離回路２からは、垂直同期信号が導出さ
れ、複合ゲート６に加えられる。 Now, in FIG. 5, a composite video signal is applied to the input terminal 13, and a vertical synchronization signal is derived from the composite synchronization signal obtained from the composite synchronization signal supply means 1 in the vertical synchronization separation circuit and applied to the composite gate 6. On the other hand, the output of the composite synchronization signal circuit 1 is passed through a 1/2H blocking circuit 3 to remove the 1/2H signal during the equalization pulse period, and a horizontal periodic continuous signal is derived from the horizontal periodic signal generation circuit 4, which is then gated by an AND gate. 5, a vertical synchronization signal is also derived from the vertical synchronization separation circuit 2 and applied to the composite gate 6.
ここでANDゲート５の出力は、水平周期連続
信号及び垂直同期信号が共にハイＨレベル期間の
みに現われ、一方複合ゲート６の出力は、前記水
平周期連続信号の反転信号と垂直同期信号がハイ
Ｈレベルのときのみに現われる。前記ANDゲー
ト５の出力は時間Td分遅延回路９にて遅延され、
前者が第２フイールド、後者が第１フイールド用
の各パルスとして生成され、これらによりＲ−Ｓ
フリツプフロツプ７はセツト又はリセツトされ
る。その結果前記Ｒ−Ｓフリツプフロツプ７は第
６図ハに示す通り、第２フイールドパルス（第６
図イ）のb1で立上り（セツトされ）、次に第１フ
イールドパルス（第６図ロ）のa1から遅延回路９
にて遅延時間（Td）後立下り（リセツトされ）、
再び第２フイールドパルスb2にて立上り（セツト
され）、仮に第１フイールドパルスのパルスa2が
弱電界の影響等によつて欠落した場合でもハイＨ
レベルを保ち、第１フイールドパルスa3のTd分
遅延されたタイミングにて立下る（リセツトされ
る。 Here, the output of the AND gate 5 appears only when both the horizontal periodic continuous signal and the vertical synchronizing signal are at a high H level, while the output of the composite gate 6 is such that the inverted signal of the horizontal periodic continuous signal and the vertical synchronizing signal are both at a high H level. Appears only when level. The output of the AND gate 5 is delayed by a delay circuit 9 by a time Td,
The former is generated as a pulse for the second field, and the latter is generated as a pulse for the first field, and these generate R-S
Flip-flop 7 is set or reset. As a result, the R-S flip-flop 7 receives the second field pulse (sixth field pulse) as shown in FIG.
It rises (is set) at b 1 in Figure A), and then from a 1 of the first field pulse (Figure 6 B) to delay circuit 9.
falls (resets) after delay time (Td) at
It rises (sets) again at the second field pulse b2 , and remains high even if pulse a2 of the first field pulse is lost due to the influence of a weak electric field, etc.
It maintains the level and falls (reset) at a timing delayed by Td of the first field pulse a3 .
このときＴ−フリツプフロツプ１１のＴ端子は
第６図ニに示す如く垂直同期信号が印加されてお
り、またANDゲート１０の出力は第６図ホに示
す波形となり、第２フイールドパルスが入力され
た次の第１フイールドパルスでハイＨレベルとな
る。従つてＴ−フリツプフロツプ１１のリセツト
はかかることなく、垂直同期パルス（第６図ホ）
がＴ端子に入力される毎に反転を繰返し、出力端
子１２からは判別出力（第６図ヘの方形波）が現
われる。 At this time, a vertical synchronizing signal is applied to the T terminal of the T-flip-flop 11 as shown in FIG. 6D, and the output of the AND gate 10 has the waveform shown in FIG. The next first field pulse becomes a high H level. Therefore, the T-flip-flop 11 is not reset, and the vertical synchronizing pulse (FIG. 6)
is repeatedly inverted each time it is input to the T terminal, and a discrimination output (the square wave in FIG. 6) appears from the output terminal 12.
前述の第６図ロで第１フイールドパルスの中で
a2の欠落を説明したが、第２フイールドパルスの
中でb3，b4の次のb5が欠落した場合も、Ｒ−Ｓフ
リツプフロツプ７はロ−Ｌレベルを保持したまま
で反転せず、前述と併せて、フイールド判別時に
何らかの異常が発生し、第１フイールドパルス、
第２フイールドパルスが順次選択されない場合で
も恰も判別パルスとして出力が現われる。 In the first field pulse in Figure 6B above,
As explained above about the omission of a2 , even if b5 , which follows b3 and b4 , is omitted in the second field pulse, the R-S flip-flop 7 remains at the low-L level and does not invert. , In addition to the above, some abnormality occurs during field discrimination, and the first field pulse,
Even if the second field pulses are not selected sequentially, the output appears as a discrimination pulse.
従つて斬る出力をサーボシステム回路に加えれ
ば、安定した記録、再生が行える。 Therefore, by applying the cutting output to the servo system circuit, stable recording and playback can be performed.
(ヘ) 発明の効果
本発明によれば、弱電界等の影響により、フイ
ールドパルスの一部が欠落し、第１フイールドパ
ルスと第２フイールドパルスが順次選択されない
場合でもフイールド判別パルスは所定の極性にて
現われ、従来のようにサーボ系の乱れは未然に防
止できると共に画面の乱れを生じることもない。(f) Effects of the Invention According to the present invention, even if a part of the field pulse is missing due to the influence of a weak electric field or the like and the first field pulse and the second field pulse are not selected sequentially, the field discrimination pulse can be set to a predetermined polarity. Therefore, disturbances in the servo system can be prevented from occurring, unlike in the conventional case, and there is no disturbance in the screen.
第１図はVTRのフイールド判別装置を説明す
るための説明図、第２図はコントロールパルス波
形、第３図は従来のVTRのフイールド判別装置
を示すブロツク図、第４図は第３図における同装
置のタイミングチヤート、第５図は本発明の同装
置のブロツク図、第６図は第５図における同装置
のタイミングチヤートを示す。
主な図番の説明
１……複合同期信号供給手段、２……垂直同期
分離回路、３……1/2Ｈ阻止回路、４……水平周
期信号発生回路、５，１０……ANDゲート、６
……複合ゲート、７……Ｓ−Ｒフリツプフロツ
プ、９……遅延回路、１１……Ｔ−フリツプフロ
ツプ、１２……出力端子。
Fig. 1 is an explanatory diagram for explaining a VTR field discrimination device, Fig. 2 is a control pulse waveform, Fig. 3 is a block diagram showing a conventional VTR field discrimination device, and Fig. 4 is the same as in Fig. 3. FIG. 5 is a block diagram of the same device of the present invention, and FIG. 6 is a timing chart of the same device in FIG. 5. Explanation of main figure numbers 1...Composite synchronization signal supply means, 2...Vertical synchronization separation circuit, 3...1/2H blocking circuit, 4...Horizontal periodic signal generation circuit, 5, 10...AND gate, 6
...Composite gate, 7...S-R flip-flop, 9...delay circuit, 11...T-flip-flop, 12...output terminal.
Claims (1)
と、1/2Ｈ阻止回路と、水平周期信号発生回路と、
前記垂直同期分離回路及び水平周期信号発生回路
の各出力側に接続した第１及び第２の論理積手段
と、該第１、第２の論理積手段の一方の出力側に
入力端子のセツト側が接続された他の出力側に遅
延回路を介してリセツト側に接続されたＳ−Ｒフ
リツプフロツプと、該Ｓ−Ｒフリツプフロツプの
出力端子及び前記論理積手段の他方の出力側がそ
の入力側に接続された第３の論理積手段と、前記
垂直同期分離回路の出力側及び前記第３の論理積
手段の出力側が接続されたＴ−フリツプフロツプ
とより成り、該Ｔ−フリツプフロツプの出力端子
よりフイールド判別パルスを導出することを特徴
としたVTRのフイールド判別装置。 ２ 特許請求の範囲第１項において、前記垂直同
期分離回路の出力端を前記Ｔ−フリツプフロツプ
のＴ端子に、前記第３の論理積の出力端を前記Ｔ
−フリツプフロツプのＲ端子に接続し、前記Ｔ−
フリツプフロツプの出力端よりフイールド判別パ
ルスを導出することを特徴としたVTRのフイー
ルド判別装置。[Claims] 1. Composite synchronization signal supply means, vertical synchronization separation circuit, 1/2H blocking circuit, horizontal periodic signal generation circuit,
first and second AND means connected to each output side of the vertical synchronization separation circuit and the horizontal periodic signal generation circuit; and a set side of an input terminal on one output side of the first and second AND means. An S-R flip-flop is connected to the other output side connected to the reset side via a delay circuit, and the output terminal of the S-R flip-flop and the other output side of the AND means are connected to the input side thereof. It consists of a third AND means, and a T-flip-flop to which the output side of the vertical synchronization separation circuit and the output side of the third AND means are connected, and a field discrimination pulse is derived from the output terminal of the T-flip-flop. A VTR field discrimination device that is characterized by: 2. In claim 1, the output terminal of the vertical synchronization separation circuit is connected to the T terminal of the T-flip-flop, and the output terminal of the third logical product is connected to the T terminal of the T-flip-flop.
- connected to the R terminal of the flip-flop, and said T-
A VTR field discrimination device characterized by deriving a field discrimination pulse from the output end of a flip-flop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58141724A JPS6032492A (en) | 1983-08-01 | 1983-08-01 | Field discriminating device of vtr |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58141724A JPS6032492A (en) | 1983-08-01 | 1983-08-01 | Field discriminating device of vtr |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6032492A JPS6032492A (en) | 1985-02-19 |
| JPH0475708B2 true JPH0475708B2 (en) | 1992-12-01 |
Family
ID=15298725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58141724A Granted JPS6032492A (en) | 1983-08-01 | 1983-08-01 | Field discriminating device of vtr |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6032492A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4651867B2 (en) * | 2001-06-20 | 2011-03-16 | 株式会社アルファシビルエンジニアリング | Cutting edge drilling equipment |
-
1983
- 1983-08-01 JP JP58141724A patent/JPS6032492A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6032492A (en) | 1985-02-19 |
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