JPH03792Y2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a video signal processing device, and particularly to a video signal processing device that can obtain high quality frame-by-frame images without noise.

Prior art and its problems In a helical scanning VTR, during variable speed playback, a recorded magnetic tape is run (or stopped) at a tape running speed different from that during recording and the recorded video signal is played back. It is well known that since the relative speed between the tape and the head is different from that during recording, the head scanning locus is drawn at a different slope from the recording track trace. For this reason, adjacent tracks are recorded by rotary heads having gaps with different azimuth angles, and there is a track pattern in which there is no guard band or only a very small guard band is formed between the tracks. During variable-speed reproduction of a magnetic tape, the reproducing rotary head performs one track scanning period by recording a track recorded by a rotary head having a gap of the same azimuth angle and by a rotary head having a gap having a different azimuth angle. The recorded tracks (reverse tracks) are scanned alternately, and therefore, during reverse track scanning, the reproduced signal level becomes extremely low due to the azimuth loss effect and the S/N ratio deteriorates. Similarly, during variable speed reproduction of a magnetic tape with a track pattern in which a guard band of a sufficient constant width is formed between adjacent tracks, the guard band is crossed more than once per track scanning period. During guard band scanning, the reproduced signal level becomes extremely low and the S/N ratio deteriorates.

Here, if the variable speed playback described above is frame-by-frame playback in which still images are sequentially obtained from arbitrary different recording tracks on the tape, in addition to the deterioration of the S/N ratio of the playback signal, Precise service regarding tape feeding, etc. to drive noise outside the effective screen.
However, it was difficult to completely eliminate the noise from the screen, and it sometimes appeared on the screen as well.

Therefore, the present invention alternately writes the reproduced composite video signal into one of the two field memories and reads out the reproduced composite video signal one field before the other during frame-by-frame playback, and also writes the reproduced composite video signal into one of the two field memories. The field in the section where the level is extremely low can be read out from one side of the field memory by reading out the reproduced composite video signal of the immediately preceding field that does not have the section where the reproduced FM signal level is extremely low. An object of the present invention is to provide a video signal processing device that solves the above problems.

Means for Solving the Problems The present invention provides an AD converter for converting a composite video signal, which is reproduced from a recording medium in a signal form having at least FM waves and then demodulated, into a digital video signal; The first and second field memories supplied, a switch means for selectively outputting an output digital video signal of the field memory undergoing a read operation, and an output digital video signal of the switch means. A detection signal indicating a reproduction period during which the level of the FM wave reproduced from the recording medium is lower than a certain value is supplied, and when the detection signal is received, no subsequent detection signal is received. in the first and second field memories at the time when the detection signal is received, and until a total of two vertical synchronization pulses in the output digital video signal of the switch means are detected in succession. The write operation on one side and the read operation on the other side are continued, and during the period after the continuation until the next detection signal comes in, the AD is stored in one of the first and second field memories.
memory control means that alternately writes the output digital video signal of the converter and reads the digital video signal one field before the other memory from the other memory for each field;
and output means for obtaining a reproduced composite video signal output from the output signal of the switch means,
One embodiment will be described below with reference to the drawings.

Embodiment FIG. 1 shows a block diagram of an embodiment of the device of the present invention. In the figure, an input terminal 1 receives a reproduced composite color video signal. This reproduced composite color video signal is produced by, for example, frequency modulating (FM) the luminance signal, frequency converting the carrier chrominance signal to a low frequency band, frequency division multiplexing of these two signals, and transmitting one file to one track by a rotating head. - The magnetic tape recorded on successive tracks is played back at variable speeds at a rate of 1.5 - 1.5 seconds. This is a reproduced composite color video signal obtained by multiplexing these two signals and substantially conforming to the standard method.

The above-mentioned reproduced composite color video signal, which is reproduced in a signal form having at least FM waves and demodulated, which has entered the input terminal 1, is supplied to the AD converter 2, where it is analog-to-digital converted and converted into a digital video signal. After being made into a signal, it is supplied to the first and second field memories 3 and 4, respectively. Fee
The readout output digital video signal from the field memory 3 or 4 is selectively outputted by the bus line controller 5 and supplied to the timing control circuit 6 and the DA converter 11. The timing control circuit 6 is supplied with an output digital video signal from the bus line controller 5 and a detection signal from an input terminal 8, as will be described later. This detection signal is at a high level, for example, during a period when the amplitude of the FM luminance signal reproduced from the rotating head that is scanning the magnetic tape becomes smaller than a certain value due to reverse track scanning, and when the amplitude exceeds this certain value. This is a binary signal generated to be at a low level. The timing control circuit 6 outputs a pulse whose phase is synchronized with the detection signal to the second timing control circuit 9 from the output terminal 7a.

Further, the timing control circuit 6 outputs the horizontal synchronization pulse from which the equalization pulse and the vertical synchronization pulse have been removed from the output terminal 7b and supplies it to the timing control circuit 9, while the vertical synchronization pulse is obtained by waveform shaping from the output terminal 7c. A pulse is output and supplied to the address signal generation circuit 10. The timing control circuit 9 generates a signal controlled by the color subcarrier frequency based on the signal from the terminal 7a and supplies it to the bus line controller 5 to control its switching. necessary for reading and writing to field memories 3 and 4.
CAS (column address strobe) signal, RAS
(row address strobe) signal, WE (read/
It generates write control signals and supplies them to the field memories 3 and 4, respectively, and also outputs signals to the address signal generation circuit 10. Address signal generation circuit 10 generates address signals and supplies them to field memories 3 and 4, respectively. The field memories 3 and 4 are each, for example, a random access memory (RAM), which has a storage capacity capable of storing one field's worth of digital video signals. The other side is controlled to perform a write operation and the other side to perform a read operation, and the read output signal (digital video signal) is supplied to the bus line controller 5 and the AD converter 2.
Writes the digital video signal extracted by. The DA converter 11 converts the input digital video signal from digital to analog to convert it back into a composite color video signal, which is an analog signal, and outputs it to the output terminal 12.

Here, the above-mentioned bus line controller 5 selects and outputs the readout output digital video signal of the field memory which is performing the readout operation among the field memories 3 and 4.
Switching is controlled by the output signal of the timing control circuit 9. Further, the detection signal from the input terminal 8 is a signal indicating, for example, a high level, a reproduction period in which the level of the FM wave reproduced from the recording medium (here, magnetic tape) is lower than a certain value. is as described above. As will be described later, the field memories 3 and 4 are connected to the bus when the detection signal is received (becomes high level) and when the detection signal is no longer received (becomes low level). The write operation and the read operation at the time of input of the detection signal are controlled to continue until two consecutive vertical synchronization pulses are detected in the output digital video signal of the line controller 5. Also, the period after this continuation until the next detection signal comes in (period of low level)
In this case, one of the field memories 3 and 4 writes the digital video signal from the AD converter 2, and the other reads the digital video signal one field before that, which is alternately repeated for each field. It is controlled by both output signals of the timing control circuit 9 and the address signal generation circuit 10.
As a result, a high-quality frame-by-frame image without deterioration of the S/N ratio can be obtained at the output terminal 12.

The field memories 3 and 4 and the bus line controller 5 are controlled by the output signals of the timing control circuit 9 and the address signal generation circuit 10, but the reference signal is generated by the timing control circuit 6. Next, the configuration and operation of the timing control circuit 6, which is a signal and constitutes a main part of the present invention, will be explained in more detail.

FIG. 2 shows a circuit diagram of one embodiment of the timing control circuit 6. As shown in FIG. In the figure, the same components as in FIG. 1 are designated by the same reference numerals. In FIG. 2, the bus line controller 5 that has entered the input terminal 15
The digital video signal is supplied to a horizontal synchronizing pulse extraction circuit 16, and is also supplied to a vertical synchronizing pulse extraction circuit 17, where a vertical synchronizing pulse is extracted to form the pulse shown at a in FIG. 3. This vertical synchronizing pulse a is applied to a two-input OR circuit 2, which will be described later.
On the other hand, it is supplied to one input terminal of the waveform shaping circuit 18, where its rising edge is detected and the pulse width (low-level period) is narrow and constant width as shown in FIG. - after being converted into a pulse c with a period of
It is applied to the clear terminal CLR of the J-K flip-flop (hereinafter referred to as J-KF.F.) 20 and is cleared at its falling edge.

On the other hand, the detection signal b shown in FIG. 3 that has entered the input terminal 8 is supplied to a waveform shaping circuit 19. Here, as an example, the detection signal b is detected during the period from time t ₁ to time _{t 2 (} this is one frame in which the digital video signal of the fourth field is output from the AD converter 2), as shown by b 1 in FIG. - a period smaller than one field within the field period) and time t ₇ ~ as shown by b ₂ in the same figure.
The period t ₅ (this is a period smaller than one field within one field period during which the digital video signal of the sixth field is output from the AD converter 2) and b ₃ in the same figure. As shown in , the period from time t ₆ to time _{t 7} (this is the period during which the digital video signal from approximately the second half of the sixth field to approximately the first half of the seventh field is output from the AD converter 2). It is assumed that each of the following conditions is entered (becomes at a high level). The numbers in the brackets above the waveform of the vertical synchronizing pulse a in Figure 3 indicate the field order of the output digital video signal of the AD converter 2, that is, the field of the composite video signal currently being reproduced from the recording medium. The numerical values in the waveform of the vertical synchronizing pulse a indicate the order contents of the playback field of the output digital video signal of the bus line controller 5, which is controlled as described later.

The rising edge and falling edge of the above detection signal b are detected by the waveform shaping circuit 19 and converted into extremely narrow pulses as shown by d in FIG. is applied to J-KF.F20 has its J terminal connected to the positive DC voltage V _CC input terminal, and its K terminal connected to its output terminal. Therefore, J
- After KF/F20 is cleared by the vertical synchronization pulse detection pulse c, the output signal of its Q output terminal remains at a low level (clear state) unless pulse d is input to its clock terminal. In addition, the output is inverted at the time of the first pulse d that comes in in the clear state, and even if the second and subsequent pulses d come in, the output remains unchanged until the next pulse c comes in. The output signal of the Q output terminal maintains a high level state.

Therefore, _the Q output signal of J-KF.F20 rises at times t ₁ , t _{4 ,} t ₇ as shown by e in FIG.
The waveform becomes a falling waveform (square wave) at the time of arrival of the first pulse c after each time _t7 . This Q output signal e is
It is supplied to the other input terminal of the OR circuit 21, where it is logically summed with the vertical synchronizing pulse a and shown as f in FIG.
After being converted into a signal shown in , it is applied to the clock terminal of J-KF.F22. J-KF.F22 is that J
Since the terminal and the K terminal are each connected to the input terminal of the positive DC voltage Vcc, a high level signal is always applied to the J terminal and the K terminal, respectively. Therefore, the output of the J-KF.F22 is inverted every time the rising edge of the signal f is input to its clock terminal, and the output from its Q output terminal to the output terminal _7a1 as shown in FIG. A pulse g is outputted, and a pulse as shown in FIG. 3 is outputted from the output terminal to the output terminal _7a2 .

The output terminals 7a ₁ and 7a ₂ are terminals corresponding to the output terminal 7a shown in FIG.
g are respectively supplied to the timing control circuit 9 in parallel. The high level period of the pulse g, approximately corresponds to the readout period of the field memories 3 and 4, and the high level period of the pulse g,
The low level period approximately corresponds to the write period of the field memories 3 and 4.

On the other hand, the horizontal synchronizing pulse waveform extracted by the horizontal synchronizing pulse extracting circuit 16 is converted by the wave rectifying circuit 23 into a pulse whose phase is synchronized with the rising edge portion of the horizontal synchronizing pulse, for example, and then supplied to the sampling circuit 24 . Here, at the output end of the horizontal synchronization pulse extraction circuit 16,
In addition to the horizontal synchronization pulse, an equalization pulse and a vertical synchronization pulse are also taken out during the vertical blanking period. Therefore, the sampling circuit 24 removes the equalization pulse and the vertical synchronizing pulse, extracts only the pulse that is phase-synchronized with the horizontal synchronizing pulse at 1H intervals, and outputs it as a timing signal to the timing control circuit 9 from the output terminal 7b. Note that the extraction circuit 24 becomes unnecessary if the horizontal synchronization pulse extraction circuit 16 is provided with that function.

The timing signal taken out from the output terminal 7b is supplied to the timing control circuit 9 shown in FIG. 1 together with the pulse g taken out from the output terminals 7a ₁ and 7a ₂ . Based on the clock pulse whose repetition frequency is equal to the color subcarrier frequency _S and the timing signal from the terminal 7b, the timing control circuit 9 causes the clock pulse to rise in phase synchronization with, for example, the rising edge of the clock pulse as shown in FIG. A signal j with a waveform is generated. Here, terminal 7
The timing signal from b comes in every 1H (=227.5/ _S ), but since the color subcarrier frequency _S is 227.5 times the horizontal scanning frequency _H , the phase is reversed every 1H, but the above If a signal j is generated that rises only in phase synchronization with the rising edge of a clock pulse having a repetition frequency _S , the phase of the color subcarrier and the phase of the rising edge of the signal j will always have the same relationship. Thus, the time interval from any rising edge to the next rising edge of signal j is
227/ _S or 228/ _S .

The timing control circuit 9 generates the above signal j and supplies it to the clock input terminal of the D-type flip-flop inside _the circuit 9, and also outputs _the input pulse g( or)
is applied to the data input terminal of the D-type flip-flop, and the flip-flop outputs a signal k as shown in FIG. This signal k is applied to the field memories 3 and 4 shown in FIG.
and is generated and output as a control signal for the bus line controller 5. During the low level period of the signal k, the field memory 3 is operated for writing and the field memory 4 is operated for reading, and the bus line controller 5 is used to select the output of the field memory 4. Switch to state. On the other hand, during the high level period of the signal k, the field memory 3 is operated for reading, the field memory 4 is operated for writing, and the bus line controller 5 is switched to the output selection output state of the field memory 3.

The signal k has substantially the same signal waveform as the pulse g as described above, and has the same signal waveform if the phase of the color subcarrier is not considered. Therefore, for convenience of explanation, the high level period and low level period of the pulse g are read out from the field memories 3 and 4,
Assuming that the period corresponds to writing, the field memory 3 is controlled so that the writing operation is performed during the low level period of the pulse g shown in FIG. 3, and the reading operation is performed during the high level period.
Similarly, the field memory 4 performs a write operation during the low level period of the pulse shown in FIG.
The read operation is controlled to be performed during the high level period.

As mentioned above, the pulse g is a pulse that is inverted every time the rising edge of the OR output pulse f of the vertical synchronizing pulse a and the pulse e arrives, and at time t ₁
When the detection signal b ₁ comes in, the detection signal b ₁ comes after that.
In the detection signal non-incoming time period after time t ₂ when the vertical synchronizing pulse a is no longer received, the period until the second time t ₃ when the vertical synchronizing pulse a is detected twice in succession is as follows:
Pulse g at time t ₁ when detection signal b ₁ arrives,
The logical value of g is held as it is and is inverted at time _t3 . Therefore, the field memory 3 starts writing the digital video signal of the fourth field from the time when the vertical synchronization pulse is input immediately before time _t1 .
Moreover, assuming that the field memory 4 has started the read operation of the digital video signal of the third field, the field memory 3 continues the write operation until time t ₃ and writes W ₄ and W ₅ at g in FIG. As shown, the digital video signals of the fourth field and the fifth field are sequentially written, while the field memory 4 continues the read operation, and the digital video signal of the third field is repeatedly written for two field periods as shown by _R3 in the third field. and read it out.

In addition, the detection signal b ₂ comes in at time t ₄ and stops coming in at time _{t 5} , but before the time when the first vertical synchronization _pulse is detected in the time period after time t ₅ . At time _t6 , the detection signal _b3 enters again, and at time _t7 , the detection signal b3 disappears. Then, in the detection signal non-incoming time period after time _t7 , the vertical synchronization pulse a is detected twice in succession at time _t8 . Therefore, pulse g, changes the logical value at time _t4 to time
It is held until t ₈ and reversed at time t ₈ . Therefore, as shown by _R5 in g in FIG. 3, the field memory 3 stores the signal written immediately before during the three field periods from time _t3 when the vertical synchronizing pulse arrives immediately before time _t4 to time _t8 . The undegraded digital video signal of the fifth field is read out three times, while the field memory 4 is read out as shown in _FIG .
The digital video signals of the _6th , 7th, and _8th fields from the AD converter 2 are sequentially written as shown by W 7 and W 8 .

Here, as is well known, field memories 3 and 4
Since each has a storage capacity of only one field,
The previously stored digital video signal for one field is erased by the digital video signal for one field written next, and only the digital video signal for one field written next remains. ，
The stored contents of No. 4 are updated sequentially, and become the latest digital video signal for one field immediately before switching to the read operation. Therefore, even if the field memory 3 writes the digital video signal of the fourth field with a degraded S/N ratio, at time _t3 when the read operation is started, the digital video signal of the next fifth field without a degraded S/N ratio is written. A new digital video signal has been written into the field memory 4, and the field memory 4 is in the state where the sixth and seventh
Even if the digital video signals of the fields are sequentially written, at time _t8 when the read operation is started, the digital video signal of the eighth field without deterioration of the S/N ratio of one field period immediately before is stored. Therefore, field memory 3,
4, a digital video signal with no deterioration in S/N ratio is read out.

Furthermore, in a state where no detection signal is received for two or more fields, one of the field memories 3 and 4 performs a writing operation, and the other stores the digital video signal of one field before, until the next detection signal arrives. The reading operation is repeated alternately for each field. In this way, the output terminal 12 outputs a reproduced composite video signal of a frame-by-frame image without deterioration of the S/N ratio.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can also be applied to frame-by-frame playback of a playback device such as a video disc.

Effects As described above, according to the present invention, one of the first and second field memories is controlled to perform a write operation, and the other is controlled to perform a read operation,
In addition, when a detection signal indicating a reproduction period in which the level of the FM wave is lower than a certain value is received, the operation of the first and second field memories at the time the detection signal is received is Since the period continues until a total of two vertical synchronizing pulses are detected in a row, the field memory to be read next has a single pulse without deterioration of the S/N ratio.
It is possible to write the digital video signal for the field, and during the period when the detection signal is received, the digital video signal without deterioration of the S/N ratio can be continuously read out repeatedly as many times as possible. This makes it possible to obtain a frame-by-frame image without deterioration of the S/N ratio, and has the advantage that a very precise servo circuit is not required for frame-by-frame playback.

[Brief explanation of the drawing]

Fig. 1 is a block system diagram showing one embodiment of the device of the present invention, Fig. 2 is a circuit system diagram showing an embodiment of the main part of the block system shown in Fig. 1, and Fig. 3 is the circuit shown in Fig. 2. FIG. 4 is a signal waveform diagram for explaining the operation of the system. FIG. 4 is a signal waveform diagram for explaining the operation of other main parts of the device of the present invention. 1...Reproduction composite color video signal input terminal, 2...
...AD converter, 3, 4...Field memory, 5
... Bus line controller, 6, 9 ... Timing control circuit, 7a to 7c, 7a ₁ to 7a ₂ ... Output terminal, 8 ... Detection signal input terminal, 10 ... Address signal generation circuit, 11 ... DA conversion Vessel, 12...
Reproduction color video signal output terminal, 15...Digital video signal input terminal, 16...Horizontal synchronization pulse extraction circuit, 17...Vertical synchronization pulse extraction circuit, 2
0,22...J-K flip-flop (J-KF.
F).

Claims (1)

[Scope of utility model registration request] an AD converter that converts a composite video signal reproduced from a recording medium in a signal form having at least FM waves and then demodulated into a digital video signal; and first and second field memories to which the digital video signal is supplied. a switch means for selectively outputting the output digital video signal of the one of the first and second field memories undergoing a read operation; A detection signal indicating a reproduction period in which the level of the FM wave is lower than a fixed value is respectively supplied, and when the detection signal comes in, the detection signal is in a state where no subsequent detection signal comes in, and Until a total of two vertical synchronizing pulses in the output digital video signal of the switching means are detected in succession, the writing operation of one of the first and second field memories at the time of the input of the detection signal and the writing operation of the other The reading operation continues, and after the continuation until the next detection signal comes in, the AD is stored in the - side of the first and second field memories.
memory control means that alternately writes the output digital video signal of the converter and reads the digital video signal one field before the other memory from the other memory for each field;
A video signal processing device comprising: output means for obtaining a reproduced composite video signal output from the output signal of the switch means.