JPH03791Y2 - - Google Patents

Description

[Detailed explanation of the idea]

INDUSTRIAL APPLICATION FIELD The present invention relates to a video signal processing device, and particularly to a video signal processing device that can obtain high-quality still images at arbitrary timing. Conventional technology and its problems In helical scanning VTR,
During variable speed playback, in which recorded video signals are played back by running (or stopping) a recorded magnetic tape at a tape running speed different from that during recording, the relative speed between the tape and the head is different from that during recording, so the head scanning trajectory changes. It is well known that the marks are drawn at a different slope from the recorded tracks. For this reason, adjacent tracks are recorded by rotary heads having gaps with different azimuth angles, respectively.
During variable speed playback of a magnetic tape with a track pattern in which there is no guard band or only a very small guard band is formed between the tracks, the playback rotary head rotates with a gap of the same azimuth angle as itself per one track scanning period. The track recorded by the head and the track recorded by the rotary head (reverse track) having a gap of different azimuth angle are scanned alternately, and therefore, during reverse track scanning, the track is reproduced due to the azimuth loss effect. The signal level becomes extremely low and the S/N ratio deteriorates. Similarly, during variable speed playback of a magnetic tape with a track pattern in which a guard band of a sufficient constant width is formed between adjacent tracks, the guard band is crossed more than once per track scanning period, so when the guard band is scanned, The reproduced signal level becomes extremely low and the S/N ratio deteriorates. Here, if the variable speed playback described above is a still motion playback in which a still image is obtained by stopping the tape running and reproducing the recorded composite video signal, in addition to the above-mentioned deterioration of the S/N ratio of the playback signal, Second, there is the problem of slight wobble in the reproduced still image that occurs when recorded composite video signals from two adjacent tracks are played back alternately, and the rotating head that occurs when still motion playback is continued for a long time. There are further problems such as clogging of the gap and damage to the magnetic surface of the magnetic tape. Regarding the problem of slight wobble in reproduced still images, conventionally in the case of VTRs using the azimuth recording and reproduction method,
For example, one of two recording/reproducing rotary heads with different azimuth angles and one rotary head dedicated for special reproduction, which is selected to have the same azimuth angle as the other rotary head, alternately perform the same recording. By playing back the track, a completely still image was obtained. but,
For this, one new rotating head is required,
Additionally, it was necessary to add one more rotary transformer, preamplifier, etc., making the device expensive. Regarding the above-mentioned problem that occurs when still motion playback is continued for a long time, conventionally when still motion playback is continued for a certain period of time or longer, the mode is immediately switched to stop mode after a certain period of time, or the tape tension is turned on after a certain period of time has elapsed. The player would drop the tape, feed a small amount of the tape to lift it off the rotating head, or switch to slow motion playback mode after the above-mentioned certain period of time had elapsed. However, with all of the above methods, still motion playback cannot be continued for more than a preset period of time, and with these methods, if you suddenly start high-speed playback from a state where the tape tension has dropped, the reel rotation will be interrupted. However, there were also problems such as slack in the tape and hunting in the reel tension. Therefore, the present invention writes the reproduced composite video signal to the field memory during still motion reproduction, and also writes the reproduced composite video signal of the approximately equivalent interval one track scanning period ago in the section where the reproduced FM signal level is extremely low. By writing into the field memory and obtaining the reproduced composite video signal based on the signal read from the field memory, the above problems of deterioration of the S/N ratio of the reproduced composite video signal and slight jitter of the reproduced still image can be solved. Furthermore, it is an object of the present invention to provide a video signal processing device that solves problems during long-time still motion playback. Means for Solving the Problems The present invention provides an AD converter to which a composite video signal is reproduced from a recording medium in a signal form including at least FM waves and then demodulated, a field memory and a switch means, and a still video signal. means for generating and outputting a mode signal indicating a continuous reproduction period; and during the non-generation period of the mode signal, a period in which the level of the reproduced FM wave is lower than a certain value and a predetermined period around the period or a predetermined period therearound; In the shorter period, the digital video signal of the corresponding section one track scanning period ago is read out from the field memory instead of the output signal of the AD converter and is selectively outputted by the switch means. The relative phase difference between the synchronization signals in both the output signals of the switch means and the AD converter is detected, and the read timing of the field memory is controlled so that the phase difference becomes approximately zero, and the read timing of the field memory is controlled so that the phase difference becomes approximately zero. When this occurs, the read operation of the field memory is terminated even within the above-mentioned fixed period, and except for the above-mentioned read period, the switch means is used to selectively output the output signal of the AD converter and perform AD conversion to the field memory. a first control means for generating and outputting a control signal for writing an output signal of the device;
During the mode signal generation period, if a read operation of the field memory is performed by a control signal after the input of the vertical synchronization pulse immediately before the input of the mode signal, one field is read from the time of input of the first vertical synchronization pulse after the end of the read operation. After writing the output signal of the AD converter into the field memory, if no read operation is performed, after the mode signal comes in, first detect the vertical synchronization pulse in the input playback signal, and check the detection point. A period after the mode signal disappears until the field memory read operation is not performed by the first control signal and the vertical synchronization pulse arrives;
a second control means for causing the field memory to continue its read operation and for causing the switch means to selectively output a read output signal from the field memory; The device is composed of an output means for obtaining a signal output, and one embodiment thereof will be described below with reference to the drawings. Embodiment FIG. 1 shows a block system diagram of an embodiment of the device of the present invention. In the figure, a reproduced composite color video signal is input to an input terminal 1. This reproduced composite color video signal is produced by frequency modulating (FM) the luminance signal, frequency converting the carrier color signal to a low frequency band, frequency division multiplexing these two signals, and transmitting one field to one track using a rotating head. The magnetic tape recorded on successive tracks is played back at various speeds, the FM luminance signal in the playback signal is FM demodulated, the low frequency conversion carrier color signal is frequency converted to the original band, and these two signals are combined. This is a reproduced composite color video signal that is obtained by multiplexing and substantially conforms to the standard format. In addition, when the variable speed playback described above is applied to a VTR using the azimuth recording/playback method, the magnetic tape is moved (or ), thereby at least one part of the section in which the rotary head scans the reverse track.
In the corresponding section before the track scanning period, a reproduced signal was normally obtained by another rotary head. The above-mentioned composite color video signal inputted to the input terminal 1 is supplied to the AD converter 3 via the amplifier 2, where it is analog-to-digital converted into a digital video signal, and then sent to the bus line controller 4 and the digital video signal. 1 timing control circuit 5, respectively. As will be described later, the timing control circuit 5 is supplied with digital video signals from both the input and output sides of the bus line controller 4, as well as a control signal from an input terminal 6 and a still mode signal from an input terminal 14, which will be described later. This control signal was reproduced from a rotating head while scanning the magnetic tape.
This is a binary signal generated so that the amplification of the FM luminance signal becomes, for example, a high level during a period when the amplification becomes smaller than a certain value due to reverse track scanning, and a low level during a period when the amplification exceeds this certain value. The timing control circuit 5 outputs a pulse whose phase is synchronized with the above control signal to the second timing control circuit 8 from the output terminal 7a. Further, the timing control circuit 5 outputs the horizontal synchronization pulse from which the equalization pulse and the vertical synchronization pulse have been removed from the output terminal 7b and supplies it to the timing control circuit 8, while the vertical synchronization pulse is waveform-shaped and obtained from the output terminal 7c. A pulse is output and supplied to the address signal generation circuit 10. The timing control circuit 8 generates a signal controlled by the color subcarrier frequency based on the signal from the terminal 7a and supplies it to the bus line controller 4 for switching control, and also controls the memory based on this signal. CAS (column address strobe) signal, RAS (row address strobe) signal, WE (read/write control) necessary for reading and writing 9.
It generates signals and supplies them to the memory 9, and also outputs signals to the address signal generation circuit 10. Address signal generation circuit 10 generates an address signal and supplies it to memory 9. Memory 9 is, for example, a random
An access memory (RAM) is a field memory that has a storage capacity that can store one field's worth of digital video signals, and its read output signal (digital video signal) is supplied to the bus line controller 4. Writes the digital video signal extracted from the The digital video signal selectively output from the bus line controller 4 is sent to a timing control circuit 5,
The signal is supplied to the memory 9 and the DA converter 11, respectively.
The DA converter 11 performs digital-to-analog conversion on the input digital video signal, returns it to a composite color video signal which is an analog signal, and outputs it to the output terminal 13 through the amplifier 12. Here, the memory 9 normally writes the output digital video signal of the AD converter 3 supplied via the bus line controller 4, but when the rotary head performing variable speed playback scans the reverse track, As such, the memory 9 is switched to read control during at least the period including the scanning period, and the bus line controller 4 selectively outputs the reproduced digital video signal of the same period one track scanning period ago, read from the memory 9. Output terminal 1
The reproduced composite color video signal of No. 3 is normally the reproduced composite color video signal of the current field reproduced by the rotating head currently scanning the magnetic tape, but the reverse track scanning period is the reproduced composite color video signal of the current field that was reproduced one track scanning period ago. The reproduced composite color video signal is replaced with a corresponding section of a different field (an even field when the current field is an odd field, and an odd field when the current field is an even field). As a result, the S/N during reverse track scanning
Deterioration of the ratio can be prevented. Here, if the relative phase difference between the synchronization signal in the digital video signal read out from the memory 9 and the synchronization signal in the digital video signal being reproduced taken out from the AD converter 3 is large, the above-mentioned When changing the screen, the horizontal synchronization signal interval changes and the screen becomes distorted. Therefore, in order to ensure stable signal connection during the above-mentioned transition and to obtain high-quality still images during still motion playback, the timing control circuit 5 of the present invention is set to a specified value. The structure and operation of the timing control circuit 5 will be explained next. FIG. 2 shows a circuit diagram of one embodiment of the timing control circuit 5. As shown in FIG. In the figure, the same components as in FIG. 1 are designated by the same reference numerals. In FIG. 2, the control signal a whose high level period corresponds to the reverse track scanning period as shown in FIG.
The signal is supplied to one input terminal of the 2-input OR circuit 16 and to the inverter 17, respectively. Here, the monostable multivibrator 15 is triggered by the falling edge of the control signal a, and outputs a pulse with a constant width T according to a time constant determined by the product of the values of the resistor _R1 and the capacitor _C1 . Therefore, as shown in FIG. 3A, when the control signal a is at a high level during the periods _t0 to _t1 and _t5 to _t6 , the monostable multivibrator 1
A high level pulse is taken out from the Q output terminal of 5 for a certain period T (t ₁ to t ₄ , t ₆ to t ₇ ) from each time t _{1 and} t 6 and sent to the other input terminal of the OR circuit 16 . Supplied. As a result, high-level pulses b are taken out from the OR circuit 16 during the respective periods of time t ₀ to t ₄ and t ₅ to t ₇ as shown in FIG. 3B.
It is applied to one input terminal of the input AND circuit 18. Further, from the output terminal _{of the} monostable multivibrator 15, _a pulse f as shown in _FIG .
is taken out and applied to one input terminal of the two-input OR circuit 19. Furthermore, the signal whose polarity is inverted and taken out by the inverter 17 is sent to a J-K flip-flop (J-K flip-flop).
KF.F) 20 is applied to the clear terminal CLR to keep it in the clear state during its low level period. J-
In KF.F20, positive DC voltage Vcc is applied to the J terminal, and the output signal of the output terminal is applied to the K terminal.
Further, an output signal from a D-type flip-flop 26, which will be described later, is supplied to the clock terminal CK. On the other hand, the input terminal 22 receives a digital video signal from the AD converter 3, and the input terminal 23 receives a digital video signal selectively output from the bus line controller 4. The digital video signal from the input terminal 22 is supplied to a horizontal synchronizing pulse extraction circuit 24, where a horizontal synchronizing pulse with a period of 1H (H is a horizontal scanning period) is extracted and supplied to a monostable multivibrator 25, and its rising edge is extracted. Trigger this. Here, the time constant of the monostable multivibrator 25 is formed by the resistor R ₂ and the capacitor C ₂ , and is approximately half the period of 1H (approximately
31μsec). As a result, the monostable multivibrator 25 is connected to its Q output terminal.
A substantially symmetrical square wave with a period of 1H is outputted and applied to the data input terminal D of the D-type flip-flop 26. On the other hand, the digital video signal input to the input terminal 23 is supplied to a horizontal synchronizing pulse extracting circuit 27 and a vertical synchronizing pulse extracting circuit 35, which will be described later.
The horizontal synchronizing pulse extracted from the horizontal synchronizing pulse extracting circuit 27 is supplied to a waveform shaping circuit 28, where its rising edge portion is extracted, and then applied as a clock pulse to the D-type flip-flop 26, while the shift register 29. The shift register 29 sequentially shifts the pulses that have entered the input terminal in response to a clock pulse (shift pulse) from the input terminal 30, and transfers them to the output terminal.
It is sequentially outputted from Q _A , Q _B , and Q _C and supplied to input terminals 31 ₃ , 31 ₂ , and 31 ₁ of the multiplexer 31 .
The flip-flop 26 outputs a signal obtained by sampling and holding the input pulse at the data input terminal D when the pulse is input from the waveform shaping circuit 28 from its Q output terminal, as shown in FIG.
Since the readout output digital video signal of the memory 9 is input to the input terminal 23 during a period approximately corresponding to the high level period of the pulse e shown in FIG. A signal with a polarity corresponding to the lead/lag between the phase of the reproduced horizontal synchronizing pulse read from the memory 9 and the phase of the reproduced horizontal synchronizing pulse one track scanning period ago is output to the Q of the flip-flop 26.
It will be taken out from the output terminal. The output signal of the Q output terminal of this flip-flop 26 is the third
As shown in FIG. C, the signal c from the output terminal is applied to the clock input terminal CK of J-KF.F20. Here, the period t ₀ to t ₁ and t ₅ during which a low level signal is applied to the clear terminal CLR of J-KF.F20
At ~t ₆ , J-KF.F20 is in the clear state and a high level signal is output from its output terminal, so the input level of the K terminal becomes high level as well as the J terminal, so In this state, after time _t1 or after time _t5 , the output signal is held at a high level until a clock pulse is received. Therefore, when the clock pulse arrives at time _t2 , the output signal of J-KF.F20 goes low at time _t2 , and when it arrives at time _t3 , it goes low at _t3 . As a result, J-
The output signal of KF.F20 becomes signal d as shown in FIG. 3D. In addition, as shown in FIG. 3C, the signal c
Assuming that d remains at high level or low level during the period from _t5 to _t8 , the signal d as shown in FIG.
Since no signal is received during the period from _t6 to _t7 , the high level state is maintained. The above output signal d is supplied to a two-input AND circuit 18, where it is ANDed with the pulse d and converted into a pulse e as shown in FIG. Applied to the input terminal. Here, the Q output signal of a D-type flip-flop 41, which will be described later, is applied to the other input terminal of the OR circuit 37, and the still mode signal from the input terminal 14, which is applied to the data input terminal D of the flip-flop 41, is applied to the other input terminal of the OR circuit 37. is at a low level in all modes other than the still mode, so the Q output signal of the flip-flop 41 is always at a low level in playback modes other than the still mode. Therefore, in a reproduction mode other than the still mode, the pulse e passes through the OR circuit 37 as it is and is outputted to the output terminal 7a as a control signal. When the clock pulse arrives at time _t2 , the pulse e remains at a high level from _t0 to _t2 , and when the clock pulse arrives at time _t3 , it remains at a high level from t0 to _t2 .
It is at a high level for a period of _t3 , and is also at a high level for a period from _t5 to _t7 , and during a period approximately corresponding to this high level period, the memory 9 is read-out controlled and the bus line controller 4 selects the output of the memory 9. During a period approximately corresponding to the period in which the pulse e is at a low level, the memory 9 is controlled to write as shown by R in E in the same figure, and
The bus line controller 4 is switched to selectively output the output of the AD converter 3. As will be described later, the control of the bus line controller 4 and the write and read control of the memory 9 are performed by the output signal k of the timing control circuit 8, but the pulse e and the output signal k are controlled by the output signal k of the timing control circuit 8 as shown in FIGS. 4A and C, respectively. It roughly corresponds to k. Further, the above output signal d is supplied to the NAND circuit 21 together with the output signal of the inverter 17, thereby converting it into the signal g as shown in FIG. 3G.
The signal is supplied to an OR circuit 19, where it is logically summed with the pulse f to form a pulse h as shown in H in the figure. This pulse h is applied to one input terminal of each of the OR circuits 32 and 33. multiplexer 31
is a circuit that selects and outputs one of the input signals of the input terminals 31 ₁ to 31 ₃ from the output terminal according to the input signal of the 2-bit control input terminals A and B. The relationship between the signal level supplied to the input terminal and the input terminal of the input signal selectively output from the multiplexer 31 is summarized as shown in the following table.

[Table] However, in the above table, L indicates low level and H indicates high level. Here, the control input terminal A of the multiplexer 31
The pulses supplied to
This is a pulse obtained through the OR circuit 32, and since the pulse t is normally at a high level, the control input terminal A is also normally at a high level, but from time t ₁ to t ₂ or t ₁ shown in FIG. The low level period of the pulse h from _t3 to the period from _t6 to _t7 is determined by the polarity of the output pulse c of the flip-flop 26 and is indefinite. For example, during the low level period of the pulse h, when the output pulse of the circuit 25 is delayed from the output pulse of the circuit 28, the output signal c of the flip-flop 26 becomes low level, so the control input terminal A also becomes low level. Become. On the other hand, the pulse supplied to the control input terminal B of the multiplexer 31 is a pulse taken out from the output terminal of the OR circuit 33 which takes the logical sum of the pulse h and the low level signal, so it is the same pulse as the pulse h. . Therefore, during variable speed playback, after the rotary head scans a reverse track, a certain period (t ₁ to t ₂ , _t1 to _t3 , _t6 to _t7 ) are control input terminals A
and B both go to high level, the multiplexer 31 outputs the input pulse from the input terminal 31 ₂ . On the other hand, during the above period, control input terminal B
is at a low level, and the control input terminal A receives a pulse c
When the pulse c is at a low level, it becomes a low level, so the input pulse of the input terminal ₃₁₁ is taken out from the multiplexer 31, and when the pulse c is at a high level, the control input terminal A also becomes a high level, so the input pulse from the multiplexer 31 is taken out from the input terminal. 31 ₃ input pulses are taken. Here, the input pulse at the input terminal 31 ₁ is delayed in phase by one period of the shift clock by the shift register 29 with respect to the input pulse at the input terminal 31 ₂ , and the input pulse at the input terminal 31 ₃ is delayed in phase by one cycle of the shift _clock . The phase of the shift clock is one period ahead of the input pulse. Therefore, the clock pulses (shift pulses) entering the input terminal 30 are transmitted to, for example, an oscillator (not shown).
By selecting a pulse with a repetition frequency equal to the color subcarrier frequency fs, the low level period of the above pulse h is equal to the horizontal synchronizing pulse in the composite video signal currently being played and one track read from the memory 9. The output signal i of the multiplexer 31 (shown in FIG. 3
is gradually advanced or delayed in phase by one cycle of fs. According to this embodiment, the timing adjustment time is set to the time T determined by the time constant of the monostable multivibrator 15, but even within the adjustment time, the timing adjustment time is set to the time T determined by the time constant of the monostable multivibrator 15. When the phase difference between the horizontal synchronizing pulse and the horizontal synchronizing pulse in the video signal currently being reproduced by the rotating head becomes extremely small (at t ₂ or t ₃ in FIG. 3), the output pulse c of the flip-flop 26 becomes high level, and the output signal d of J-KF.F20 becomes low level, so P ₁ , P ₂ , P ₃ are shown in Fig. 3I.
The adjustment operation is completed only by adjusting the timing of either one of them, and the reading operation of the memory 9 is also completed, and the writing operation is switched to. Furthermore, even if timing adjustments are made as shown in P ₁ ', ..., P ₄ ' in Fig. 3I until the set time T is reached during the period from t ₆ to _{t 7} , the state is still unsuitable for switching. If so, flipflop 26
Since the output pulse c remains at low level,
The output signal d of J-KF.F20 is the set time
It remains at a high level until _t7 , and therefore the memory 9 is read out for the full set time T, and the readout ends at time _t7 , and the reproduced composite video currently being played back and output from the rotary head. Digital signals of the signals are switched and output from the bus line controller 4. According to the present invention, if the set time T is long enough, the timing adjustment operation will continue during this period. Since the phase difference with the horizontal synchronizing pulse is extremely small and the timings match, the composite video signal currently being reproduced can be switched and output at the time of matching. Note that the time setting (timing adjustment time) for the period T mentioned above should be used in cases where there is a time lag (one field interval time) between the reproduction horizontal synchronizing pulses before and after one track scanning period, depending on the model of the VTR, for example. , may be set in advance in accordance with the time lag. The output pulse i of the multiplexer 31 is also synchronized with the equalization pulse and the vertical synchronization pulse at intervals of 0.5H within the vertical blanking period. Therefore, this pulse i is supplied to an equalization pulse/vertical synchronization pulse extracting circuit 28, where the vertical synchronization pulse and equalization pulse are removed, and the pulse i is converted into a pulse having an interval of 1H, and then outputted to the output terminal 7b. On the other hand, the vertical synchronizing pulse l extracted from the vertical synchronizing pulse extracting circuit 35 as shown in FIG. 5A is converted into a pulse as shown in FIG. 7c. Note that FIG. 3I shows the time axis of each of the waveforms A to H in the same figure enlarged. Further, the extraction circuit 34 becomes unnecessary if the horizontal synchronizing pulse extraction circuits 24 and 27 are provided with that function. The timing signal taken out from the output terminal 7b is supplied to the timing control circuit 8 shown in FIG. 1 together with the pulse s taken out from the output terminal 7a. The timing control circuit 8 operates as shown in FIG. 4B based on the clock pulse whose repetition frequency is equal to the color subcarrier frequency s obtained by shaping the input clock pulse at the input terminal 30 and the timing signal from the terminal 7b. A signal j having a waveform that rises in phase synchronization with, for example, the rising edge of the clock pulse is generated. Here, terminal 7b
The timing signal of 2 is received every 1H (=227.5/s), but since the color subcarrier frequency s is 227.5 times the horizontal scanning frequency H, the phase is reversed every 1H, but as shown above, , repetition frequency s
When the signal j shown in FIG. 4B, which rises only in phase synchronization with the rising edge of the clock pulse, as shown in FIG. 4B, is generated, the phase of the color subcarrier and the phase of the rising edge of the signal j always have the same relationship. This results in a time interval of 227/s or 228/s from any rising edge of signal j to the next rising edge, but if the above timing adjustment is made, it becomes 226/s or 229/s. It will be corrected so that The timing control circuit 8 generates the above signal j and supplies it to the clock input terminal of the D-type flip-flop inside the circuit 8, and also inputs the input pulse s from the terminal 7a shown in FIG. 4A (as shown in FIG. 5I). The circuit is constructed so that a pulse (same as the one shown) is applied to the data input terminal of the D-type flip-flop, and the flip-flop outputs a signal k as shown in FIG. 4C. This signal k is generated and output as a control signal for the memory 9 and bus line controller 4 shown in FIG. On the other hand, during the high level period of the signal k, the memory 9 is read out and the bus line controller 4 is switched to the selected output state of the output of the memory 9. According to this embodiment, in the timing adjustment section, the horizontal scanning period is 226 s or 229/s.
Although this is different from the normal value of 227.5/s, the error is sufficiently small and does not pose a problem in practice. As a result, when switching from one of the readout signal and the currently reproduced signal to the other, the connection is made on the same phase of the color subcarrier frequency,
Connection is extremely stable. Next, the operation in still motion reproduction mode (still mode) will be explained. In any playback mode other than the still mode (however, strictly speaking, a playback mode in which the low level period of pulse e occurs at intervals larger than one field), when the user operates a predetermined switch at any timing, , during the operation period, a high-level still mode signal is generated by a predetermined circuit to the input terminal 14.
is applied to the data input terminal D of the D-type flip-flop 41. The configuration of the still mode signal generation circuit described above can be easily deduced by those skilled in the art, so a description of the configuration will be omitted. Now, it is assumed that the above-mentioned still mode signal is generated at time ta during the second field playback period, as shown in FIG. Then, the still mode signal m is output at time tg during the nth field playback period.
shall disappear (become low level). A low-level pulse l during the vertical synchronization period as shown in FIG. After the waveform is shaped and converted into a narrow and constant pulse o that falls in phase synchronization with the rising edge of the vertical synchronizing pulse l as shown in Fig. 5E, the clear terminal of J-KF.F39 is applied to the signal, and its falling edge clears it. J-
The J terminal of KF.F39 is connected to the input terminal of the positive DC power supply voltage Vcc, and the K terminal is connected to its output terminal. Therefore, J-KF.F.
39 is cleared above, a high level signal is applied to the K terminal as well as the J terminal, and a low level signal is output from the Q output terminal. In this state, a clock pulse is input to the clock input terminal. It will be held until it comes. Here, the AND circuit 1
Assume that the output pulse e of No. 8 becomes high level as shown in FIG. 5B. As mentioned above, play
The output pulse e of the AND circuit 18 is at a high level during a period in which the FM signal level is lower than a certain value, and during a period approximately corresponding to a predetermined period around the period or a period shorter than that. up to time td in the first half of the third field, Figure 5B
Assume that the level is high as shown in . While the pulse e is supplied to the OR circuit 37, its rising edge and falling edge are each detected by the waveform shaping circuit 38, and a narrow and constant width fifth edge is detected.
After being converted into a pulse p as shown in FIG. F, it is applied to J-KF.F 39 as a clock pulse. As a result, the Q output signal of J-KF.F39 becomes high level at the first clock pulse input time tb, as shown in FIG.
It is cleared and becomes a low level, and becomes a high level when the next clock pulse comes in at time td, and becomes a low level when the first pulse o of the fourth field comes in and is cleared at time te. The Q output signal q shown in FIG. 5G of the J-KF.F 39 is applied to the other input terminal of the two-input OR circuit 40, where it is ORed with the vertical synchronizing pulse l. As shown in FIG. 5H, the signal r taken out from the OR circuit 40 is at a high level during the period from time ta to te mentioned above and the period before and after that, and from the end of the fourth field to the beginning of the fifth field. It becomes a low level corresponding to the low level period of the vertical synchronizing pulse l. D
The type flip-flop 41 receives this signal r as a clock pulse and outputs from its Q output terminal a signal obtained by sampling the input signal level of the data input terminal D at the time when the rising edge of the signal r arrives. Therefore, during the input period ta to tg of the still mode signal m, the flip-flop 41 operates at the time td when the pulse e changes from high level to low level (this time td
The still mode signal m is sampled at the detection time tf of the second incoming vertical synchronization pulse after the time when the memory 9 finishes the read operation, and the still mode signal m is at a higher level than the time tf. A signal is generated and outputted from its Q output terminal. This state of the flip-flop 41 continues after the time tg when the still mode signal m disappears until the arrival time th of the pulse o obtained by detecting the first vertical synchronizing pulse. Therefore, the Q output signal of the flip-flop 41 becomes a high-level pulse n from time tf to time th, as shown in FIG. After being converted into a pulse s shown in FIG. 5I, it is output to the output terminal 7a. During a period approximately corresponding to the period in which the pulse s is at a high level, the memory 9 performs a read operation and the bus line controller 4 is switched to selectively output the read output signal of the memory 9, and the pulse s is at a low level. During a period that approximately corresponds to a certain period, the memory 9 and the bus line controller 4 are
As described above, the memory 9 is controlled to write the output signal of the AD converter 3. Therefore, the memory 9 stores the digital video signal of the reproduced composite video signal of the fourth field without S/N deterioration written in the period approximately corresponding to the period from time tf to th and corresponding to the period from time te to tf. is controlled to be read out repeatedly, and during this readout period, a still image related to the reproduced composite video signal of the fourth field is displayed. This still image is S/
Since it is based on one field's worth of completely reproduced composite video signals with no deterioration in the N ratio, it is completely still, and furthermore, there is no deterioration in the S/N ratio, resulting in an extremely high quality still image. Furthermore, during still motion playback, the digital video signal for one field in the memory 9 is repeatedly read out, so there is no restriction on the continuous playback period of still images, and still images can be obtained for any desired period. Furthermore, it is necessary to continue the reproduction for about three field periods after the still motion instruction operation, but after that, it is not necessary to stop the tape running. Note that the same operation as described above is performed when the still mode signal m enters during the high level period tb to td of the pulse e. Furthermore, if the pulse e remains at a low level during the period from time ta when the still mode signal m arrives to time tc when the waveform shaping pulse o of the first vertical synchronization pulse arrives (from ta to tc), During the period, if the level of the reproduced FM wave does not become smaller than a certain value and a normal reproduced output is obtained), no clock pulse is applied to J-KF.F39, so the output signal r of the OR circuit 40 has the same waveform as the vertical synchronization pulse l, and therefore the time
Immediately after tc, read control of the memory 9 is started,
Is it possible to obtain a still image of the reproduced composite video signal of the second field (when pulse e is low level even in one or more fields immediately before ta), or is a still image of the reproduced composite video signal of the third field obtained immediately after time te? (when pulse e changes from high level to low level within one field immediately before ta). Furthermore, when the pulse e is at a high level at time th, the signal r becomes a low level when the next vertical synchronizing pulse l arrives and the pulse e is at a low level. The reading operation (still motion reproducing operation) of the memory 9 ends at the rising edge of the signal r immediately after. It should be noted that the present invention is not limited to the above-mentioned embodiments, but can record video discs on which composite video signals of two or more fields per revolution are recorded as changes in capacitance using the electrode of the playback needle. A reproducing device that reads and reproduces signals can also be applied to still motion reproduction. Effects As described above, according to the present invention, during variable speed playback, the period including the period in which the FM level of the composite video signal currently being played becomes smaller than a certain value, and the surrounding period, is one track scanning period shorter than that period. Since the digital signal of the reproduced composite video signal of the previous corresponding section is read out from the memory and replaced with the reproduced composite video signal currently being reproduced, it is possible to obtain good image quality without deterioration of the S/N ratio of the reproduced composite video signal. A reproduced composite video signal output can be obtained, and the relative phase lead/lag between the readout output signal and each vertical synchronization pulse of the composite video signal being reproduced is detected near the end of reading from the memory, and it is detected that Since the readout output timing is controlled so that the digital video signal written in the memory can be faithfully reproduced, the timing of the composite video signal currently being played and the vertical synchronization signal phase almost match. During still motion playback, when the still mode signal is being generated and output, the output digital of the AD converter for one complete field can be read out after the input of the vertical synchronization pulse immediately before the input of the mode signal. After writing the video signal to the field memory, the input of the first reproduction vertical synchronizing pulse is detected, and after the mode signal disappears from the time of this detection, the read operation of the field memory by the first control signal is not performed, and , the period up to the point at which the vertical sync pulse arrives,
Since the field memory is used and its readout output signal is continuously output, it is possible to obtain a completely still image and a high-quality still image without deterioration of the S/N ratio. ,
In addition, since there is no need to add a new rotary head, the structure can be constructed at low cost without complicating the mechanism.Furthermore, the still image is generated by repeating the digital video signal for one field stored in the field memory. Since the data is obtained by reading the data from the recording medium, there is no need to repeatedly reproduce the same track on the recording medium, and there is no risk of damage to the recording medium or clogging of the gap of the rotating head. It has many features such as being able to continue playing still motion.

[Brief explanation of drawings]

Fig. 1 is a block system diagram showing one embodiment of the device of the present invention, Fig. 2 is a circuit system diagram showing an embodiment of the main part of the block system shown in Fig. 1, and Figs. Signal waveform diagram for operation explanation in Figure 2, Figure 4 A~
C is a signal waveform diagram for explaining the operation of other main parts of the device of the present invention, and FIGS. 5A to 5I are signal waveform diagrams for explaining the operation of FIG. 2, respectively. 1...Reproduction composite color video signal input terminal, 3...
...AD converter, 4...Bus line controller,
5, 8...Timing control circuit, 6...Control signal input terminal, 7a-7c...Output terminal, 9...Memory, 10...Address signal generation circuit, 11...
DA converter, 13... Reproduction composite color video signal output terminal, 14... Still mode signal input terminal, 1
5,25...monostable multivibrator, 20,
39...J-K flip-flop (J-KF.F),
21, 39...NAND circuit, 22, 23...Digital video signal input terminal, 24, 27...Horizontal synchronizing pulse extraction circuit, 26, 41...D-type flip-flop, 29...Shift register, 30...
...Clock pulse input terminal, 31...Multiplexer, 35...Vertical synchronization pulse extraction circuit.

Claims (1)

[Scope of utility model registration request] An AD converter that converts a composite video signal reproduced from a recording medium in a signal form having at least FM waves and then demodulated into a digital video signal, a field memory, and any of the output signals of the AD converter and the field memory. means for generating and outputting a mode signal indicating a continuous period of steel motion reproduction at an arbitrary timing; and means for generating and outputting a mode signal indicating a continuous period of steel motion reproduction at an arbitrary timing; For a period smaller than , and a predetermined period around it, or a period shorter than that, the data of the corresponding section one track scanning period ago, read from the field memory, is used instead of the output signal of the AD converter. The digital video signal is selectively outputted by the switching means, and the relative phase difference between the synchronizing signals in both the output signals of the switching means and the AD converter is detected within the predetermined period, and the phase difference is detected. The read timing of the field memory is controlled so that the phase difference becomes approximately zero, and when the phase difference becomes approximately zero, the read operation of the field memory is terminated even within the above-mentioned fixed period, Otherwise, use the switch means to selectively output the output signal of the AD converter and store the AD converter in the field memory.
a first control means for generating and outputting a control signal for writing an output signal of the converter; and a first control means for generating and outputting a control signal for writing an output signal of the converter; When a read operation is performed, the output signal of the AD converter for one field is written into the field memory from the time when the first vertical synchronization pulse is input after the end of the read operation, and when the read operation is not performed, After the mode signal enters, a vertical synchronizing pulse in the first incoming reproduction signal is detected, and after the mode signal disappears from the detection point, the first read operation of the field memory by the control signal is performed. not carried out, and
a second control means for causing the field memory to continue its read operation and for causing the switch means to selectively output the read output signal of the field memory until the vertical synchronization pulse is received; and output means for obtaining a reproduced composite video signal output from the output signal of the switch means.