JPH03789Y2 - - Google Patents

Description

[Detailed explanation of the idea]

INDUSTRIAL APPLICATION FIELD The present invention relates to a video signal processing device, and in particular, the signal-to-noise ratio (S/N) of a reproduced composite video signal that occurs when a head crosses different tracks during variable speed reproduction.
The present invention relates to a video signal processing device that performs digital signal processing to compensate for the deterioration of the ratio (ratio). Conventional technology and its problems In helical scanning VTR,
During variable speed playback, in which recorded video signals are played back by running (or stopping) a recorded magnetic tape at a tape running speed different from that during recording, the relative speed between the tape and the head is different from that during recording, so the head scanning trajectory changes. It is well known that the marks are drawn at a different slope from the recorded tracks. For this reason, adjacent tracks are recorded by rotary heads having gaps with different azimuth angles, respectively.
During variable speed playback of a magnetic tape with a track pattern in which there is no guard band or only a very small guard band is formed between the tracks, the playback rotary head rotates with a gap of the same azimuth angle as itself per one track scanning period. The track recorded by the head and the track recorded by the rotary head (reverse track) having a gap of different azimuth angle are scanned alternately, and therefore, during reverse track scanning, the track is reproduced due to the azimuth loss effect. The signal level becomes extremely low and the S/N ratio deteriorates. Similarly, during variable speed playback of a magnetic tape with a track pattern in which a guard band of a sufficient constant width is formed between adjacent tracks, the guard band is crossed more than once per track scanning period, so when the guard band is scanned, The reproduced signal level becomes extremely low and the S/N ratio deteriorates. Therefore, the present invention solves the above problem by replacing the section where the reproduced FM signal level becomes extremely low during variable speed playback with the reproduced composite video signal of a substantially equivalent section from one track scanning period earlier. The purpose of the present invention is to provide a signal processing device. Means for Solving the Problems The present invention is an AD converter that converts a composite video signal reproduced from a recording medium that is run at a predetermined speed different from the recording speed or stopped running into a digital video signal. , a switch means for selectively outputting either the output signal of the memory having a storage capacity of one field or more, the output signal of the AD converter, or the read output signal of the memory, and the level of the reproduced composite video signal being lower than a certain value. period and a predetermined period around it or a shorter period
Instead of the output signal of the AD converter, the digital video signal of the corresponding section one track scanning period ago, which is read from the memory, is selectively outputted by the switch means.
control means for selectively outputting the output signal of the converter and writing the output signal of the AD converter into the memory; The relative lead and lag are detected, and the read timing of the memory is controlled so that the phases thereof are small, and when the detected phases substantially match, the control means is operated even within the certain period of time. The apparatus is comprised of a read control means for terminating the read operation of the memory, and an output means for obtaining a reproduced composite video signal from the output signal of the switch means, and one embodiment thereof will be described below with reference to the drawings. Embodiment FIG. 1 shows a block system diagram of an embodiment of the device of the present invention. In the figure, a reproduced composite color video signal is input to an input terminal 1. This reproduced composite color video signal is produced by frequency modulating (FM) the luminance signal, frequency converting the carrier color signal to a low frequency band, frequency division multiplexing these two signals, and transmitting one field to one track using a rotating head. The magnetic tape recorded on successive tracks is played back at various speeds, the FM luminance signal in the playback signal is FM demodulated, the low frequency conversion carrier color signal is frequency converted to the original band, and these two signals are combined. This is a reproduced composite color video signal that is obtained by multiplexing and substantially conforms to the standard format. In addition, when the variable speed playback described above is applied to a VTR using the azimuth recording/playback method, the magnetic tape is moved (or ), thereby at least one part of the section in which the rotary head scans the reverse track.
In the corresponding section before the track scanning period, a reproduced signal was normally obtained by another rotary head. The reproduced composite color video signal inputted to the input terminal 1 is supplied to the amplifier 2 and the AD converter 3, where it is analog-to-digital converted into a digital video signal, and then sent to the bus line controller 4 and the AD converter 3. 1 timing control circuit 5, respectively. As will be described later, the timing control circuit 5 is supplied with a control signal from an input terminal 6 along with both digital video signals to the input and output sides of the bus line controller 4. This control signal is, for example, at a high level during the period when the amplitude of the FM luminance signal reproduced from the rotating head while scanning the magnetic tape becomes smaller than a certain value due to reverse track scanning, and at a low level during a period when the amplitude is above this certain value. This is a binary signal generated so that The timing control circuit 5 outputs a pulse phase-synchronized with the control signal to an output terminal 7.
It is output to the second timing control circuit 8 from a. Further, the timing control circuit 5 outputs the horizontal synchronization pulse from which the equalization pulse and the vertical synchronization pulse have been removed from the output terminal 7b and supplies it to the timing control circuit 8, while the vertical synchronization pulse is waveform-shaped and obtained from the output terminal 7c. A pulse is output and supplied to the address signal generation circuit 10. The timing control circuit 8 generates a signal controlled by the color subcarrier frequency based on the signal from the terminal 7a and supplies it to the bus line controller 4 for switching control, and also controls the memory based on this signal. CAS (column address strobe) signal, RAS (row address strobe signal), WE (read/write control) necessary for reading and writing 9.
It generates signals and supplies them to the memory 9, and also outputs signals to the address signal generation circuit 10. Address signal generation circuit 10 generates an address signal and supplies it to memory 9. The memory 9 is, for example, a random access memory (RAM), which has a storage capacity capable of storing one field's worth of digital video signals, and its readout output signal (digital video signal) is supplied to the bus line controller 4. , and also writes the digital video signal taken out from the bus line controller 4. The digital video signal selectively output from the bus line controller 4 is sent to a timing control circuit 5,
The signal is supplied to the memory 9 and the DA converter 11, respectively.
The DA converter 11 performs digital-to-analog conversion on the input digital video signal, returns it to a composite color video signal which is an analog signal, and outputs it to the output terminal 13 through the amplifier 12. Here, the memory 9 normally stores the output digital video signal of the AD converter 3 supplied via the bus line controller 4, but when the rotary head performing variable speed playback scans the reverse track, the As described above, the memory 9 is switched to readout control during at least a period including the scanning section, and the bus line controller 4 selectively outputs the reproduced digital video signal of the same section one track scanning period ago, read from the memory 9. , the reproduced composite color video signal at the output terminal 13 is normally the reproduced composite color video signal of the current field being reproduced by the rotating head currently scanning the magnetic tape;
During the reverse track scanning period, a different field reproduced one track scanning period ago (if the current field is an odd field, it is an even field; if it is an even field, it is an odd field) is replaced with a reproduced composite color video signal of the corresponding section. It happens. As a result, the S/
Deterioration of the N ratio can be prevented. Further, in the present invention, timing control is performed so that the digital video signal being reproduced and the digital video signal read from the memory 9 are stably connected, and this will be explained next. FIG. 2 shows a circuit system diagram of one embodiment of the timing control circuit 5 in FIG. In the same figure, the first
Components that are the same as those in the figures are given the same reference numerals, and their explanations will be omitted. In FIG. 2, the control signal a whose high level period corresponds to the reverse track scanning period as shown in FIG. and the inverter 17, respectively. Here, the monostable multivibrator 15 is triggered by the falling edge of the control signal a, and outputs a pulse with a constant width T according to a time constant determined by the product of the values of the resistor _R1 and the capacitor _C1 .
Therefore, as shown in FIG. 3A, the control signal a is at time t ₀
When the level is high during periods ~ _t1 and _t5 ~ _t6 , the Q output terminal of the monostable multivibrator 15 outputs T( _{t1 )} for a certain period from time t1 _{and t6} .
~ _t4 , _t6 ~ _t7 ) High level pulses are extracted.
It is supplied to the other input terminal of the OR circuit 16. As a result, high-level pulses b are taken out from the OR circuit 16 during each period of time t ₀ to _{t 4} and t ₅ to t ₇ as shown in FIG. Applied to the input terminal. Further, from the output terminal _of the monostable multivibrator 15 _, a pulse f as _shown in _FIG . It is applied to one input terminal of the circuit 19. Furthermore, the signal whose polarity is inverted and taken out by the inverter 17 is sent to a J-K flip-flop (J-K flip-flop).
KF.F) 20 is applied to the clear terminal CLR to keep it in the clear state during its low level period. J-
In KF.F20, positive DC voltage Vcc is applied to the J terminal, and the output signal of the output terminal is applied to the K terminal.
Further, an output signal from a D-type flip-flop 26, which will be described later, is supplied to the clock terminal CK. On the other hand, a digital video signal is input from the AD converter 3 to the input terminal 22, and a digital video signal selectively output from the bus line controller 4 is input to the input terminal 23. The digital video signal from the input terminal 22 is supplied to a horizontal synchronizing pulse extraction circuit 24, where a horizontal synchronizing pulse with a period of 1H (H is a horizontal scanning period) is extracted and supplied to a monostable multivibrator 25, and its rising edge is extracted. Trigger this. Here, the time constant of the monostable multivibrator 25 is formed by the resistor R ₂ and the capacitor C ₂ , and is approximately half the period of 1H (approximately
31μsec). As a result, the monostable multivibrator 25 is connected to its Q output terminal.
A substantially symmetrical square wave with a period of 1H is outputted and applied to the data input terminal D of the D-type flip-flop 26. On the other hand, the digital video signal input to the input terminal 23 is supplied to a horizontal synchronizing pulse extraction circuit 27 and a vertical synchronizing pulse extraction circuit 35, which will be described later.
The horizontal synchronizing pulse extracted from the horizontal synchronizing pulse extracting circuit 27 is supplied to a waveform shaping circuit 28, where its rising edge portion is extracted, and then applied as a clock pulse to the D-type flip-flop 26, while the shift register 29. The shift register 29 uses a clock pulse (shift pulse) from the input terminal 30 to sequentially shift the pulses that have entered the input terminal, and transfers them to the output terminal.
It is sequentially outputted from Q _A , Q _B , and Q _C and supplied to input terminals 31 ₃ , 31 ₂ , and 31 ₁ of the multiplexer 31 .
The flip-flop 26 outputs a signal obtained by sampling and holding the input pulse at the data input terminal D when the pulse is input from the waveform shaping circuit 28 from its Q output terminal.
Since the readout output digital video signal of the memory 9 is input to the input terminal 23 during a period approximately corresponding to the high level period of the pulse e shown in FIG. A signal of a polarity corresponding to the lead/lag between the phase of the reproduced horizontal synchronizing pulse read from the memory 9 and the phase of the reproduced horizontal synchronizing pulse one track scanning period ago is output to the Q of the flip-flop 26.
It will be taken out from the output terminal. The output signal of the Q output terminal of this flip-flop 26 is the third
The signal c from the output terminal is applied to the clock input terminal CK of J-KF.F20. Here, the periods t ₀ to t ₁ and t ₅ to t 1 during which a low level signal is applied to the clear terminal CLR of J-KF.F20 are
At t ₆ , J-KF.F20 is considered to be in a clear state,
Since a high level signal is output from the output terminal, the input level of the K terminal is also high like the J terminal, and therefore, in this state, the time clock is
After _t1 or after _t5 , the output signal is held high until a clock pulse is received. Therefore, when the clock pulse arrives at time _t2 , the output signal of J-KF.F20 will be at time _t2.
It becomes low level at t, and when it comes in at time t ₃ ,
It becomes low level at t ₃ . As a result, J-KF.
The output signal of F20 becomes signal d as shown in FIG. 3D. In addition, as shown in FIG. 3C, the signal c is from _t5 to
Assuming that the signal d remains at a high level or a low level for a period of t ₈ , the signal d remains at a high level or a low level from t ₆ to t 8 as shown in FIG. 3D.
Since no signal is received during the period _t7 , the high level state is maintained. The above output signal d is supplied to a two-input AND circuit 18, where it is ANDed with the pulse b and converted into a pulse e as shown in FIG. 3E, which is output to the output terminal 7a. When the clock pulse C arrives at time _t2 , the pulse e is at a high level from _t0 to _t2 , when the clock pulse C arrives at time _t3 , it is at a high level from _t0 to _t3 , and from _t5 to _t7 . The period of is also at a high level, and during a period approximately corresponding to this high level period, the memory 9 is controlled to be read and the bus line controller 4 is switched to selectively output the output of the memory 9, and the pulse e is at a low level. During the period approximately corresponding to the period, the memory 9 is
As shown in FIG. 3, writing is controlled and the bus line controller 4 is switched to selectively output the output of the AD converter 3. As will be described later, the control of the bus line controller 4 and the write and read control of the memory 9 are performed by the output signal k of the timing control circuit 8.
As shown in FIGS. A and C, the pulses e and k substantially correspond to each other. Further, the above output signal d is supplied to the NAND circuit 21 together with the output signal of the inverter 17, thereby converting it into the signal g as shown in FIG. 3G.
The signal is supplied to an OR circuit 19, where it is logically summed with the pulse f to form a pulse h as shown in H in the figure. This pulse h is applied to one input terminal of each of the OR circuits 32 and 33. multiplexer 31
is a circuit that selects and outputs one of the input signals of the input terminals 31 ₁ to 31 ₃ from the output terminal according to the input signal of the 2-bit control input terminals A and B. The relationship between the supplied signal level and the input terminal of the input signal selectively output from the multiplexer 31 is summarized as shown in the following table.

[Table] However, in the above table, L indicates low level and H indicates high level. Here, the control input terminal A of the multiplexer 31
The pulses supplied to
This is a pulse obtained through the OR circuit 32, and since the pulse h is normally at a high level, the control input terminal A is also normally at a high level, but from time t ₁ to t ₂ or t ₁ shown in FIG. The low level period of the pulse h from _t3 to the period from _t6 to _t7 is determined by the polarity of the output pulse c of the flip-flop 26 and is indefinite. For example, during the low level period of the pulse h, when the output pulse of the circuit 25 is delayed from the output pulse of the circuit 28, the output signal c of the flip-flop 26 becomes low level, so the control input terminal A also becomes low level. Become. On the other hand, the pulse supplied to the control input terminal B of the multiplexer 31 is a pulse taken out from the output terminal of the OR circuit 33 which takes the logical sum of the pulse h and the low level signal, so it is the same pulse as the pulse h. . Therefore, during variable speed playback, after the rotary head scans a reverse track, it continues for a certain period _of time (t _{1 t2} , _t1 to _t3 , _t6 to _t7 ), the control input terminals A and B are both at high level, so the input pulse of the input terminal ₃₁₂ is output from the multiplexer 31. On the other hand, during the above period, the control input terminal B is at a low level, and the control input terminal A is at a low level when the pulse c is at a low level, so the input pulse of the input terminal 311 is taken out from the multiplexer ₃₁ . When the pulse c is at a high level, the control input terminal A is also at a high level, so the input pulse at the input terminal ₃₁₃ is taken out from the multiplexer 31. Here, the input pulse of the input terminal 31 ₁ is delayed in phase by one period of the shift clock by the shift register ₂₉ with respect to the input pulse of the input terminal 31 2, and the input pulse of the input terminal 31 ₃ is delayed by the phase of the input pulse of the input terminal 31 ₂ . The phase of the shift clock is one period ahead of the pulse. Therefore, the clock pulses (shift pulses) entering the input terminal 30 are transmitted to, for example, an oscillator (not shown).
By selecting a pulse with a repetition frequency equal to the color subcarrier frequency _s , the low level period of the above pulse h is equal to the horizontal synchronizing pulse in the composite video signal currently being played and one track read from the memory 9. The output signal i of the multiplexer 31 (shown in FIG. 3
is gradually advanced or delayed in phase by one period of _s . According to this embodiment, the timing adjustment time is set to the time T determined by the time constant of the monostable multivibrator 15, but even within the adjustment time, the timing adjustment time is set to the time T determined by the time constant of the monostable multivibrator 15. When the phase difference between the horizontal synchronizing pulse and the horizontal synchronizing pulse in the video signal currently being reproduced by the rotating head becomes extremely small (at t ₂ or t ₃ in FIG. 3), the output pulse c of the flip-flop 26 becomes high level, and the output signal d of J-KF.F20 becomes low level, so that the adjustment operation is completed by adjusting the timing of any one of P ₁ , P ₂ , and P ₃ as shown in FIG. The read operation of the memory 9 is terminated, and a switch is made to the write operation. Moreover, even if _the timing adjustment is performed as shown in _P1 ',..., _P4 ' in _FIG . If so, the output pulse c of the flip-flop 26 remains at low level, so J-
The output signal d of KF.F20 remains at a high level until the set time _t7 , and therefore, during the set time T-cup, the memory 9 is read out and the readout is completed at time _t7 , and , the digital signal of the reproduced composite video signal currently being reproduced and output from the rotary head is switched and output from the bus line controller 4. According to the present invention, if the set time T is long enough, the timing adjustment operation will continue during this period. Since the phase difference with the horizontal synchronizing pulse is extremely small and the timings match, the composite video signal currently being reproduced can be switched and output at the time of matching. Note that the time setting (timing adjustment time) for the above period T may have a time lag (one field interval time) between the playback horizontal synchronizing pulses before and after one track scanning period, depending on the model of the VTR, for example. In this case, the time lag may be set in advance according to the time lag. The output pulse i of the multiplexer 31 is also synchronized with the equalization pulse and the vertical synchronization pulse at intervals of 0.5H within the vertical blanking period. Therefore, this pulse i is supplied to an equalization pulse/vertical synchronization pulse extracting circuit 28, where the vertical synchronization pulse and equalization pulse are removed, and the pulse i is converted into a pulse having an interval of 1H, and then outputted to the output terminal 7b. On the other hand, the vertical synchronizing pulse extracted from the vertical synchronizing pulse extraction circuit 35 is waveform-shaped by a waveform shaping circuit 36 and then output to the output terminal 7c. In addition, Fig. 3 I is similar to Fig. 3 A~
The time axis for each waveform of H is shown enlarged. Further, the extraction circuit 34 becomes unnecessary if the horizontal synchronizing pulse extraction circuits 24 and 27 are provided with that function. The timing signal taken out from the output terminal 7b is supplied to the timing control circuit 8 shown in FIG. 1 together with the pulse taken out from the output terminal 7a. The timing control circuit 8 operates as shown in FIG. 4B based on the clock pulse whose repetition frequency is equal to the color subcarrier frequency s obtained by shaping the input clock pulse at the input terminal 30 and the timing signal from the terminal 7b. A signal j having a waveform that rises in phase synchronization with, for example, the rising edge of the clock pulse is generated. Here, the timing signal from terminal 7b comes in every 1H (=227.5/s), but the color subcarrier frequency s is the horizontal scanning frequency.
Since the frequency is 227.5 times higher than _H , the phase is reversed every 1H, but as mentioned above, the signal j shown in Figure 4B is generated that rises only in phase synchronization with the rise of the clock pulse with the repetition frequency s. Then, the phase of the color subcarrier and the phase of the rising edge of signal j always have the same relationship. Thus, the time interval from any spurious rising edge of signal j to the next rising edge will be 227/s or 228/s, but if the timing adjustment described above is made, it will become 226/s or 229/s. It will be corrected so that The timing control circuit 8 generates the above signal j and supplies it to the clock input terminal of the D-type flip-flop inside the circuit 8, and also inputs the input pulse e from the terminal 7a shown in FIG. 4A (as shown in FIG. 3E). The circuit is constructed so that a pulse (same as the shown pulse e) is applied to the data input terminal of the D-type flip-flop, and the flip-flop outputs a signal k as shown in FIG. 4C. This signal k is generated and output as a control signal for the memory 9 and bus line controller 4 shown in FIG. On the other hand, during the high level period of the signal k, the memory 9 is read out and the bus line controller 4 is switched to the selected output state of the output of the memory 9. According to this embodiment, in the timing adjustment section, the horizontal scanning period is 226 s or 229/s.
Although this is different from the normal value of 227.5/s, the error is sufficiently small and does not pose a problem in practice. As a result, when switching from one of the readout signal and the currently reproduced signal to the other, the connection is made on the same phase of the color subcarrier frequency,
Connection is extremely stable. Effects As described above, according to the present invention, during variable-speed playback, the period surrounding the period including the period in which the level of the reproduced composite video signal currently being played becomes smaller than a certain value is one track scanning period earlier than that period. Since the digital video signal of the reproduced composite video signal in the corresponding section is read out from the memory and replaced with the reproduced composite video signal currently being reproduced, the S/
It is possible to obtain a reproduced composite video signal output of good image quality without deterioration of the N ratio, and near the end of reading the memory, the relative phase between the read output signal and each horizontal synchronization pulse of the composite video signal being reproduced can be obtained. Since the lead/lag of the signal is detected and the readout output timing is controlled to minimize it, it is possible to faithfully reproduce the digital video signal written in the memory, and also to match the composite video signal currently being played. Reading can be completed when the horizontal synchronization signal phase timings approximately match, and since the color subcarrier frequency is also controlled, replenishment of a certain line interval of the composite video signal being reproduced can be performed approximately one track scanning period before. When performing video signals with the same line spacing, signal connections can be made smoothly without compromising the phase continuity of color subcarriers, significantly improving image quality, and within a predetermined timing setting time. Even if the readout output signal and the composite video signal being played back have both horizontal synchronization signal phases that substantially match, the timing adjustment is finished and the switch is made to the composite video signal being played back, so the timing adjustment time and The memory read period can be shortened, and it is possible to shorten the memory read period between 1 field (within 1 track scanning period).
It is more effective in cases where the playback FM signal level frequently decreases, and by shortening the memory read period, it is possible to obtain more information on the playback image currently being played. It has certain characteristics.

[Brief explanation of the drawing]

Fig. 1 is a block system diagram showing one embodiment of the device of the present invention, Fig. 2 is a circuit system diagram showing an embodiment of the main part of the block system shown in Fig. 1, and Figs. 4A to 4C are signal waveform diagrams for explaining the operation of other main parts of the device of the present invention, respectively. 1...Reproduction composite color video signal input terminal, 3...
...AD converter, 4...Bus line controller,
5, 8...Timing control circuit, 6...Control signal input terminal, 7a-7c...Output terminal, 9...Memory, 10...Address signal generation circuit, 11...
DA converter, 13... Reproduction composite color video signal output terminal, 15, 25... Monostable multivibrator, 20... J-K flip-flop (J-KF.
F), 22, 23...Digital video signal input terminal, 24, 27...Horizontal synchronization pulse extraction circuit,
26...D-type flip-flop, 29...Shift register, 30...Clock pulse input terminal, 3
1... Multiplexer, 35... Vertical synchronization pulse extraction circuit.

Claims (1)

[Scope of utility model registration request] The speed is different from that at the time of recording, and any one
The vehicle is caused to run at such a speed that, for a section in which the level of the reproduced signal is lower than a certain value during the track scanning period, a reproduced signal having a level higher than the certain value is obtained in the corresponding section one track scanning period before. an AD converter that converts a composite video signal reproduced from a recording medium whose running has been stopped into a digital video signal; a memory having a capacity capable of storing at least one field of digital video signals; and an output of the AD converter. a switch means for selectively outputting either the signal or the readout output signal of the memory; and a switch means for selectively outputting either one of the signal and the readout output signal of the memory; period is applicable
Instead of the output signal of the AD converter, the switch means selectively outputs the digital video signal of the corresponding section one track scanning period ago, which is read from the memory. control means for selectively outputting the output signal of the converter and writing the output signal of the AD converter into the memory; The relative lead/lag of the phases is detected, the read timing of the memory is controlled so that these phases become small, and when the detected phases substantially match, the control means is activated even within the certain period. A video signal processing device comprising: readout control means for terminating the readout operation of the memory; and an output signal for obtaining a reproduced composite video signal from the output signal of the switch means.