JPH043713B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal processing device, and in particular, when writing or reading a digital video signal to or from a memory, a reference signal for an address signal is generated based on a horizontal synchronization pulse and a vertical synchronization pulse. The present invention relates to a video signal processing device that generates a video signal.

Conventional technology and its problems In helical scanning VTR,
During variable speed playback, in which recorded video signals are played back by running (or stopping) a recorded magnetic tape at a tape running speed different from that during recording, the relative speed between the tape and the head is different from that during recording, so the head scanning trajectory changes. It is well known that the marks are drawn at a different slope from the recorded tracks. For this reason, adjacent tracks are recorded by rotary heads having gaps with different azimuth angles, respectively.
During variable speed playback of a magnetic tape with a track pattern in which there is no guard band or only a very small guard band is formed between the tracks, the playback rotary head rotates with a gap of the same azimuth angle as itself per one track scanning period. The track recorded by the head and the track recorded by the rotary head (reverse track) having a gap of different azimuth angle are scanned alternately, and therefore, during reverse track scanning, the track is reproduced due to the azimuth loss effect. The signal level becomes extremely low and the S/N ratio deteriorates. Similarly, during variable speed playback of a magnetic tape with a track pattern in which a guard band of a sufficient constant width is formed between adjacent tracks, the guard band is crossed more than once per track scanning period, so when the guard band is scanned, The reproduced signal level becomes extremely low and the S/N ratio deteriorates.

Therefore, the present applicant previously filed a patent application dated January 18, 1982 (title of invention "Video signal processing device").
In the section where the playback FM signal level becomes extremely low during variable speed playback, etc., the 1
We have proposed a video signal processing device that replaces the reproduced composite video signal with a substantially equivalent section before the track scanning period.
In this proposed device, when writing the reproduced composite video signal to the memory through the AD converter or reading out the digital video signal of the reproduced composite video signal one track scanning period ago from the memory, the address command signal is sent based on the horizontal synchronization pulse and the vertical synchronization pulse. is being generated.

However, during variable speed playback, there is some error (time difference) in the period of the horizontal synchronizing pulse in the reproduced composite video signal.
In addition, horizontal synchronization pulses and vertical synchronization pulses may be missing due to dropout, etc., resulting in a problem that writing and reading operations of the memory may become unstable.

SUMMARY OF THE INVENTION An object of the present invention is to provide a video signal processing device that solves the above problems by measuring and calibrating the horizontal scanning period of an input composite video signal at arbitrary intervals.

Means for Solving the Problems The present invention is a video signal processing device that generates a reference signal for an address signal of a memory, which uses first and second counters and an output count value of the first counter. 1 of the number of times the first counter is cleared
Generates and outputs the first pulse of one horizontal scanning period at the time when the time obtained by subtracting the first set time from the horizontal scanning period has elapsed, and at the same time generates and outputs the first pulse of one horizontal scanning period after the clearing time, and calculates the first set time from one horizontal scanning period after the cleared time. gate circuit means for generating and outputting a second pulse for a period from when a time equal to or greater than a second set time has elapsed until the first counter is cleared next time; a delay circuit that applies a plurality of delay times to one pulse and outputs them in parallel; a holding means that temporarily holds a count value of the second counter that is cleared by the second pulse; a comparison/counting means that counts pulses of a constant period, controls the counting direction so that the counted value becomes equal to the counted value of the holding means, and stops the counting operation when the two become equal;
A selection circuit selectively outputs - of the parallel output signals of the delay circuits having different delay times according to the count value of the comparing/counting means, and a gate outputting the input horizontal synchronizing pulse only during the output period of the second pulse. and a logic circuit that clears the first counter approximately every horizontal scanning period based on the pulse obtained from the horizontal scanning pulse, and also clears the counter based on the output pulse of the selection circuit when the horizontal synchronizing pulse is missing. , and is configured to generate and output the first or second pulse as the reference signal, and an embodiment thereof will be described below with reference to the drawings.

Embodiment FIG. 1 shows a block system diagram of an embodiment of the apparatus of the present invention. In the figure, a reproduced composite color video signal is input to an input terminal 1. This reproduced composite color video signal is produced by frequency modulating (FM) the luminance signal, frequency converting the carrier color signal to a low frequency band, frequency division multiplexing these two signals, and transmitting one field to one track using a rotating head. The magnetic tape recorded on successive tracks is played back at various speeds, the FM luminance signal in the playback signal is FM demodulated, the low frequency conversion carrier color signal is frequency converted to the original band, and these two signals are combined. This is a reproduced composite color video signal that is obtained by multiplexing and substantially conforms to the standard format. In addition, when the variable speed playback described above is applied to a VTR using the azimuth recording/playback method, the magnetic tape is moved (or ), thereby at least one part of the section in which the rotary head scans the reverse track.
In the corresponding section before the track scanning period, a reproduced signal was normally obtained by another rotary head.

The reproduced composite color video signal inputted to the input terminal 1 is supplied to the AD converter 3 via the amplifier 2, where it is analog-to-digital converted into a digital video signal, and then sent to the bus line controller 4 and the first are supplied to the timing control circuits 5, respectively. The timing control circuit 5 is supplied with a control signal from an input terminal 6 along with digital video signals from both the input and output sides of the bus line controller 4 . This control signal is, for example, at a high level during the period when the amplitude of the FM luminance signal reproduced from the rotating head while scanning the magnetic tape becomes smaller than a certain value due to reverse track scanning, and at a low level during a period when the amplitude is above this certain value. This is a binary signal generated so that The timing control circuit 5 outputs a pulse synchronized in phase with the control signal to the second timing control circuit 8 from the output terminal 7a.

Further, the timing control circuit 5 outputs the horizontal synchronization pulse from which the equalization pulse and the vertical synchronization pulse have been removed from the output terminal 7b and supplies it to the timing control circuit 8, while the vertical synchronization pulse is waveform-shaped and obtained from the output terminal 7c. A pulse is output and supplied to the address signal generation circuit 10. The timing control circuit 8 generates a signal controlled by the color subcarrier frequency based on the signal from the terminal 7a and supplies it to the bus line controller 4 for switching control, and also controls the memory based on this signal. CAS (column address strobe) signal, RAS (row address strobe) signal, WE (read/write control) necessary for reading and writing 9.
It generates signals and supplies them to the memory 9, and also outputs signals to the address signal generation circuit 10. Address signal generation circuit 10 generates an address signal and supplies it to memory 9. The memory 9 is, for example, a random access memory (RAM), which is a field memory with a storage capacity capable of storing one field's worth of digital video signals, and its readout output signal (digital video signal) is supplied to the bus line controller 4. , and also writes the digital video signal taken out from the bus line controller 4.

The digital video signal selectively output from the bus line controller 4 is sent to a timing control circuit 5,
The signal is supplied to the memory 9 and the DA converter 11, respectively.
The DA converter 11 performs digital-to-analog conversion on the input digital video signal, returns it to a composite color video signal which is an analog signal, and outputs it to the output terminal 13 through the amplifier 12. Here, the memory 9 normally stores the output digital video signal of the AD converter 3 supplied via the bus line controller 4, but when the rotary head performing variable speed playback scans the reverse track, the As such, the memory 9 is switched to read control for at least a period including the scanning period, and the bus line controller 4 selects and outputs the reproduced digital video signal of the same period one track scanning period ago, read from the memory 9. Therefore, the reproduced composite color video signal at the output terminal 13 is normally the reproduced composite color video signal of the current field reproduced by the rotary head currently scanning the magnetic tape, but the reverse track scanning period is one track scanning period before. This is replaced by a reproduced composite color video signal of a corresponding section of a different field (if the current field is an odd field, an even field; if the current field is an even field, an odd field). This makes it possible to prevent deterioration of the S/N ratio during reverse track scanning.

The present invention is a video signal processing device characterized by the configuration of the timing control circuit 5 in the above device. FIG. 2 shows a circuit diagram of one embodiment of the timing control circuit 5. As shown in FIG. In the figure, a digital video signal from the bus line controller 4 that has entered the input terminal 14 is supplied to a horizontal synchronizing pulse extracting circuit 15 and a vertical synchronizing pulse extracting circuit 16, respectively. Note that the timing control circuit 5 is the AD converter 3.
It also has an input terminal to which a digital video signal is directly supplied without passing through the bus line controller 4, and a processing circuit for the input signal.
Since this processing circuit has no direct relation to the present invention, its explanation and illustration will be omitted.

The horizontal synchronizing pulse extraction circuit 15 has a circuit configuration that measures the high level of the input digital video signal using a counter or the like for a certain period of time, and uses this to distinguish the horizontal synchronizing pulse from the video signal. In addition to the horizontal sync pulse, the terminal also contains a vertical sync pulse and an equalization pulse. The output pulse of the horizontal synchronizing pulse extraction circuit 15 is converted by the waveform shaping circuit 17 into a pulse a of a constant width as shown in FIG. 3, which falls in synchronization with the rising edge of the output pulse. It is assumed that the pulse a is 0.5H (H is the horizontal scanning period) in the period corresponding to the vertical synchronization pulse and the equalization pulse, and that the pulse is missing for some reason at time _t3 .

Pulse a is applied to the clear terminal CLR of the first counter 20 through NOR circuits 18 and 19, respectively. The counter 20 counts the clock pulses input from the input terminal 21 after being cleared, and supplies the n-bit count output signal to the gate circuit 22. The gate circuit 22 outputs a pulse of a constant width from its output terminal A when the count value from the counter 20 reaches a value indicating the time of 1H- _tX , and
A pulse is output from its output terminal B. As a result, the pulse b shown in FIG. 3 is output from the output terminal A of the gate circuit 22 and is output to the output terminal 7b (same as 7b in FIG. 1), while being supplied to the shift register 25. Further, a pulse c shown in FIG. 3 is taken out from the output terminal B of the gate circuit 22. Pulse c is a pulse that becomes low level when the counter 20 is cleared, and is supplied to the NOR circuits 18 and 24 via the inverter 23, and is also supplied to the clear terminal of the second counter 26.

The shift register 25 receives the pulse b at the input terminal 27.
The clock pulses (shift pulses) are sequentially shifted in accordance with the clock pulses (shift pulses), and pulses b sequentially delayed by periods equal to a natural number multiple of one period of the clock pulse are outputted from the plurality of output terminals and supplied to the multiplexer 32. Further, the counter 26 is cleared during the low level period of the pulse c, and counts the clock pulses from the input terminal 27 during the high level period of the pulse c. Therefore, the count value of the counter 26 is equal to the pulse c
The count value signal is supplied to the latch circuit 28, where it is latched at the time when the output pulse d of the pulse generation circuit 29 is generated. The pulse generation circuit 29 is a circuit that generates and outputs an extremely narrow pulse with a constant period of any natural number multiple of 1H (or every field based on the vertical synchronization pulse) based on the horizontal synchronization pulse a, and is used in this embodiment. As an example, the phase synchronization with the horizontal synchronization pulse a is shown as d in Figure 3.
A pulse with a 3H period and a pulse f with a 3H period delayed by a time _tz as shown in FIG. 3 from the pulse d are generated and output, respectively.

Therefore, _{the count value D 1 indicating the length of the period T 1 ( = t} The output pulse of circuit 29 latches into latch circuit 28. As a result, the latch circuit 28
The count value D ₁ is held until the pulse d ₂ is supplied from the pulse generation circuit 29 after 3H, and the pulse d ₂ is
At the time when the pulse c enters, the count value _D2 indicating the length of the high level period _T4 of the pulse c shown in FIG. A count value indicating the length of the period is updated and stored. As a result, the latch circuit 28 outputs the data (count value) shown at e in FIG. 3, and supplies it to the first input terminal of the magnitude comparator 30.

On the other hand, the up-down counter 31 receives the pulse f applied to its clock input terminal. The count value of the up-down counter 31 is applied to the second input terminal of the comparator 30, while being applied to the multiplexer 32. The comparator 30 compares the count value from the latch circuit 28 (this is referred to as D) and the count value from the up-down counter 31 (this is referred to as E), and as a result of the comparison, from the output terminal High level (when D>E) or low level (D<
generates and outputs a signal (when E) and supplies it to the up/down count control terminal U/D of the counter 31;
In addition to controlling its counting direction, its output terminal Y
A signal of a higher level (when D=E) or a lower level (when D≠E) is generated and outputted and supplied to the enable terminal EN of the counter 31.

The counter 31 is controlled so that it performs addition counting when the input signal at the control terminal U/D is at a high level, and performs subtraction counting when it is at a low level, but is inhibited when the input signal at the enable terminal EN is at a high level. , since the counter 31 is configured to stop counting, when D≠E, the counting direction is controlled according to the magnitude, and D=E.
The counting operation will be stopped only when . In this embodiment, the data in the latch circuit 28 is rewritten as D ₀ , D ₁ , D ₂ , etc. every 3H, and the comparator 30 determines whether the data is larger or smaller than the count value of the up-down counter 31. The comparison result is fed back to the up-down counter 31, which determines the output count value of the counter 31, and the count value of the up-down counter 31 gradually converges in the direction of the count value of the latch circuit 28 every 3H. It becomes equal to the count value of the latch circuit 28.

On the other hand, the multiplexer 32 is connected to the shift register 2
Among the 5 parallel output signals, the negative output signal is selected and output according to the output count value of the up-down counter ₃₁ , and the ₁ The output pulse of the shift register 25 delayed by the clock cycle is selectively output. That is, the pulse b is taken out from the multiplexer 32 while the delay amount (a natural number multiple of the input clock pulse period of the input terminal 27) is automatically and variably controlled by the multiplexer 32 in accordance with the horizontal synchronizing pulse interval. The output signal of the multiplexer 32 becomes a pulse as shown by g in FIG.
This pulse g is converted by the waveform shaping circuit 33 into a narrow pulse that becomes low level in phase synchronization with the rising edge portion of the pulse g, and is then supplied to one input terminal of the NOR circuit 24.

Now, at time t ₁ when pulse a arrives, the output pulse c from output terminal B of the gate circuit 22 is set so that the high level period is longer than t _Y when the counter 20 is not cleared. Therefore, the output signal of the inverter 23 is at a low level, and the output of the NOR circuit 18 is therefore at a high level. Further, the output pulse of the waveform shaping circuit 33 becomes a low level in phase synchronization with the rising edge of the pulse g, and is normally a high level, so that at time t ₁
In this case, the output of the NOR circuit 24 is at a low level.
Therefore, the output of the NOR circuit 19 to which the output pulses of the NOR circuits 18 and 24 are supplied becomes low level at time _t1 , and the counter 20 is cleared. As a result, the output pulse c of the input terminal B of the gate circuit 22 becomes a low level immediately after time _t1 , and the output signal of the NOR circuit 18 and the output signal of the NOR circuit 19 each become a pulse with an extremely narrow pulse width.

Here, by selecting the above-mentioned time _t Since it remains at a low level after H has elapsed, the NOR circuit 18 does not accept the pulse a, and its output remains at a low level. Therefore, pulse a is
If the pulse train arrives at an interval of 0.5H, the transmission of every other pulse train is blocked by the NOR circuit 18, so that the counter 20 is cleared every 1H period. Therefore, pulse a is 1H or
When input with a 0.5H period, the output of the NOR circuit 18 is always a positive pulse with a 1H period,
The output of the NOR circuit 24 is at a low level as shown by h in FIG. , a pulse that rises a time t _X before the fall of the pulse every 1H is extracted.

Next, to explain the operation when pulse a is lost at time _t3 , the counter 20 has been reset by the pulse a that arrived at time _t2 , 1H before time _t3 , so from time _t3 A high-level pulse c is taken out from the output terminal B of the gate circuit 22 at a time _tX , and a pulse b is output from the output terminal A of the gate circuit 22 at a time _tX before time _t3 . On the other hand, assuming that the count value of the up-down counter 31 is equal to the output count value of the latch circuit 28, the pulse a is input from the parallel output signal of the shift register 25 before the time _t3 when it should originally arrive from the multiplexer 32. The pulse g ₁ shown in FIG. 3 is delayed by one period of the clock pulse from terminal 27.
is selected and output. Therefore, if the pulse a does not arrive at the time _t3 when it should have arrived, the output of the NOR circuit 18 remains at a low level, but even in this case, the pulse _g1 does not arrive immediately after the time _t3 . is taken out, and at the rising edge of the pulse, a low level pulse that is phase synchronized with the part is applied from the waveform shaping circuit 33 to the NOR circuit 24, so that both inputs of the NOR circuit 24 become low level. A high-level pulse h shown in FIG. 3 is output in phase with the rising edge of pulse _g1 .

Therefore, among the output pulses of both NOR circuits 18 and 24 supplied to NOR circuit 19, NOR circuit 1
Even if the output of the NOR circuit 8 remains at a low level due to the omission of the pulse a, the output of the NOR circuit 24 becomes a high level as shown by h in FIG. Accordingly, a pulse that becomes low level is taken out and the counter 20 is cleared. By clearing the counter 20, the high level period of pulse c becomes a period _T3 ' which is longer than the original period _T3 by one period of the clock pulse.
Also, at the time when 1H- _t
The pulse indicated by bo ₁ will be extracted.

In this way, the time when pulse a should originally arrive
Even if it does not arrive at t ₃ , the counter 20 will be approximately
Since it is reset every 1H period, pulses are normally taken out to the output terminal 7b every about 1H period, as shown by bo ₁ in FIG.

FIGS. 4A and 4C show the output pulse waveforms near the vertical synchronization pulses of odd and even fields extracted from the horizontal synchronization pulse extraction circuit 15, so that the output terminal 7b has the timing shown in B and D of the same figure. A pulse with a period of 1H is extracted. On the other hand, the vertical synchronizing pulse extraction circuit 16 shown in FIG. 2 extracts the vertical synchronizing pulse l shown in FIG. 4E. The waveform shaping circuit 34 uses this vertical synchronizing pulse l.
A narrow pulse m as shown in FIG. 4F rising in phase synchronization with the falling edge of is generated and output to the output terminal 7c.

The pulse b (or the pulses shown in FIG. 4B and D) output from the output terminal 7b is supplied to the timing control circuit 8 in FIG. converted. That is, the address counter in the address signal generation circuit 10 consists of a row address counter and a column address counter, and the row address counter is reset by the pulse m from the output terminal 7b and counts the pulse b of the 1H period. , outputs the counting output to the memory 9 as a row address signal to designate a row address. Further, the column address counter uses the pulse b as a clear signal and counts a clock signal based on the color subcarrier frequency.

In this way, the signal written to the memory 9 is
The address signal is determined by each control signal based on this, and based on the signal read from the memory 9 via the bus line controller 4,
Each control signal is created and addressed similarly.

In this example, the pulse b (FIG. 4B,
By determining the presence or absence of pulses shown in D, odd and even fields can be easily determined.

Incidentally, as shown by d ₁ and d ₂ in FIG. 3, the time interval for calibration is determined by the pulse d outputted from the pulse generation circuit 29 to the latch circuit 28 at a 3H cycle, and this interval is Can be set arbitrarily. Further, a configuration may be adopted in which the output pulse c of the output terminal B of the gate circuit 22 is outputted to the output terminal 7b and the shift register 25, respectively. Furthermore, the rising edge of pulse c may precede that of pulse b by a small period of time.

Effects As described above, according to the present invention, a reference signal for an address signal is generated and output based on the count values of the first and second counters that count clock pulses of a constant frequency, and the delay of the signal serving as the reference signal is reduced. The time is selected according to the count value of the comparison/counting means controlled to be equal to the count value of the second counter, and from the delayed signal, a signal based on the count output of the first counter, and the horizontal synchronization pulse. Since the clear timing of the first counter is set, when writing to memory, it is based on the horizontal synchronizing signal in the composite video signal written, and when reading from memory, it is based on the horizontal synchronizing signal in the composite video signal read out. It is possible to generate and output an optimal reference signal for the address signal based on the , and also to automatically follow the interval of horizontal synchronizing pulses to determine the clearing timing of the first and second counters, regardless of the mode. It is possible to approximately correct the reference signal of the address signal under the optimum condition, and even if there is an instantaneous dropout, the above reference signal can be stably generated and output at approximately 1H intervals. At the same time, when pulses arrive at 0.5H intervals due to equalization pulses, vertical synchronization pulses, etc., or when unnecessary signals or noises come within 1H, the signal will be ignored without responding to these signals.
The above reference signal can be generated and output in a 1H cycle, and from the above, memory writing and reading operations can be stabilized, and a good address (command) can be obtained.
It has the advantage of being able to control memory writing and reading operations by generating signals.

[Brief explanation of drawings]

FIG. 1 is a block system diagram of an embodiment of the device of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the essential parts of the device of the invention, and FIGS.
FIG. 3 is a signal waveform diagram for explaining the operation of the illustrated circuit system. 1...Playback composite video signal input terminal, 3...AD
Converter, 4... Bus line controller, 5, 8
... Timing control circuit, 6 ... Control signal input terminal, 9 ... Memory, 10 ... Address signal generation circuit, 11 ... DA converter, 14 ... Digital video signal input terminal, 15 ... Horizontal synchronization pulse extraction Circuit, 16... Vertical synchronization pulse extraction circuit, 20,
26... Counter, 21, 27... Clock pulse input terminal, 22... Gate circuit, 25... Shift register, 28... Latch circuit, 29... Pulse generation circuit, 30... Magnitude comparator (comparator) , 31...up-down counter,
32...Multiplexer.

Claims (1)

[Claims] 1. When writing a composite video signal to a memory and reading it, the composite video signal written to the memory is supplied when writing to the memory, and the composite video signal read from the memory is supplied when reading from the memory. , a video signal processing device that generates a reference signal of an address signal based on a horizontal synchronization pulse and a vertical synchronization pulse in the input composite video signal, the video signal processing device comprising first and second counters that count clock pulses of a constant frequency; A first pulse of one horizontal scanning period after the time when the first counter is cleared based on the output count value of the first counter, when a time period obtained by subtracting the first setting time from one horizontal scanning period has elapsed. and generates and outputs the first counter from the point in time after the clearing time, when a time period obtained by subtracting a second set time equal to or larger than the first set time from one horizontal scanning period has elapsed. gate circuit means for generating and outputting a second pulse for a period until the second pulse is cleared next; a delay circuit for providing a plurality of delay times to the first pulse and outputting them in parallel; holding means for temporarily holding the count value of the second counter which is cleared by the pulse of the second counter and outputs a count value corresponding to the width of the second pulse; Comparing and counting means that compares the counted values of the holding means and controls the counting direction so that both become equal, and stops the counting operation when both become equal; a selection circuit that selects and outputs - of the parallel output signals of the delay circuits having different delay times, and a pulse obtained by gate-outputting the input horizontal synchronizing pulse only during the output period of the second pulse; a logic circuit that clears the first counter approximately every horizontal scanning period, and also clears the counter based on the output pulse of the selection circuit when the horizontal synchronization pulse is missing; A video signal processing device configured to generate and output a pulse as the reference signal.