JPS63102575A - Video disk player - Google Patents

Video disk player

Info

Publication number
JPS63102575A
JPS63102575A JP61248920A JP24892086A JPS63102575A JP S63102575 A JPS63102575 A JP S63102575A JP 61248920 A JP61248920 A JP 61248920A JP 24892086 A JP24892086 A JP 24892086A JP S63102575 A JPS63102575 A JP S63102575A
Authority
JP
Japan
Prior art keywords
signal
circuit
video signal
phase
horizontal synchronizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP61248920A
Other languages
Japanese (ja)
Inventor
Yukio Sugimura
杉村 幸生
Toshiaki Kumoi
雲井 俊朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP61248920A priority Critical patent/JPS63102575A/en
Publication of JPS63102575A publication Critical patent/JPS63102575A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the disorder of a time base due to the discontinuity of the horizontal synchronizing signal of a reproducing video signal written into a memory after the track is jumped by controlling the rotation of a disk so as to coincide the phase of the horizontal synchronizing signal and a reference signal in a reproducing video signal. CONSTITUTION:A reproducing video signal N obtained by a pick-up 2 is inputted to a horizontal synchronizing separating circuit 16, only a horizontal synchronizing signal Hsync is extracted, the phase comparing with a reference signal from a reference signal generating circuit 18 is executed by a phase comparing circuit 17 and a phase error signal equivalent to the phase difference is supplied to a spindle motor servo circuit 19. While the discontinuity of the Hsync of the reproducing video signal occurs immediately after the track jumping after a kicking pulse (a) occurs, a detecting signal (f) is not supplied to a writing control circuit 11 as a writing command signal (h), writing is executed only when the time base control is normal, and the static image signal comes to be the picture in which the Hsync is continuous and stable.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明に、線速度一定に映像信号が記録されtビデオデ
ィスクプレーヤの特殊再生に関する0(ロ)従来の技術 所謂LV方式のビデオディスクには、トラ・ンクー回転
当りに2フイールドづつ角速度一定に記録されmcAV
ディスクと、線速度が一定となる様に記録されたCLV
ディスクとがある。
DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field The present invention relates to the special playback of a video disc player in which a video signal is recorded at a constant linear velocity. is recorded at a constant angular velocity of 2 fields per trunk rotation, and mcAV
Disk and CLV recorded so that the linear velocity is constant
There is a disc.

CAVディスクぼ、半径方向に同期信号が一列に並んで
記録されているため、ディスクを走査するピックアップ
を半径方向にトラックジャンプさせても水平同期信号の
不連流による時間軸の変動に生じることがなく、スチル
等の特殊再生が可能となるのぼ周知の事実である。
On CAV discs, synchronization signals are recorded in a line in the radial direction, so even if the pickup that scans the disc jumps tracks in the radial direction, fluctuations in the time axis due to discontinuous flow of horizontal synchronization signals will not occur. This is a well-known fact that allows special reproduction of stills and the like.

−7、CLVディスクに、半径方向の同期信号が一列に
並んでいないため、トラ・ツクジャンプの前後で再生同
期1訂号が不連続となる。又、所定のディスクの回転数
が異なり、時間用制惧が大きく乱n、再生出力画面ζ色
おちや垂直同期の乱れ、水平スキュー等が発生し、特殊
再生(グ困碓であつ7tn そこで、特開昭58−159577号公報(HD4N5
/93)に先行技術として示される様にCLVディスク
における特殊再生時に、所定の1フレームの信号を別の
メモリー手段に記憶せしめ、そのメモリー手段からの信
号を操り返し出力させることが考えられる。
-7. Since the synchronization signals in the radial direction are not lined up in a line on the CLV disk, the reproduction synchronization number 1 is discontinuous before and after the track jump. In addition, the rotational speed of a given disc is different, and the time limit is greatly disturbed, and the playback output screen ζ color distortion, vertical synchronization disturbance, horizontal skew, etc. occur, and special playback (difficult) occurs. Japanese Unexamined Patent Publication No. 58-159577 (HD4N5
It is conceivable to store a predetermined one-frame signal in another memory means, and to manipulate and output the signal from the memory means during special playback on a CLV disc, as shown in the prior art in No. 1999/93).

(ハ) 発明が解決しようとする間印点前記従来技術に
示される様に、メモリー手段によって一画面分の再生映
像信号を記tはせしめることにより、CLVディスクに
ひいても特殊再生が可能となるが、メモリー手段への再
生映像信号の書込み時に、トラックジャンプ直後の水平
同期信号の不連続が発生していると、時間軸制御が乱れ
た状態で再生映像信号を書き込むことになり、これ全読
み出した場合、乱れt画面となって安定な特殊再生が為
されないことになるコ前記従来技術ζ、この間J点?解
決する手段についての示唆がない。
(C) Points to be Solved by the Invention As shown in the above-mentioned prior art, special reproduction is possible even on CLV discs by recording one screen worth of reproduced video signals in a memory means. However, when writing the playback video signal to the memory means, if a discontinuity occurs in the horizontal synchronization signal immediately after a track jump, the playback video signal will be written in a state where the time axis control is disrupted, and this will result in a complete failure. If it is read out, the screen will be distorted and stable special playback will not be possible.In the prior art ζ, during this time point J? There is no suggestion of a solution.

に)間0点を解決するための手段 本発明に、線速度一定に成像信号が記録されたディスク
全走査して、特殊再生時にトラックジャンプが為される
ピックアップと、このピックアップに工9得られる再生
映像信号の一画面分全静止画像信号として記憶するメモ
リー手段と、再生映像信号中の水平同期信号と基準信号
との位相を比較する位相比較平段と、位相が一致する様
にディスクの回転?制御する回転制御手段と、水平同期
信号と基準信号との位相差が所定値を越える時にメモリ
ー手段への再生映像信号の書込みを禁止する書込み制御
手段とから成ることを特徴とする□(ホ)作 用 本発明は上述の如く構成したので、CLVディスクのト
ラックジャンプ時においても、時間軸制御が正常な再生
映像信号がメモリー手段に書き込まれる。
2) Means for solving the 0-point problem The present invention provides a pickup in which a disk on which an imaging signal is recorded at a constant linear velocity is scanned over the entire disk and a track jump is performed during special playback, and this pickup has nine techniques. A memory means for storing one screen of the reproduced video signal as a full still image signal, a phase comparison stage for comparing the phases of the horizontal synchronization signal in the reproduced video signal and the reference signal, and rotation of the disk so that the phases match. ? □ (E) characterized by comprising: a rotation control means for controlling; and a write control means for prohibiting writing of the reproduced video signal into the memory means when the phase difference between the horizontal synchronization signal and the reference signal exceeds a predetermined value. Operation Since the present invention is constructed as described above, even when a track jump is performed on a CLV disc, a reproduced video signal with normal time axis control is written into the memory means.

(へ)実施例 以下、図面に従い本発明の一実施例について説明する□ 第1図ζ本実施例装支の回路プロ、ンク図、第2図にタ
イミングチャートであるn尚、本実施例は特殊再生時の
%高速再生について説明する一1槃高速再生時には、C
LVのディスクtl+の走査によりピックアップ+2+
 jり得られる再生映像信号(N)が、垂直同期分離回
路13;にて同期分離されて得られる垂直同期信号(V
s’yJ1C)(C)’iM個カウントして出力される
)即ちMVsylc毎にVsyncの前縁でシスコン(
3;ヨリキックパルス(a)が発せられる。尚、本実施
例で1n−7の場合について説明している。
(F) Example Hereinafter, one embodiment of the present invention will be explained according to the drawings. □ Fig. 1 shows the circuit diagram of the system of this embodiment, and Fig. 2 shows a timing chart. Explaining % high-speed playback during special playback. During high-speed playback, C
Pickup +2+ by scanning LV disk tl+
The reproduced video signal (N) obtained is synchronously separated in the vertical synchronous separation circuit 13;
s'yJ1C) (C)' iM counts and output) In other words, for each MVsylc, the system controller (
3; Yoli kick pulse (a) is emitted. In this embodiment, the case of 1n-7 is explained.

このキックパルス(a )i、ピックアップドライブ回
路(41に入力される□このピックアップドライブ回路
+41iトラツキング耶1@回路・AMP )う、ソキ
ングコイルにて構成され、キックパルス(a)はトラッ
キング■!御回路を経て増幅されt後、トラッキングコ
イルに印加され、ピックアップ+21のトラックジャン
プが為される。
This kick pulse (a) i is composed of a pickup drive circuit (input to 41 □ this pickup drive circuit + 41i tracking 1 @ circuit/AMP), and the kick pulse (a) is composed of a tracking coil! After being amplified through a control circuit and applied to a tracking coil, a pickup +21 track jump is performed.

このキックパルス(a)で、Q出力がVsyncカウン
タ+61のリセット入力となっているR−8フリフブフ
ロツプ15+かリセット1れ信号(b)を発する□即ち
、キックパルス(a)によりVsyncカウンタ(6−
のリセットが解除され、Vsync (C)のカウント
が開始される□ vsyncカウンタf61i (M −2)カウントを
為すと、その出力がLレベルからHレベルに移行する様
に設定されている□キックパルスta)i生後、Vsy
nc (C)がCM−2)個カウントされると、Vsy
ncカウンタ(6−ハカウントパルス(d)を発し、こ
のカウントパルス(d)がR−8FF +71’i −
i= 、卜する一、R−8FF171rzVsync 
(C)全遅延回路(8)にて一定時間(1)遅延せしめ
定信号(C)でリセットされ、その出力i(e )の如
く立下がる。尚、遅延時間(t)iトラックジャンプ以
後、CM−2)個目のvsync から(M−1)ff
!l目のVsync  間での書き込みの開始点を設定
しており、通常(M−1)個目のVsyncの数H(H
:水平走査期間)前に設定されている0 立下り検出回路(81はこの立下vt−検出して検出信
号(f)i出力する。この検出信号(f)1’!ゲ−ト
回路(書き込み禁止手段N91i経て再生映像信号(N
)の書き込み制御回路(1」hへの−it弯込み指令信
号(h)となる^書き込み制御回路(IOに書き込み指
令信号(hl受けてビデオRAM(メモリー手段)(1
21Vc−iI*込み開始信号を発して、ピックアップ
+21から得られる再生映像信号(N11フイールド(
1画面)分をA/D変換回路[111にて8ピ、ントの
ディジタル値に変換しt信号k 3 f s C(fs
c:カラーサブキャリア周波数)のサンプリング周波数
でビデオRAM(13にて静止画像信号として記憶せし
めるn ビデオRAM(121からの読出しは、3fSCのサン
プリング周波数を有する読出しタイミング信号にて連続
的に繰り返し為される□但し、読出しタイばング信号ζ
書き込み開始信号とは独立したものであり、ま友、ビデ
オRAM(121は高速でアクセス可能であり、再生映
像信号の1フイ一ルド分を書き込んでいる途中で、同時
にビデオRAMn21からの読出しも可能である。読み
出され之静止画像信号ぼD/A変換回路(131にてL
l/Al/式れ、モニター(1シに映出される。
With this kick pulse (a), the R-8 flip-flop 15+, whose Q output is the reset input of the Vsync counter +61, issues a reset 1 signal (b).
The reset of Vsync (C) is released and the count of Vsync (C) starts □ When the vsync counter f61i (M -2) counts, its output is set to shift from L level to H level □ Kick pulse ta) After i birth, Vsy
When nc (C) is counted CM-2), Vsy
nc counter (6-count pulse (d) is emitted, and this count pulse (d) is R-8FF +71'i -
i = , 1, R-8FF171rzVsync
(C) The total delay circuit (8) delays the signal for a certain period of time (1) and resets it with a constant signal (C), and falls as the output i(e). Note that delay time (t) after i track jump, from CM-2)th vsync to (M-1)ff
! The writing start point is set between the l-th Vsync, and usually the number H (H
0 set before the horizontal scanning period) The falling detection circuit (81 detects this falling vt- and outputs the detection signal (f)i. This detection signal (f) 1'! gate circuit ( The reproduced video signal (N
)'s write control circuit (1'') becomes the -it inversion command signal (h) to the write control circuit (IO).
A start signal including 21Vc-iI* is issued, and the reproduced video signal obtained from the pickup +21 (N11 field (
The A/D conversion circuit [111] converts the t signal k3fsC(fs
Reading from the video RAM (121) is continuously and repeatedly performed using a read timing signal having a sampling frequency of 3 fSC. □However, the read tying signal ζ
It is independent of the write start signal, and the video RAM (121) can be accessed at high speed, and while one field of the playback video signal is being written, it is also possible to read from the video RAM n21 at the same time. The read still image signal is converted to L at the D/A conversion circuit (131).
l/Al/It is displayed on the monitor (1 screen).

次に検出信号(f)’i書き込み指令信号<h>とじて
通過制御するゲート回路(91の簡偶について説明する
Next, the gate circuit (91) which controls the passage of the detection signal (f)'i write command signal <h> will be explained.

ピックアップ(21から得られる再生映像信号(N)は
水平同期分離回路(161に入力されて、水平同期信号
< Hsync )のみが抽出され、位相比較回路(位
相比較手段)α7)にて基準信号発生回路!1&からの
基準信号と位相比較が為される。
The reproduced video signal (N) obtained from the pickup (21) is input to the horizontal synchronization separation circuit (161, where only the horizontal synchronization signal < Hsync) is extracted, and the phase comparison circuit (phase comparison means) α7) generates a reference signal. circuit! A phase comparison is made with the reference signal from 1&.

この位相比較により得られる両信号の位相差に相当する
位相誤差信号ζスピンドルモータサーボ回路(回転制御
手段)(19に供給され、これによりディスクIIIの
回転駆動全為すスピンドルモータ(図示省略]のサーボ
が為される。即ち、Hsyncが基準信号の位相に一致
する様に回転、vlI@が為嘔れる□尚、基準信号発生
回路(18)は固定発撮器と分周回路にて構成され、常
時正規の水平同期信号の周波数を有するパルス奮発する
n 位相誤差信号aロック検出回路■にも供給される。この
ロック検出回路c1gに位相誤差信号が所定のレベルの
範囲内にある場合、即ちHsyncが基準信号と位相合
致(位相ロック)状態であれば、Te5Cロ一ツク信号
(g)を発する□グー8回路+91はTBGロック信号
(g)がHレベルの時にのみ検出信号(f’)の通過を
許容し、Lレベルの時には通過は遮断されるり従って、
キックパルス(a)発生後のトラックジャンプ直後に再
生映像信号のHsync の不連続が発生している期間
でに、検出信号(f)は書き込み指令信号(h)として
書き込み制御回路111−に供給されず、従って再生映
像信号(N)のビデオflAM+121への書き込みが
禁止され、時間畑制御が正常なときにのみ書き込みが為
され、静止画像信号はHsyncが連続し之安定しt画
面となる□ 前述の実施例とは別に、シスコン1;引からのキックパ
ルス(a)i一定周期とせず、キックパルス(?L)発
生後、TBGロック信号(g+が出力されれば、直ちに
書き込みタイピング信号を出力し、書尊込みが終了すれ
ば、シスコン13+jり次のキックパルスを出力する様
な構成も可能である−1まt、通常再生から特殊再生に
移行する時は、先ずキックパルス発生前に書き込みを為
し、この書き込みが終了してからキックパルスを発する
様に構成されている。
A phase error signal ζ corresponding to the phase difference between the two signals obtained by this phase comparison is supplied to the spindle motor servo circuit (rotation control means) (19), thereby controlling the servo of the spindle motor (not shown) that completely drives the rotation of the disk III. That is, Hsync is rotated so that it matches the phase of the reference signal, and vlI@ is changed.In addition, the reference signal generation circuit (18) is composed of a fixed oscillator and a frequency dividing circuit, A phase error signal (a) which constantly generates pulses having the frequency of a regular horizontal synchronization signal is also supplied to the lock detection circuit (2).If the phase error signal is within a predetermined level range, the lock detection circuit (c1g) receives If the phase matches (phase lock) with the reference signal, the Te5C lock signal (g) is emitted. □The Goo 8 circuit +91 outputs the detection signal (f') only when the TBG lock signal (g) is at H level. Passage is allowed, and when it is at L level, passage is blocked.
Immediately after the track jump after the kick pulse (a) is generated, the detection signal (f) is supplied to the write control circuit 111- as a write command signal (h) during a period in which the Hsync discontinuity of the reproduced video signal is occurring. Therefore, writing of the reproduced video signal (N) to the video flAM+121 is prohibited, and writing is performed only when the time field control is normal, and the still image signal becomes stable with continuous Hsync and becomes the t screen □ As mentioned above. Separately from the embodiment shown in FIG. 1, the kick pulse (a) from the system controller 1; does not have a constant cycle, but after the kick pulse (?L) is generated, if the TBG lock signal (g+) is output, the write typing signal is immediately output. However, it is also possible to configure the system controller 13+j to output the next kick pulse once the writing is completed.However, when transitioning from normal playback to special playback, first write the kick pulse before the kick pulse is generated. The configuration is such that the kick pulse is emitted after this writing is completed.

尚、本実施例は高速再生について説明しtが、Mの値を
選択しジャンプするトラック数を選択することによりス
ロー等の特殊再生各可能となる。
In this embodiment, high-speed playback will be explained, and by selecting the value of t and M and the number of tracks to jump to, special playback such as slow speed playback becomes possible.

(ト)発明の効果 上述の如く本発明によれば、メモリーに静止画像信号全
記憶せしめ、CLVディスクの特殊再生に用いる場合に
、トラックジャンプ後にメモリーに書き込まれる再生映
像信号の水平同期信号の不連続による時間軸の乱れが防
止でき、安定【7之特殊再生画面が得られるり
(g) Effects of the Invention As described above, according to the present invention, when all still image signals are stored in a memory and used for special playback of a CLV disc, the horizontal synchronization signal of the reproduced video signal written to the memory after a track jump is not affected. Disturbance of the time axis due to continuity can be prevented, and a stable [7 special playback screen] can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は全て本発明に係り、第1図に回路ブロック図、第
2図ぼタイミングチャートである□Il+・・・ディス
ク、12」・・・ピックアップー+91・・・ゲート回
路(書き込み禁止手段)、口2・・・ビデオFtAM 
(メモリー手段)、鼎・・・位相比較回路(位相比較手
段)、(HJ・・・スピンドルモータサーボ回路(回転
制御手段)。
The drawings all relate to the present invention, and FIG. 1 is a circuit block diagram, and FIG. 2 is a timing chart. Mouth 2...Video FtAM
(memory means), Ding...phase comparison circuit (phase comparison means), (HJ...spindle motor servo circuit (rotation control means).

Claims (1)

【特許請求の範囲】[Claims] (1)線速度一定に映像信号が記録されたディスクと、
前記ディスクを走査し特殊再生時にトラックジャンプが
為されるピックアップと、 前記ピックアップにより得られる再生映像信号の一画面
分が静止画像信号として書き込まれるメモリー手段と、 前記再生映像信号中の水平同期信号と基準信号との位相
を比較する位相比較手段と、 前記位相が一致する様に前記ディスクの回転を制御する
回転制御手段と、 前記位相比較手段により前記水平同期信号と前記基準信
号との位相差が所定値を越える時に前記メモリー手段へ
の前記再生映像信号の書込みを禁止する書き込み禁止手
段 とから成るビデオディスクプレーヤ
(1) A disk on which a video signal is recorded at a constant linear velocity,
a pickup that scans the disk and makes track jumps during special playback; a memory means into which one screen of the reproduced video signal obtained by the pickup is written as a still image signal; and a horizontal synchronization signal in the reproduced video signal. a phase comparison means for comparing the phase with a reference signal; a rotation control means for controlling rotation of the disk so that the phases match; and a phase difference between the horizontal synchronization signal and the reference signal by the phase comparison means. a video disc player comprising write inhibiting means for inhibiting writing of the reproduced video signal to the memory means when a predetermined value is exceeded.
JP61248920A 1986-10-20 1986-10-20 Video disk player Withdrawn JPS63102575A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61248920A JPS63102575A (en) 1986-10-20 1986-10-20 Video disk player

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61248920A JPS63102575A (en) 1986-10-20 1986-10-20 Video disk player

Publications (1)

Publication Number Publication Date
JPS63102575A true JPS63102575A (en) 1988-05-07

Family

ID=17185384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61248920A Withdrawn JPS63102575A (en) 1986-10-20 1986-10-20 Video disk player

Country Status (1)

Country Link
JP (1) JPS63102575A (en)

Citations (6)

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Publication number Priority date Publication date Assignee Title
JPS60157383A (en) * 1984-01-27 1985-08-17 Victor Co Of Japan Ltd Video signal processing device
JPS6040171B2 (en) * 1978-10-20 1985-09-10 ハイドロ−ケベツク variable inductor
JPS61150477A (en) * 1984-12-25 1986-07-09 Toshiba Corp Video disk reproducer
JPS61232786A (en) * 1985-04-05 1986-10-17 Pioneer Electronic Corp Image reproducer
JPS62145982A (en) * 1985-12-20 1987-06-30 Sony Corp Video disc reproducing device
JPS6356082A (en) * 1986-08-27 1988-03-10 Hitachi Ltd Preproducing device for clv video disk

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6040171B2 (en) * 1978-10-20 1985-09-10 ハイドロ−ケベツク variable inductor
JPS60157383A (en) * 1984-01-27 1985-08-17 Victor Co Of Japan Ltd Video signal processing device
JPS61150477A (en) * 1984-12-25 1986-07-09 Toshiba Corp Video disk reproducer
JPS61232786A (en) * 1985-04-05 1986-10-17 Pioneer Electronic Corp Image reproducer
JPS62145982A (en) * 1985-12-20 1987-06-30 Sony Corp Video disc reproducing device
JPS6356082A (en) * 1986-08-27 1988-03-10 Hitachi Ltd Preproducing device for clv video disk

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