JP2783607B2 - Synchronous signal generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization signal generator that generates various timing signals synchronized with an input synchronization signal.

[Conventional technology]

Conventionally, a synchronization signal is recorded together with an information signal on a recording medium during recording, a synchronization signal recorded along with the information signal on the recording medium is reproduced during reproduction, and various timing signals are generated based on the reproduced synchronization signal. There is an information signal recording / reproducing apparatus that performs various processes on a reproduced information signal based on a timing signal obtained.

As an example of the information signal recording / reproducing apparatus as described above, a still image signal is converted into a vertical synchronizing signal (Vsync) and a horizontal synchronizing signal (H
There is a still video recording / reproducing apparatus which records and reproduces on a magnetic disk together with a composite synchronizing signal (Csync) constituted by sync.

FIG. 5 shows an example of the configuration of a synchronization signal generator (see FIG. 5 (a)) in the above-described still video recording / reproducing apparatus and a timing chart (see FIG. 5 (b)) showing its operation.

FIG. 5A shows a still video recording / reproducing apparatus.
FIG. 3 is a diagram showing a configuration of a synchronization signal generator for generating a window pulse (H _BLK ) for providing a horizontal blanking period in a reproduced still image signal.

In the still video recording / reproducing apparatus, Csync reproduced during reproduction (see FIG. 5B) is supplied to a reset terminal (RES) of the counter 100 in FIG. 5A.

The counter 100 is reset during the low level period of Csync supplied from the RES, and counts for a predetermined period (T _{2 of} FIG. 5B) from the rising edge of Csync (T _{0 in} FIG. 5B). And supplies the count data to the AND gates 101 and 102.

AND gate 101 detects whether the output count data of the counter 100 reaches the T ₀ of FIG. 5 (b) to T _1,
A gate that outputs a high-level signal when it reaches
AND gate 102 detects whether the output count data of the counter 100 reaches from T ₁ of the FIG. 5 (b) to T _2, when it reaches is a gate which outputs a high level signal.

The signal output from the AND gate 101 is supplied to the set terminal (S) of the SR flip-flop 103,
The signal output from the gate 102 is supplied to a reset terminal (R). As a result, a window pulse (H _BLK ) as shown in FIG. 4B is output from the output terminal (Q) of the SR flip-flop 103. In the still video recording / reproducing apparatus, a horizontal blanking period is provided in the still image signal reproduced based on the _HBLK formed as described above.

[Problems to be solved by the invention]

By the way, in the synchronous signal generator in the above-described still video recording / reproducing apparatus, since various synchronous signals are formed based on the synchronous signal reproduced from the porcelain disk, for example, a drop-out occurs in the synchronous signal reproduced during reproduction. Occurs, a part of the signal is lost, noise or the like is mixed in from the outside, the signal waveform is distorted, or the time axis of the reproduced synchronization signal fluctuates due to uneven rotation of the magnetic disk, etc. Various synchronization signals formed on the basis of the deteriorated synchronization signal also become inaccurate, and eventually, the reproduced still image signal processed based on the incorrect synchronization signal also deteriorates. .

SUMMARY OF THE INVENTION It is an object of the present invention to provide a synchronization signal generator capable of forming various accurate timing signals even when an input synchronization signal is deteriorated.

[Means for solving the problem]

A synchronization signal generator according to the present invention includes: a clock signal generator that generates a clock signal; a counter that counts clock signals generated by the clock signal generator and outputs a count result; A first timing signal generator for generating various timing signals, a synchronizing signal, and the input synchronizing signal and the first synchronizing signal.
A phase comparator compares the phase of a timing signal generated by a timing signal generator, and counts a phase comparator that controls a counting cycle in the counter according to the comparison result, and a timing signal generated by the first timing signal generator. And a second timing signal generator for generating a timing signal of a type different from the timing signal generated by the first timing signal generator in accordance with the counting result.

[Action]

According to the above configuration, it is possible to form various accurate timing signals even when the input synchronization signal is deteriorated.

〔Example〕

 Hereinafter, the present invention will be described using examples of the present invention.

FIG. 1 is a diagram showing, as an embodiment of the present invention, a schematic configuration of a synchronization signal generator in a still video recording / reproducing apparatus that handles a still image signal conforming to an NTSC television signal.

In FIG. 1, reference numeral 1 denotes an input terminal of a composite synchronizing signal (Csync) reproduced from a magnetic disk (not shown), and Csync (see FIG. 2) inputted from an input terminal 1 is a comparator 6, which will be described later, and a vertical synchronizing signal. It is supplied to the detection circuit 9.

On the other hand, a clock pulse having a color subcarrier frequency (3.58 MHz) is generated from the reference clock generator 2 and supplied to a clock pulse input terminal CK _H of a horizontal synchronization counter (H counter) 3.

The H counter 3 counts the number of clock pulses input from the clock input terminal CK _H and supplies the count value data (see FIG. 2) to the H decoder 4.

The H decoder 4 sets the levels of the output signals D _{0 to} D ₆ to high level or low level according to the value of the count value data supplied from the H counter 3, and supplies the output signals D _{0 to} D ₆ to the data selector 5.

Note that the H decoder 4 shown in FIG. 1 operates when the count value data supplied from the H counter 3 indicates "226-16 = 210".
When the output signal D0 is set to the high level and the count value data is "22
When 6-4 = 222 ", the output signal D1 is set to the high level. When the count value data indicates" 226-1 = 225 ",
The output signal D2 is set to the high level, and the count value data is “22”.
When 6 + 16 = 242 ", the output signal D3 is set to the high level, and when the count value data indicates" 226 + 4 = 230 ",
Set the output signal 4D to high level and set the count value data to "22
6 ", the output signal D5 is set to the high level. When the count value data indicates" 113 ", the output signal D6 is set to the high level. When the count value data indicates" 50 ", the output signal H is set.
_REF (see FIG. 2) is set to a high level. The data selector 5 outputs any one of the signals D0 to D6 supplied from the H decoder 4 in accordance with select signals S0 to S2 output from a controller 8 described later. The resetting of the H counter 3 by supplying it to the reset terminal _{RH of the same,} and the input terminal VK _{V of} a vertical synchronization counter (V counter) 11 to be described later.
Supplied to

On the other hand, the output signal H _REF of the H decoder 4 is
And it is supplied to a counter 7, the comparator 6 the H _REF
And the phase difference between Csync supplied from the input terminal 1 and the output signals C0 to C3 is set to a high level or a low level according to the phase difference, and supplied to the counter 7 and the controller 8.

That is, the comparator 6 is set to the high level output signal C1 in the case where the phase of the Csync is ahead H _REF, if the delay is set to low level.

The comparator 6 respectively the level of the output signal C0, C2, C3 in accordance with the amount of phase difference between the Csync and H _REF supplied s,
It is set to high level or low level,
The phase difference between the Csync and H _REF is in terms of the number of clock pulses output from the reference clock generator 2, in the case where 8 or more clock component to the output signal C0 to the high level, 4
If it is for 8 clocks, the output signal C2 is at a high level. If it is for 0 to 4 clocks, the output signal C3 is at a high level. The levels of these output signals C0 to C3 are held for one horizontal synchronization period. It is like.

The counter 7 is supplied with the output signal C0 of the comparator 6 and the H _REF output from the H decoder 4. When the output signal C0 of the comparator 6 is at a low level, the counter 7 is reset and at a high level. In the case of (1), the number of pseudo horizontal synchronizing pulses of H _REF supplied from the H decoder 4 is counted, and when the count value reaches “3”, a high-level output signal is supplied to the controller 8.

By the way, the Csync (see FIG. 3) inputted from the input terminal 1 is also supplied to the vertical synchronizing signal detecting circuit 9 as described above. The vertical synchronization blanking period (b in FIG. 3) is detected.

That is, as shown in FIG. 3, the vertical synchronization blanking period (b in FIG. 3) is performed in the horizontal synchronization blanking period (third
Since the period of the low level is longer than the period a) in the figure, the vertical synchronization signal detection circuit 9 counts the period in which the level of the supplied Csync is low, and the counted value is the horizontal synchronization blanking period (FIG. 3). If the period is longer than the period a), the output signal is also set to the high level and supplied to the delay circuit 10 at the subsequent stage.

The delay circuit 10 delays the output signal of the vertical synchronization signal detection circuit 9 by several H (H is a horizontal synchronization period), and
Counter) 11 is supplied to the reset terminal R _V of, V counter
Numeral 11 is reset while the signal supplied from the delay circuit 10 is at a high level.

By the way, an equalizing pulse is added to Csync input from the input terminal 1, and a timing signal of a different type from the other periods is set to H during the equalizing pulse period (c in FIG. 3) during Csync. Based on the counter value data of the counter 3 and the V counter 11, the vertical synchronization signal detection circuit 9 detects the vertical blanking period as described above and forms the Csync equalization pulse If the V counter 11 is reset during the operation, the continuity of the timing signal formed during the equalization pulse may be lost. Therefore, in this embodiment, the output signal of the vertical synchronizing signal detecting circuit 9 is several H
Due to the delay, the V counter 11 is reset at a timing sufficiently delayed from the equalizing pulse period of Csync.

The output signal of the data selector 5 is supplied to the clock pulse input terminal CK _V of the V counter 11 as described above.
The V counter 11 counts the number of times the high level signal output from the data selector 5 is supplied, and outputs count value data to the V decoder 12.

When the count value data supplied from the V counter 11 reaches the number of horizontal synchronization pulses (that is, 263) within one field period, the V decoder 12 outputs the pseudo vertical synchronization signal V _REF, and outputs the V counter 11. When the supplied count value data reaches a predetermined count value,
The output signal B0 is set to a high level and supplied to the controller 8.

By the way, in the still video recording / reproducing apparatus of this embodiment, the magnetic disk is rotated by a motor, and a still image signal for one field period is recorded on one of the concentric recording tracks formed on the magnetic disk. It is configured.

Also, the motor is controlled by a motor servo circuit or the like so as to rotate at a predetermined rotation speed.
Since rotation unevenness cannot be completely eliminated, the recording start position and the end position of the still image signal on the magnetic disk do not exactly match, and an unrecorded portion or an overwritten portion may occur.

In the above case, as shown by d in FIG. 3, the signal is separated from the still image signal reproduced from the magnetic disk.
Not gone 1H is the period of the horizontal synchronizing signal in the still image signal recording start position and the end position position corresponding to the switched point or when to quenching point of Csync, the phase difference between the Csync and H _REF in this part It gets bigger.

Therefore, in the V decoder 12 of this embodiment, when the count value data supplied from the V counter 11 reaches the count value corresponding to the vicinity of the switching point in Csync (a period of several H), the output signal B1 is set to a high level. And supplies it to the controller 8.

Hereinafter, the controller 8 in the embodiment shown in FIG.
The input / output operation of the signal will be described with reference to the operation flowchart of FIG.

In Figure 1, H _REF output from Csync and H decoder 4 that is input from the input terminal 1 is fed to a comparator 6, where the phase difference between two signals is detected, is detected from the comparator 6 Signal C0-
C3 is supplied to the counter 7 and the controller 8. (See Figure 4 step ST _1).

On the other hand, the V counter 11 counts the output signal of the data selector 5 and outputs count value data corresponding to the count value to the V decoder 12.
When the supplied count value data reaches a predetermined count value, the output signals B0 and B1 are set to a high level. When the V counter 11 counts "262", the output signal is output from the V decoder 12. B0 goes high, and the controller 8 sends S0: 1, S1: 1, S
A 2: 1 select signal is output, and the data selector 5 selectively outputs the output signal D6 output from the H decoder 4 when the H counter 3 counts "113", resets the H counter 3 and simultaneously outputs the V counter 11 Is counted up.

By the above operation, for example, when the composite synchronizing signal to be handled conforms to the NTSC television signal, the one-field period is "262.5H", and the H counter 3 is set to the normal 1H period (reference clock generation). H _REF output from the H decoder 4 is terminated at the end of one field period in order to reset it in a half period (i.e., 113 clocks) with respect to the number of clock pulses output from the decoder 2 in 226 clocks. Even in the part, it will be possible to synchronize with Csync.

When the V counter 11 counts a count value near the switching point of Csync, the V decoder 11
12 B1 becomes high level output from the controller 8 is much to the data selector 5 irrespective of the signal C0~C3 corresponding to a phase difference between the Csync and H _REF output from the comparator 6 S0: 1, S1 : 1, S2: 0 and S0: 1, S1: 0, S2: 1 are alternately output every 1H period.
When the counter 3 counts "225" or "226", the output signals D2 and D5 output from the H decoder 4 are alternately selected and output every 1H period, and the H counter 3 is reset and the V counter 11 is counted up. causes (see Figure 4 step ST ₅ ~ST _7).

By the above operation, H _REF output from the H decoder 4 can be synchronized with Csync at a position corresponding to the switching point on the magnetic disk.

Then, the controller 8 in the case of BO and B1 are both low level is outputted from the V decoder 12, (or delayed or fast) direction of the phase shift of the Csync and H _REF from the comparator 6 and in accordance with the amount of phase difference output Select signals S0 to S2 corresponding to C0 to C3 to be output.

First, the comparator 6, if it in terms of the number of clock pulses to the phase difference amount between Csync and H _REF is outputted from the reference clock generator 2 is 0-4 clock component is detected C0, C2 Is low level, C3 is high level, and when the phase of Csync is ahead of H _REF , C
1 becomes high level, the controller 8 outputs select signals S0: 0, S1: 1, S2: 0 to the data selector 5,
Data selector 5 selects and outputs an output signal D2 output from the H decoder 4 when counting is H counter 3 "225", also, C1 becomes a low level when the phase of Csync is delayed from H _REF The controller 8 outputs S0: 1, S1: 0, S2: 1 select signals to the data selector 5, and the data selector 5 outputs the data from the H decoder 4 when the H counter 3 counts "226". select an output signal D5, the V counter 11 is counted up-as well as resetting the H counter 3 (Fig. 4 step ST ₈ ~ST
₁₄ ).

The H counter 3 is driven by the signal D2 or D5 output from the data selector 5 by the above-described operation to reset the H counter 3 for one clock with respect to a normal reset period (226 clocks converted into the number of clock pulses output from the reference clock generator 2). Since the reset is performed at a shorter timing, the H _REF output from the H decoder 4 can be brought closer to the phase of Csync and synchronized.

Then, if it is 4 to 8 clock component in terms of the number of clock pulses to the phase difference amount between Csync and H _REF is outputted from the reference clock generator 2 in the comparator 6 is detected C0 is low , C2 goes high, further phase of Csync is C1 becomes a high level when the leads the H _REF, the controller 8 to the data selector 5 S0: 1, S1: 0 , S2: 0 select signal And the data selector 5 outputs H when the H counter 3 counts “222”.
Selects and outputs the output signal D1 output from the decoder,
When the phase of Csync is later than H _REF , C1 becomes low level, the controller 8 outputs select signals S0: 0, S1: 0, S2: 1 to the data selector 5, and the data selector 5 H counter 3 selects and outputs the output signal D4 outputted from the H decoder 4 when the counts "230", the V counter 11 is counted up-as well as resetting the H counter 3 (Fig. 4 step ST _8, ST ₉ , see ST ₁₅ ~ST _19).

By the above-described operation, the H counter 3 is reset by the signal D1 or D4 output from the data selector 5 for the normal reset period (226 clocks converted into the number of clock pulses output from the reference clock generator 2). In order to reset at short or long timing by clock,
The H _REF output from the H decoder 4 can be brought closer to the phase of Csync and synchronized.

Further C0 when a phase difference amount that is the reference clock generator 2 8 clock or partial in terms of the number of clock pulses output from is detected between Csync and H _REF in the comparator 6 becomes a high level. The counter 7 is in a reset state when C0 supplied from the comparator 6 is at a low level, and is in an operating state when C0 is at a high level. The counter 7 counts the number of _HREF pulses output from the H decoder 4 and the count value is "3". The low level signal is output to the controller 8 when the signal reaches "3".

In the present embodiment, Csync and H _REF
If it is detected that the phase difference amount from the clock pulse output from the reference clock generator 2 is equal to or more than 8 clocks, noise may be mixed into Csync, or dropout may occur. The counter 7 monitors whether or not such an abnormal state occurs continuously for the 3H period.

As described above, in the counter 7 detecting the continuous period of the abnormal state, while the continuous period of the abnormal state has not reached the 3H period (that is, the signal supplied from the counter 7 to the controller 8 is low). level during) the controller 8 to the data selector 5 regardless of the direction of the phase difference between the Csync and _{H REF S0: 1, S1:} 0, S2: outputs one of the select signals, the data selector 5 H Output signal output from H decoder 4 when counter 3 counts "226"
D5 is selected and output, the counter 3 is reset, and the V counter 11 is counted up.

Incidentally, the above-described operation is the phase difference of the Csync and H _REF in or comparator 6 count value of the counter 7 reaches "3" is less than 8 clock component, the output signal
This is repeated until C0 becomes low level.

When the continuous period of the abnormal state in the counter 7 has reached the 3H periods (i.e., when a signal is supplied to the controller 8 from the counter 7 reaches a high level), the phase of the Csync is ahead H _REF C1 becomes high level, the controller 8 outputs selector signals S0: 0, S1: 0, S2: 0 to the data selector 5, and the H counter 3 counts "210" in the data selector 5. H output signal DO selects output outputted from the decoder, also CI becomes low level when the phase of Csync is delayed from H _REF when, the controller 8 to the data selector 5 S0: 1, S1 : 1, S2: 0 are output, and the data selector 5 selectively outputs the output signal D3 output from the H decoder 4 when the H counter 3 counts "242", and resets the H counter 3 and V Counter 11 to count the UP. (Fig. 4 step ST _8, ST
_{20 to} ST ₂₇ ).

Even if Csync becomes abnormal due to the above-described operation, the H counter 3 receives the signal D5 output from the data selector 5 so that the normal reset period (226 clocks converted into the number of clock pulses output from the reference clock generator 2) is obtained. ), The self-running state is established, and if the abnormal state continues for 3H, the H counter 3 is reset by the signal D0 or D3 output from the data selector 5 in the normal reset cycle (reference clock generator). in terms of the number of clock pulses output from 2 226 clock minute) for resetting in 16 clock minute shorter or longer time with respect to, Csync the H _REF output from the H decoder 4
And it can be synchronized.

Incidentally, the operation described above in the data selector 5, after one signal among D0~D6 outputted from H decoder 4 is output, returns to step ST ₁ of FIG. 4 again, in the comparator 6 phase comparison Csync and H _REF is performed, so that the above-described operation is repeated.

Then, it is generated by the H decoder 4 as described above.
H _REF is supplied to the monostable multivibrator 13, V _REF generated from V decoder 12 is supplied to the monostable multivibrator 14, H _REF supplied in the monostable multivibrator 12 as a trigger pulse V _REF Generating a horizontal blanking pulse (H _BLK ) and a vertical blanking pulse (V _BLK ) each having a preset pulse width,
It is used in a still video recording / reproducing apparatus for providing a water surface or vertical blanking period to a still image signal reproduced from a magnetic disk.

In this embodiment, the synchronizing signal generator in the still video recording / reproducing apparatus that handles a still image signal based on the NTSC television signal has been described as an example. However, the present invention is not limited to this, and the PAL / SECAM In the case of a device conforming to the television signal of the system, the same configuration can be realized. In this case, in order to correspond to each system, the length of one horizontal synchronization period and the length of one vertical synchronization period, that is, H Counter 3,
The timing for resetting the V counter 11 may be changed.

Further, in this embodiment, a case has been described in which the synchronization signal generator generates horizontal and vertical blanking pulses synchronized with the composite synchronization signal Csync included in the reproduced still image signal. The present invention is not limited to this, and can cope with a case where other various timing signals such as a clamp pulse are formed. In this case, the H decoder 4 and the V decoder 12 decode the count value data output from the H counter 3 and the V counter 11. May be set so that the desired timing is obtained. Particularly, a horizontal synchronizing signal and a vertical synchronizing signal formed by decoding count value data output from the H counter 3 and the V counter 11 instead of the composite synchronizing signal Csync separated from the still image signal reproduced from the magnetic disk. , A new composite synchronizing signal may be generated.

The signal outputted from the comparator 6 in accordance with the amount of phase difference between the Csync and H _REF in this example represents the phase difference amount C0, C2, C3 3 stages of the signal, but this Not limited to this, the number of stages may be increased or decreased.

In the present embodiment, a low-level period during Csync included in a still image signal reproduced from a magnetic disk, that is, a vertical blanking period (b in FIG. 3)
The V counter 11 is reset when a low level is detected for a predetermined period or more. However, a dropout occurs in Csync included in a still image signal reproduced from a magnetic disk, and this portion is removed. It is necessary to prevent erroneous detection and resetting of the V counter 11 by mistake.

The magnetic disk used in the still video recording / reproducing apparatus of this embodiment has a PG on the circumference of the core of the magnetic disk.
A still video recording / reproducing device is provided with a magnetic medium called a pin. When recording a still image signal on a magnetic disk, the magnetic disk is rotated, and the position of the PG pin of the rotating magnetic disk is detected by a coil. The start and end of recording of the still image signal on the magnetic disk are performed at the detection position of the PG pin.

Therefore, when the PG pin of the magnetic disk is detected, the reset of the V counter 11 as described above generates a window pulse or the like, detects a low-level period only during a period specified by the window pulse, and in other periods, By not detecting the low level period, it is possible to prevent the V counter 11 from being reset by mistake.

As described above, in the synchronous signal generator of this embodiment, the Csync separated from the still image signal reproduced from the magnetic disk is formed by a counter or the like based on the reference clock generated by the reference clock generator. A phase is compared with the synchronization signal, the reset timing of the counter is changed according to the phase difference, and the period of the synchronization signal output from the counter is changed so that a desired reproduction timing signal can be generated. As a result, a reproduction timing signal that follows a change in Csync included in the still image signal reproduced from the magnetic disk can be obtained.

Even when the Csync changes, the phase of the reproduction timing signal is not instantaneously corrected, but is corrected by a predetermined amount, so that the reproduction timing signal is stable without being disturbed by disturbance such as noise. You will be able to get a signal.

Furthermore, since the circuit configuration is digitalized as shown in this embodiment, no adjustment or the like is required, and stable performance can be obtained even with environmental changes such as temperature and humidity. Since it is also small-scale, it can be easily integrated into an IC, and the mounting area for the device, the number of components, and the like can be reduced.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide a synchronization signal generator that can form accurate various timing signals even when an input synchronization signal is deteriorated. Become.

[Brief description of the drawings]

FIG. 1 is a diagram showing, as an embodiment of the present invention, a schematic configuration of a synchronization signal generator in a still video recording / reproducing apparatus which handles a still image signal conforming to an NTSC television signal. FIG. 2 and FIG. 3 are timing charts showing signal waveforms of various parts of the synchronization signal generator shown in FIG. FIG. 4 is an operation flowchart for explaining the operation of the synchronization signal generator shown in FIG. FIG. 5 is a diagram showing an example of the configuration of a synchronizing signal generator in the still video recording / reproducing apparatus (FIG. 5A) and a timing chart showing the operation thereof (FIG. 5B). 1 Composite sync signal input terminal 2 Reference clock generator 3 Horizontal sync counter 4 H decoder 5 Data selector 6 Comparator 7 Counter 8 Controller 9 Vertical sync signal detection Circuit 10 Delay circuit 11 Vertical synchronization counter 12 V decoder 13, 14 Mono multivibrator

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-70556 (JP, A) JP-A-1-320870 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N 5/91-5/956 H04N 5/10

Claims (1)

(57) [Claims] A clock signal generator for generating a clock signal; a counter for counting clock signals generated by the clock signal generator and outputting a count result; and various timing signals according to the count result in the counter. A first timing signal generator that generates the following. A synchronization signal is input, and the input synchronization signal is compared in phase with a timing signal generated by the first timing signal generator. A phase comparator for controlling a counting cycle, and counting a timing signal generated by the first timing signal generator, and a different type of timing signal from the first timing signal generator according to the counting result. A second timing signal generator for generating a timing signal.