JP2728951B2 - Image signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides various types of timing signals synchronized in phase with a composite synchronization signal added to an input image signal.
The present invention relates to an image signal processing device that processes the input image signal.

[Conventional technology]

Conventionally, a composite synchronizing signal is recorded together with an image signal on a recording medium during recording, a composite synchronizing signal recorded together with an image signal on a recording medium is reproduced during reproduction, and various timing signals are generated based on the reproduced composite synchronizing signal. There is an image signal recording / reproducing apparatus that performs various processes on a reproduced image signal based on a generated timing signal.

As an example of the image signal recording and reproducing apparatus as described above, a still image signal is converted into a vertical synchronizing signal (Vsync) and a vertical synchronizing signal (Hsy).
nc), there is a still video recording / reproducing apparatus which records and reproduces on a magnetic disk together with a composite synchronizing signal (Csync) constituted by the same.

The still video recording / reproducing device has a 3600 magnetic disk.
[Rpm], an image signal for one field per track is recorded on a plurality of tracks concentrically formed on the magnetic disk, and an image for one field recorded in this manner is recorded. The still image signal is obtained by repeatedly reproducing the signal.

In addition, when reproducing a still image signal as described above, in order to correspond to the scanning method (interlace method) of the television signal, an image signal for one field is divided into 1/2 horizontal synchronizing period (every one field period). 1 / 2H)
A so-called skew compensation is performed in which a signal obtained by delaying an image signal for one field reproduced from a magnetic disk by 1 / 2H and a signal not delayed are alternately switched and output every one field period.

In the above skew compensation, the timing for switching between a signal obtained by delaying the image signal for one field reproduced from the magnetic disk by 1 / 2H and a signal not delayed is provided on the circumference of the core of the magnetic disk during reproduction. By detecting the position of the magnetic piece (referred to as a PG pin) by a coil called a PG coil, a PG signal corresponding to the rotation cycle of the magnetic disk is generated, and a change point of the PG signal, that is, a PG pin is detected. It can be switched at the timing.

The vertical synchronizing signal added to the image signal recorded on each track on the magnetic disk is recorded so as to be shifted 7H ± 2H in the circumferential direction from the position where the PG pin is provided. I have.

[Problems to be solved by the invention]

However, in the conventional case as described above, the recording start point of the image signal recorded on the magnetic disk and the horizontal synchronizing signal obtained from the image signal reproduced from the magnetic disk always maintain a fixed phase relationship. The recording start point of the image signal for each magnetic disk to be reproduced, and the switching point between the signal delayed by 1 / 2H and the signal not delayed by 1 / 2H of the image signal reproduced from the magnetic disk in the skew compensation, that is, the position of the PG pin. When the position of the PG pin is switched between a signal obtained by delaying the image signal reproduced from the magnetic disk by 1 / 2H and a signal not delayed at the position of the PG pin for skew compensation, an image signal recorded on the magnetic disk The phase between the recording start point and the horizontal synchronizing signal obtained from the image signal reproduced from the magnetic disk differs for each magnetic disk.

FIG. 6 is a time chart showing a waveform of a synchronizing signal added to an image signal reproduced from a magnetic disk in order to explain the above situation.

In FIG. 6, (a) is a diagram continuously showing a synchronizing signal added to the image signal reproduced from the magnetic disk, and point A in the figure indicates a recording start point. (B) is a signal obtained by delaying the signal shown in (a) by 1 / 2H.

The skew compensation is performed by switching the signals (a) and (b) each time the magnetic disk makes one rotation.
(C) is a waveform when switching from (a) to (b), and (d) is a waveform when switching from (b) to (a).

When skew compensation is performed as shown in FIGS. 6 (c) and 6 (d), extra pulses are generated at points B and C in the figure, and in this portion, the continuity of the horizontal synchronization signal cannot be maintained conventionally. Had been lost.

Further, in the conventional apparatus, when a track to be reproduced is moved from an unrecorded track to a recorded track, a track in which an image signal corresponding to an odd field is recorded and a track in which an image signal corresponding to an even field is recorded are recorded. When the track to be reproduced is moved to (or vice versa), a discontinuity of the horizontal synchronizing signal occurs in the reproduced still image signal. For example, when the reproduced still image signal is supplied to an external device such as a monitor device. The external device operates according to the synchronization signal added to the supplied still image signal. However, since the added horizontal synchronization signal is discontinuous, the screen on which the supplied still image is projected is disturbed. Was likely to occur.

The present invention eliminates the conventional disadvantages as described above, and can maintain the continuity of the horizontal synchronization signal even after the skew compensation processing, and further, when an image signal is input from the reproduction unit,
It is an object of the present invention to provide an image signal processing device capable of preventing the phase of a composite synchronizing signal from changing rapidly even when a reproduction track is switched in the reproduction unit.

[Means for solving the problem]

An image signal processing device according to the present invention is a device for inputting an image signal and processing the input image signal, wherein the first composite synchronizing signal added to the image signal from the input image signal is processed. Composite synchronizing signal separating means for separating, composite synchronizing signal forming means for forming a second composite synchronizing signal phase-synchronized with the first composite synchronizing signal separated by the composite synchronizing signal separating means, and the input image A muting means for muting the signal; and a response speed of the phase synchronization control of the second composite synchronization signal with respect to the first composite synchronization signal in the composite synchronization signal forming means, wherein the response speed is at least one during the muting operation by the muting means. And a response speed control unit that changes between a period during which the muting operation is not performed and a period during which the muting operation is not performed.

(Operation)

With the above-described configuration, even after the skew compensation processing on the input image signal, it is possible to maintain the continuity of the horizontal synchronization signal, and further, when the image signal is input from the reproduction unit, Even when the reproduction track is switched, the phase of the composite synchronizing signal can be prevented from suddenly changing.

〔Example〕

 Hereinafter, the present invention will be described using examples of the present invention.

FIG. 1 is a diagram showing, as an embodiment of the present invention, a schematic configuration of a still video reproducing apparatus for repeatedly reproducing an image signal from a magnetic disk on which an image signal conforming to an NTSC television signal is recorded. It is.

In FIG. 1, reference numeral 1 denotes a magnetic disk on which 50 recording tracks are formed concentrically, and an image signal for one field is recorded on each recording track, and 2 denotes an image signal recorded on each recording track. 3 is a motor for rotating the magnetic disk 1 at 3600 [rpm], 4 is a motor servo circuit for rotating the motor 3 at a constant speed of 3600 [rpm], and 5 is a motor servo circuit. A head moving mechanism 6 for moving the magnetic head 2 between recording tracks formed on the magnetic disk 1; a reproducing amplifier 6 for amplifying and outputting a signal reproduced from the magnetic disk 1 by the magnetic head 2; A demodulation circuit 8 for demodulating the reproduction signal amplified by the reproduction amplifier 6 and restoring an image signal;
Is a 1 / 2H delay circuit for delaying the image signal demodulated by the demodulation circuit 7 by 1 / 2H, and SW1 is an image signal output from the demodulation circuit 7 and an image delayed by 1 / 2H by the 1 / 2H delay circuit 8. A skew compensation switch for alternately selecting and outputting a signal every one field period, a switching circuit 9 controlled by a timing signal generator 14 described later, and a muting circuit for muting an image signal output from the SW1, and a muting circuit 10. When an image signal is input from the input circuit 9, the composite synchronizing signal output from the timing signal generator 14 described later is replaced with a composite synchronizing signal added to the input image signal, and the image signal is output from the muting circuit 9. If not input, the timing signal generator 14 described later
A synchronizing signal adding circuit for outputting only a composite synchronizing signal outputted from the reproducing amplifier 6; an envelope detecting circuit 11 for performing envelope detection on the reproduced signal amplified by the reproducing amplifier 6 and outputting the detected signal;
By comparing the level of the detection signal output from 11 with a preset reference level, it is determined whether the track on the magnetic disk 1 traced by the magnetic head 2 is an unrecorded track or a recorded track. An unrecorded track discrimination circuit that outputs a discrimination signal corresponding to the discrimination result to a system controller 15 described later, 13 is a synchronization signal separation circuit that separates and outputs a composite synchronization signal from the signal output from the SW1, and 14 is a system described below. A timing signal generator that generates a composite synchronization signal separated by the synchronization signal separation circuit 13 according to an instruction from the control 15 and various timing signals corresponding to a PG signal supplied from a waveform shaping circuit 17 described later. The discrimination signal output from the recording track discrimination circuit 12 is input, and the motor servo circuit 4, the head moving mechanism 5, the timing signal A system controller for controlling the operation of the generator 14, 16 is a magnetic piece (PG pin) provided on the circumference of the core of the magnetic disk 1, and 17 is a PG for detecting the rotation phase of the magnetic disk 1. A PG coil 18 for generating a pulse every time the pin 16 crosses is a waveform shaping circuit for shaping the waveform of the pulse signal output from the PG coil 17 and outputting it as a PG signal corresponding to the rotation phase of the magnetic disk 1.

Hereinafter, the operation of the apparatus of the present embodiment shown in FIG. 1 will be described.

In FIG. 1, when a power switch (not shown) is turned on and power is supplied to the apparatus from a power supply unit (not shown), the system controller 15
(The signal output from the signal line b is set to a high level), the timing signal generator 14 operates the muting circuit 9, and mutes the signal output from SW1. At this time, the timing signal generator 14 is in a free-running state, the generated composite synchronization signal is supplied to the synchronization signal adding circuit 10, and only the composite synchronization signal is output from the output terminal at a predetermined level.

Also, the system controller 15 controls the motor servo circuit 4
And the motor servo circuit 4 drives the motor 3 to rotate the magnetic disk 1 at a constant speed of 3600 [rpm].

On the other hand, the reproduction signal output from the magnetic head 2 is amplified by the reproduction amplifier 6 and supplied to the envelope detection circuit 11. The envelope detection circuit 11 envelope-detects the reproduced signal amplified and supplied by the reproduction amplifier 6 and detects the level of the detected signal in an unrecorded track discrimination circuit 12.
Is compared with a preset reference level, when the level of the detection signal is higher than the reference level, the magnetic head 2 traces the magnetic disk 1
It is determined that the upper track is a recorded track, and when the level of the detection signal is smaller than the reference level, it is determined that the track on the magnetic disk 1 traced by the magnetic head 2 is an unrecorded track. The determination signal corresponding to the determination result is supplied to the system controller 15.

After the system controller 15 has operated the motor servo circuit 4 for a sufficient time for the magnetic disk 1 to start rotating at a constant speed, the system controller 15 responds to the discrimination signal supplied from the unrecorded track discriminating circuit 12 to determine whether the magnetic disc 1 has been turned on. Head 2
When it is detected that the track on the magnetic disk 1 that is being traced is a recorded track, the image signal demodulated and output by the demodulation circuit 7 is output by the 1 / 2H delay circuit 8 to 1 /
The signal delayed by 2H and the signal not delayed are alternately switched by SW1 every one field period to perform skew compensation, and then output from SW1. The switching timing of SW1 in the skew compensation is based on the rotating magnetic disk 1.
Each time the PG pin 16 crosses the PG col 17, the pulse signal output from the PG coil 17 is switched at the rising timing of the pulse of the PG signal formed by shaping the waveform in the waveform shaping circuit 18.

Since the start position of the vertical synchronizing signal of the image signal recorded on the magnetic disk 1 is determined to be 7H ± 2H after the rising timing of the pulse of the PG signal, the synchronizing signal separating circuit 13 is used based on the reproduced image signal. Is supplied to the timing signal generator 14, and the timing signal generator 14 calculates the number of horizontal synchronization pulses from the start point of the vertical synchronization signal of the composite synchronization signal supplied from the synchronization signal separation circuit 13. By counting, a signal having the same timing as the rising timing of the pulse of the PG signal can be formed, and the switching of SW1 in the skew compensation may be performed based on the timing signal thus formed.

The system controller 15 also determines the magnetic head 2 based on the discrimination signal supplied from the unrecorded track discrimination circuit 12.
Indicates that the track on the magnetic disk 1 that is being traced is a recorded track, cancels the muting operation in the muting circuit 9;
If it indicates that the track is unrecorded, the muting operation is continued.

The signal output from the muting circuit 9 is input to a synchronizing signal adding circuit 10 which adds a composite synchronizing signal generated by the timing signal generator 14 to the signal supplied from the muting circuit 9. Output. That is, when the muting circuit 9 is operating, only the composite synchronizing signal generated by the timing signal generator 14 is output, and when the muting circuit 9 is not operating, the muting circuit 9 is output.
The composite synchronizing signal added to the output image signal and the composite synchronizing signal generated by the timing signal generator 14 are converted and output.

Hereinafter, the operation of the timing signal generator 14 shown in FIG. 1 will be described.

FIG. 2 is a circuit diagram showing a part of the configuration of the timing signal generator 14 of FIG. 1. In FIG. 2, reference numerals 19, 20, and 21 denote D flip-flops, and reference numeral 22 denotes an OR gate.

FIG. 3 is a timing chart showing signal waveforms of signal lines indicated by a to e in FIGS. 1 and 2.

In FIG. 3, a) shows the waveform of the PG signal output from the waveform shaping circuit 18 shown in FIG. 1, and the rising portion of the waveform has the PG pin 16 provided on the magnetic disk 1 connected to the PG coil 17.
The timing of crossing is shown.

FIG. 3B shows the waveform of a signal supplied from the system controller 15 to the timing signal generator 14 in accordance with the determination result indicated by the determination signal output from the unrecorded track determination circuit 12 in FIG. When the track on the magnetic disk 1 traced by the head 2 is a recorded track, the level is low, and when the track is an unrecorded track, the level is high. The D flip-flop shown in FIG.
19 latches the signal b at the rising timing of the signal a and outputs the signal shown in FIG. 3 e). The signal e is further latched by the D flip-flop 20 at the rising timing of the signal a, and the signal e is supplied. The OR gate 22 outputs a signal shown in FIG. 3 (c). That is, the signal c is a signal obtained by latching the signal b at the rising timing of the signal a. However, when the signal b switches from the low level to the high level, the signal c also becomes low at the first rising timing of the signal a. When the signal b switches from the high level to the low level, the signal c switches from the high level to the low level at the second rising timing of the signal a. by the way,
The signal c performs the muting operation supplied from the timing signal generator 14 of FIG. 1 to the muting circuit 9 and cancels the muting operation when it is at a low level.

The D flip-flop 21 shown in FIG. 2 outputs a signal d whose polarity is inverted at the rising timing of the signal a.
Controls the switching timing of SW1 in FIG. That is, SW1 in FIG. 1 is connected to the A terminal in the figure when the signal d is at a high level, and to the B terminal in the figure when the signal d is at a low level.

Hereinafter, the operation of generating the composite synchronization signal in the timing signal generator 14 shown in FIG. 1 will be described.

FIG. 4 is a diagram showing a configuration of a composite synchronizing signal generator in the timing signal generator 14 shown in FIG.

The composite synchronizing signal generator shown in FIG. 4 receives the composite synchronizing signal separated from the image signal reproduced from the magnetic disk 1 in FIG. 1, and obtains a new composite synchronizing signal phase-synchronized with the inputted composite synchronizing signal. A signal is generated, and the tracking speed for phase synchronization can be controlled by an external instruction.

In FIG. 4, reference numeral 101 denotes an input terminal of a composite synchronizing signal (Csync) which is separated from the image signal reproduced from the magnetic disk 1 shown in FIG. The Csync (see FIG. 5) is supplied to a comparator 106 and a vertical synchronizing signal detection circuit 108, which will be described later.

On the other hand, from the reference clock generator 102 clock pulse of the color sub-wire carrier rear frequency (3.57945MHz) is generated and supplied to the clock pulse input terminal CK _H of the horizontal sync counter (H counter) 103.

The H counter 103 counts the number of clock pulses input from the clock input terminal CK _H and supplies the count value data (see FIG. 2) to the H decoder 104.

The H decoder 104 sets the levels of the output signals D0 to D6 to a high level or a low level, respectively, according to the value of the count value data supplied from the H counter 103, and
Supply 5

When the count value data supplied from the H counter 103 indicates "227-3 = 244", the H decoder 104 in FIG. 4 sets the output signal D0 to a high level, and sets the count value data to "227-2 = 244". 225 ", when the output signal D1 is at high level, when the count value data indicates" 227-1 = 226 ", when the output signal D2 is at high level, and when the count value data indicates" 227 ". , When the output signal D3 is set to the high level and the count value data indicates “227 + 1 = 228”, the output signal D3
4 is set to the high level, and the count value data is “227 + 2 = 22”.
When "9" is indicated, the output signal D5 is set to the high level. When the count value data indicates "227 + 3 = 230", the output signal D6 is set to the high level. When the count value data indicates "16", the output is performed. The signal H _REF (see FIG. 5) is set to a high level.

The data selector 105 responds to select signals S0 to S2 output from a controller 107 described later,
By outputting any one of the signals D0 to D6 supplied from 104 and supplying it to a reset terminal _RH of the H counter 103, the H counter 103 is reset and a vertical counter (V counter) 109 described later. Is supplied to the input terminal CKv.

On the other hand, the output signal H _REF of the H decoder 104 is
06 and is supplied to the composite synchronizing signal generator 11 to be described later, the comparator 106 detects the phase difference between the Csync being supplied from the input terminal 101 and the H _REF, the output signal C0, C1 in accordance with the phase difference The data is output to the controller 107. That is, the output signal C0 to the high level when the Csync matches or is progressing phase than H _REF, delay and a low level when are, also, data is output corresponding to the phase difference amount between Csync and H _REF The signal is output as the signal C1. In addition, the comparator 106 includes
Is used to detect the phase difference between the horizontal synchronizing signal and said H _REF in closest phase and H _REF, the first 6 (B in the figure, C) the horizontal sync pulse shown in Fig or vertical synchronization period of the equalizing pulses always it is configured so as to detect a phase difference between the horizontal sync signal and the H _REF of Csync not affect.

Incidentally, the Csync input from the input terminal 101 is also supplied to the vertical synchronization signal detection circuit 108 as described above, and the vertical synchronization signal detection circuit 108 detects the vertical synchronization signal in the supplied composite synchronization signal. , And is supplied to a reset terminal Rv of a vertical synchronization counter (V counter) 109 to reset the V counter 109.

The output signal of the data selector is supplied to the clock pulse input terminal CKv of the V counter 109 as described above. The V counter 109 counts the number of times of supplying the high level signal output from the data selector 105, and The value data is output to V decoder 110.

When the count value data supplied from the V counter 109 reaches the number of horizontal synchronization pulses (that is, 263) within one field period, the V decoder 110 outputs a pseudo vertical synchronization signal V _REF and the composite synchronization signal generator 111 To supply.

The composite synchronizing signal generator 111 forms a composite synchronizing signal Csync using the H _REF output from the H decoder 104 and the V _REF output from the V decoder 110, and outputs the composite synchronizing signal Csync from the output terminal 112. It is supplied to the additional circuit 10.

Hereinafter, the controller 10 in the embodiment shown in FIG.
The operation of signal 7 will be described.

First, the comparator 106, Csync supplied from the input terminal 101 will be described the case where is progressing phase than H _REF output from the H decoder 104. Here, it is assumed that the phase of Csync is 6 clocks ahead of H _REF in terms of the number of clock pulses output from the reference clock generator 102 in FIG.

Then, in the above case, the signal C0 output from the comparator 106 to the controller 107 becomes high level,
Also, the signal C1 becomes data representing “6” and the controller
107 generates a select signal S0, S1, S2 so as to reduce the phase difference between the Csync and H _REF, and controls the data selector 105.

That is, the controller 107 supplies select signals of S0: 0, S1: 0, S2: 0 to the data selector 105, and the data selector 105 outputs an output from the H decoder 104 when the H counter 103 counts “224”. Selects and outputs signal D0 and outputs H
The counter 103 is reset and the V counter 109 is counted up. Therefore, the H counter 103 is reset at a timing three clocks earlier than the previous reset timing, and H _REF is output from the H decoder 104 at a timing three clocks earlier than the previous reset timing, and Csync and H _REF are output. Is smaller by 3 clocks.

Then, data representing the amount of phase difference between the Csync and H _REF is 3 clock component becomes small as described above, the signal C0 output from the comparator 106 to the controller 107 remains high but the signal C1 is "3" And controller 10
7 outputs the select signals of S0: 0, S1: 0, S2: 0 to the data selector 105.
To the H counter 1
When 03 counts "224", the output signal D0 output from the H decoder 104 is selectively output, and the H counter 103 is reset and the V counter 109 is counted up. Then, the H counter 103 resets again at a timing three clocks earlier than the previous reset timing, and the H decoder 104 outputs H _{REF at a} timing three clocks earlier than the previous reset timing.
_The amount of phase difference from _REF becomes zero.

Next, the signal C0 output from the comparator 106 to the controller 107 remains at the high level, but the signal C1 is “0”.
And the controller 107 determines that S0: 1, S1: 0, S
By outputting the 2: 0 select signal to the data selector 105, the data selector 105 outputs the output signal D output from the H decoder 104 when the H counter 103 counts "227".
3 is selected and output, the H counter 103 is reset, and
The counter 109 is counted up. Therefore, the H counter 103 is reset at the same timing as the previous reset timing, and H _REF is output from the H decoder 104 at the same timing as the previous reset timing.
_The amount of phase difference from _REF is held at zero, and at this time, H _REF output from the H decoder 104 and V decoder 110
The Csync formed in the composite synchronizing signal generator 111 of FIG. 4 by using the V _REF output from the synchronizing signal generator 111 of FIG. 4 is separated by the synchronizing signal separating circuit 13 of FIG. The state is the same as the phase of Csync supplied to 106.

Then, in the comparator 106, Csync supplied from the input terminal 101 is described a case where the phase is delayed than H _REF output from the H decoder 104.

Signal C0 output from the comparator 106 to the control 107 in the case above such becomes low level, and the signal C1 becomes data corresponding to the phase difference amount between Csync and H _REF, the controller 107 is a Csync and H _REF The S0: 1, S1; 0.S2: 0 select signals are S0: 1, S1 ,;
The data selector 105 is also controlled by generating either a select signal of 0, S2: 1 or a select signal of S0: 1, S1: 1, S2: 1. Is output signal D4 output from the H decoder 104 when "228" is counted, output signal D5 output from the H decoder 104 when "229" is counted, and output from the H decoder 104 when "230" is counted. that selects and outputs any one of output signals D6, is counted up-V-counter 109 as well as resets the H counter 103, by resetting the H counter 103 at a timing later than the last time the phase difference between the Csync and H _REF Control to be zero.

In this embodiment, as shown in FIG. 4, the frequency of the clock pulse supplied from the reference clock generator 102 to the H counter 103 uses the color subcarrier frequency (3.57945 MHz). it when counting "227.5" in the counter 103, even if the phase difference between the H _REF output from the horizontal synchronizing signal and the H decoder 104 Csync inputted from the input terminal 101 is zero, after IH 0.5
Since a phase difference of one clock is generated after the clock and after 2H, the controller 107 selects the S0: 1, S1: 1, S2: 0 select signal or the S0: 0, S1: 0, S2: 1 select signal. Are alternately generated for each horizontal synchronization signal, and control the data selector 105. The data selector 105 outputs the output signals D3 and "228" output from the H decoder 104 when the H counter 103 counts "227".
And the output signal D4 output from the H decoder 104 is alternately selected and output every one horizontal synchronizing period, the H counter 103 is reset, and the V counter 109 is counted up. Is the corresponding C
The sync signal is output and supplied to the synchronization signal adding circuit 10 of FIG. 1 via the output terminal 112.

Meanwhile, the controller 107 is supplied with the signal c and the signal e shown in FIG. 2, and the controller 107 controls the output pattern of the select signal to be output to the data selector 105 according to the signals c and e. It is like.

That is, when the magnetic head 2 shown in FIG. 1 traces a recorded track on the magnetic disk 1, the signal b output from the system controller 15 is at a low level, so that the OR gate 22 shown in FIG. Output signals C and D
The signal e output from the flip-flop 19 is at a low level. At this time, the select signal supplied from the controller 107 to the data selector 105 in FIG. 4 is S0: 0.S1: in accordance with the signals C0 and C1 from the comparator 6. 0, S2: 0 to S0; 0,
One of seven types up to S1: 1, S2: 1 is supplied,
The data selector 105 selects and outputs one of the signals D0 to D6 output from the H decoder 104 according to the supplied select signal, and _sets the horizontal synchronization period of H _REF output from the H decoder 104 to 227 ± Control within 3 clocks.

When a track on the magnetic disk 1 traced by the magnetic head 2 shown in FIG. 1 is moved from a recorded track to an unrecorded track by the head moving mechanism 5, a signal b output from the system controller 15 is output. Changes from a low level to a high level, the signal C output from the OR gate 22 in FIG. 2 and the signal e output from the D terminal of the D-flip-flop 19 are the PG pin 16 shown in FIG.
At the next timing of passing through 17, the signal changes from a low level to a high level to instruct the starting of the muting operation of the muting circuit 9 in FIG. And at this time, the fourth
The controller 107 shown in the figure gives the data selector 105 a select signal of S0: 1, S1: 1, S2: 0 and a select signal of S0: 0, S1: 0, S2: 1 regardless of the signals C0 and C1 from the comparator 6. Are alternately supplied every horizontal synchronization period, and the data selector 105 selectively outputs either the D3 or D4 signal output from the H decoder 104 according to the supplied select signal, and resets the H counter 103. H decoder 1
Average value from 04 horizontal synchronization period is output 227.5 clock of H _REF, the composite synchronizing signal generator also the magnetic head 2 of FIG. 1 is not trace the unrecorded track on the magnetic disk 1 shown in FIG. 4 At 111, a Csync can be formed.

Further, when a track on the magnetic disk 1 traced by the magnetic head 2 shown in FIG. 1 is moved from an unrecorded track to a recorded track by the head moving mechanism 5, a signal b output from the system controller 15 is output. Goes from high level to low level, and the PG pin shown in FIG.
At the next timing when it passes through the PG coil 17, D in FIG.
The signal e output from the Q terminal of the flip-flop 19 changes from high level to low level, and the signal C output from the OR gate 22 remains at high level. At this time, the controller 107 shown in FIG.
Select signals supplied to the data selector 105 in accordance with the signals C0 and C1 from the S0: 0, S1: 1, S2: 0 and S2: 0
0: 1, S1; 1, S2: 0 select signal, S0: 0, S1: 0, S2: 1 select signal and S0: 1, S1: 0, S2: 1 select signal One of the four types of select signals is supplied according to the signals C0 and C1 from the comparator 6, and the data selector 105 outputs D2 to D5 output from the H decoder 104 according to the supplied select signal. , And outputs any one of the signals of H.
_{By controlling} the horizontal synchronization period of _REF within the range of "226 clock", "227 clock", "228 clock", and "229 clock", the signal b output from the system controller 15 in FIG. Changes to low level,
During the period from when the PG pin 16 passes through the PG coil 17 to the next time, the magnetic head 2 shown in FIG.
4 has a slower control response speed than the phase control response speed when the recorded track of the magnetic disk 1 is being traced, and the composite sync signal generator responds to the phase of Csync supplied to the comparator 106 in FIG. Csy output from 111
Control is performed so that the phases of nc match.

After the PG pin 16 shown in FIG. 1 passes through the PG coil 17, the signal C output from the OR gate 22 shown in FIG.
And the signal e output from the Q terminal of the D-flip-flop 19 is at a low level, and the signal e is output in the same manner as in the case where the magnetic head 2 shown in FIG. One of the signals D0 to D6 is selectively output from the data selector 105 in FIG. 4, and the phase control of Csync output from the composite synchronization signal generator 111 is performed at a high response speed.

As described above, the magnetic head 2 is moved from the magnetic disk 1 in FIG.
The composite synchronizing signal generation shown in FIG. 4 occurs when the reproduced signal is muted, when the muted state is released from muting, one vertical synchronizing period, and when muting is not performed. The Csync generated by the unit 111 is formed by different phase control operations.

As described above, in this embodiment, a new composite synchronization signal phase-synchronized with the composite synchronization signal separated from the image signal reproduced from the magnetic disk is formed, and this composite synchronization signal is added to the reproduced image signal. By exchanging with the composite synchronizing signal, a reproduced image signal maintaining the continuity of the horizontal synchronizing signal can be formed and output even when skew compensation is performed.

Also, when the magnetic head tracing the recorded track is moved, passes over the unrecorded track on the magnetic disk, and then moves to the next recorded track, when reproducing, the magnetic head is moved to the unrecorded track. During tracing, the signal reproduced by the magnetic head is muted, and a counter for forming a composite synchronizing signal synchronized with the synchronizing signal added to the reproduced image signal is self-propelled. By forming and outputting a synchronizing signal, a signal reproduced and output from this apparatus is supplied to another device such as a monitor device, for example, by a composite synchronizing signal separated from the reproduced and output signal. It is possible to reduce the phase pull-in time when the other device is operated synchronously.

Before moving the magnetic head, the signal reproduced from the magnetic disk is muted, and the phase of the composite synchronizing signal reproduced at the time of muting is the same as the phase of the composite synchronizing signal of the image signal reproduced from the magnetic disk after moving the magnetic head. Even in the case where the phase shift is 1 / 2H, the phase synchronization control is performed at a slow response speed one vertical synchronization period before the releasing of the muting operation, so that a sudden phase disturbance is generated in the composite synchronization signal. Without this, the communication of the composite synchronization signal can be maintained.

By the way, the apparatus of the present embodiment has been described by taking a still video reproducing apparatus corresponding to an NTSC television signal as an example, but the present invention is not limited to this, and for example, PAL / SE
It is also possible to adapt to a still video reproducing apparatus corresponding to a CAM television signal. In this case, the magnetic disk is rotated at 3000 [rpm], and the clock frequency of the reference clock generator in the timing signal generator 14 shown in FIG. 1 and the reset timing of the H counter and V counter are set to the PAL / SECAM. What is necessary is just to set so that it may correspond to the television signal of a system.

In this embodiment, the H decoder 10 shown in FIG.
4 from one of the signals D0 to D6 output corresponding to the seven types of count values of the H counter 103.
Is reset to reset the phase of the composite synchronizing signal generated by the composite synchronizing signal generator 111. The type of signal output from the H decoder 104 according to the count value of the H counter 103 The control range or control speed of the phase can be arbitrarily set by increasing or decreasing.

In this embodiment, the phase synchronization control is performed at a slow response speed one vertical synchronization period before the releasing of the muting operation. Phase synchronization control may be performed.

When a magnetic head reproducing a recorded track of a magnetic disk is moved to another recorded track, a muting period is provided during the movement of the magnetic head, and the muting period is slowly set one vertical synchronization period before the muting is released. By performing the phase synchronization control at the response speed set as described above, the phase of the composite synchronization signal of the image signal reproduced before the movement of the magnetic head and the composite synchronization signal of the image signal reproduced after the movement of the magnetic head becomes 1 / Even in the case where there is a 2H shift, the phase synchronization can be obtained one vertical synchronization period before the muting is canceled, and the continuity of the composite synchronization signal can be maintained without abrupt phase disturbance occurring in the composite synchronization signal. I can do it.

〔The invention's effect〕

As described above, according to the present invention, it is possible to maintain the continuity of the horizontal synchronization signal even after the skew compensation processing, and further, when an image signal is input from the reproduction unit, Thus, it is possible to provide an image signal processing device which can prevent the phase of the composite synchronizing signal from suddenly changing even when the reproduction track is switched.

[Brief description of the drawings]

FIG. 1 is a diagram showing, as an embodiment of the present invention, a schematic configuration of a still video reproducing apparatus that repeatedly reproduces an image signal from a magnetic disk on which an image signal conforming to an NTSC television signal is recorded. is there. FIG. 2 is a circuit diagram showing a part of the configuration of the timing signal generator of FIG. FIG. 3 is a timing chart showing the signal waveforms of the signal lines indicated by a to e in FIGS. 1 and 2. FIG. 4 is a diagram showing a configuration of a composite synchronizing signal generator in the timing signal generator shown in FIG. FIG. 5 is a timing chart for explaining the operation of the composite synchronization signal generator shown in FIG. FIG. 6 is a time chart showing a waveform of a synchronizing signal added to an image signal reproduced from a magnetic disk. DESCRIPTION OF SYMBOLS 1 ... Magnetic disk, 2 ... Magnetic head, 5 ... Head moving mechanism, 8 ... 1 / 2H delay circuit, 9 ... Muting circuit, 10 ... Synchronization signal addition circuit, 11 ... Envelope detection circuit, 12 …… Unrecorded track discriminating circuit, 13 …… Sync separation circuit, 14 …… Timing signal generator, 15 …… System controller, 16 …… PG pin, 17 …… PG coil, 19,20,
21 ... D-flip flop, 22 ... OR gate, 101 ...
... composite sync signal input terminal, 102 ... reference clock generator, 103 ... horizontal sync counter, 104 ... H decoder, 10
5 Data selector 106 Comparator 107
Controller, 108 Vertical sync signal detection circuit, 109
Vertical sync counter, 110... V decoder, 111... Composite sync signal generator, 112.

Claims (1)

(57) [Claims] An apparatus for inputting an image signal and processing the input image signal, wherein a composite synchronization signal for separating a first composite synchronization signal added to the image signal from the input image signal. Signal separating means; composite synchronizing signal forming means for forming a second composite synchronizing signal phase-synchronized with the first composite synchronizing signal separated by the composite synchronizing signal separating means; and muting the input image signal And a response speed of the phase synchronization control of the second composite synchronization signal with respect to the first composite synchronization signal in the composite synchronization signal forming unit during at least a part of the muting operation by the muting unit. An image signal processing device comprising: a response speed control unit configured to change the response speed during a period in which the muting operation is not performed.