JPH03107289A - Synchronous signal generator - Google Patents

Abstract

PURPOSE:To form correct various timing signals even in the case where a synchronous signal is deteriorated by comparing the generated timing signal with the regenerated and inputted synchronizing signal, and controlling a counting period according to a compared result. CONSTITUTION:A vertical blanking period in Csync incorporated in a still picture signal is detected, and when a low level is detected for over a prescribed period, a V counter 11 is reset. The detection of the low level is executed only during a period defined by a window pulse generated by detecting the PG pin of a magnetic disk. Besides, in a synchronous signal generator, Csnyc separated from the still picture signal is phase-compared with the synchronous signal formed based on a reference clock by a comparator 6, and the reset timing of a counter 7 is changed according to the phase difference, and by changing the period of the synchronous signal outputted from the counter, a desired regenerative timing signal is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization signal generator that generates various timing signals synchronized with a synchronization signal recorded on a recording medium together with an information signal.

[Conventional technology]

Traditionally, when recording, a synchronization signal is recorded on a recording medium along with an information signal, and during playback, the synchronization signal recorded on the recording medium together with the information signal is reproduced, and various timing signals are generated based on the reproduced synchronization signal. There is an information signal recording and reproducing apparatus that performs various processes on a reproduced information signal based on a timing signal generated by the information signal.

As an example of the above-mentioned information signal recording/reproducing device, a still image signal is converted into a composite synchronization signal (C) composed of a vertical synchronization signal (Vsync) and a horizontal synchronization signal (Hsync)
There is a still video recording and reproducing device that records and reproduces video on a magnetic disk along with sync).

FIG. 5 shows an example of the configuration of the synchronizing signal generator in the above-described still video recording and reproducing apparatus (see FIG. 5(a)) and a timing chart showing its operation (see FIG. 5(b)).

FIG. 5(a) is a diagram showing the configuration of a synchronizing signal generator for generating a window pulse (HBLK) for providing a horizontal blanking period in a reproduced still image signal in a still video recording and reproducing apparatus. be.

In the still video recording and reproducing apparatus, C5ync (see FIG. 5(b)) reproduced during reproduction is supplied to the reset terminal (RES) of the counter LOO in FIG. 5(a).

The counter 100 is reset during the low level period of C5ync supplied from RES, and is reset for a predetermined period (see FIG. 5(b)) from the rising edge of C5ync (70 in FIG. 5(b)).
T2) is counted, and the count data is sent to AND gate 101. 102.

The AND gate 101 determines that the output count data of the counter 100 is T in FIG. 5(b). The AND gate 102 is a gate that detects whether or not the output count data of the counter 100 reaches T from T1 in FIG. This is a gate that detects whether or not the current level has been reached, and outputs a high level signal if the current level has been reached.

Then, the signal output from the AND gate 101 is S-
The signal supplied to the set terminal (S) of the R flip-flop 103 and output from the AND gate 102 is supplied to the reset terminal (R), and as a result, the fourth signal is output from the output terminal (Q) of the S-R flip-flop 103. A window pulse (HBLK) as shown in Figure (b) is output, and in a still video recording/reproducing device, the H
A horizontal blanking period is provided in a still image signal reproduced based on BLK.

[Problem that the invention seeks to solve]

By the way, the synchronization signal generator in the above-mentioned still video recording and reproducing apparatus generates various synchronization signals based on the synchronization signal reproduced from the magnetic disk, so for example, dropouts may occur in the reproduced synchronization signal during playback. occurs, part of the signal is missing, the signal waveform is distorted due to the introduction of external noise, or the time axis of the reproduced synchronous signal fluctuates due to uneven rotation of the magnetic disk, etc. The various synchronization signals formed based on the degraded synchronization signals in this way also become inaccurate, and the reproduced still image signals that are finally processed based on the inaccurate various synchronization signals also deteriorate. become.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization signal generator that can generate various accurate timing signals even if the synchronization signal reproduced from a recording medium is degraded.

[Means to solve the problem]

The synchronous signal generator of the present invention includes a clock signal generator that generates a clock signal, a counter that counts the clock signal generated by the clock signal generator and outputs the counting result, and a synchronous signal generator that responds to the counting result of the counter. a timing signal generator that generates various timing signals; a timing signal generator that generates various timing signals; and a timing signal generator that compares the phases of the timing signal generated by the timing signal generator and a synchronization signal that is reproduced and input from a recording medium, and counts in the counter according to the comparison result. It is equipped with a phase comparator that controls the period.

[Effect]

With the above-described configuration, various accurate timing signals can be generated even if the synchronization signal reproduced from the recording medium is degraded.

〔Example〕

Hereinafter, the present invention will be explained using examples of the present invention.

FIG. 1 is a diagram showing, as an embodiment of the present invention, a schematic configuration of a synchronization signal generator in a still video recording and reproducing apparatus that handles still image signals based on NTSC television signals.

In Fig. 1, 1 is an input terminal for a composite synchronization signal (Csync) reproduced from a magnetic disk (not shown), and C5ync (see Fig. 2) inputted from input terminal 1 is a vertical synchronization signal input to a comparator 6, which will be described later. The signal is supplied to the detection circuit 9.

On the other hand, a clock pulse having a color subcarrier frequency (3.58 MHz) is generated from a reference clock generator 2 and is supplied to a clock pulse input terminal CKH of a horizontal synchronization counter (H counter) 3.

The H counter 3 counts the number of clock pulses input from the clock input terminal CKH, and supplies the count value data (see FIG. 2) to the H decoder 4.

The H decoder 4 sets the levels of the output signals D0 to D6 to high level or low level, respectively, according to the value of the count value data supplied from the H counter 3, and outputs the data selector 5.
supply to.

Incidentally, when the count value data supplied from the H counter 3 indicates 226-16=210'', the H decoder 4 in FIG. , the output signal D1 is set to high level and the count value data becomes “226-1=22
5", the output signal D2 is set to high level, and when the count value data shows "226+16=242",
The output signal D3 is set to high level, and the count value data is “
226+4=230", the output signal D4 is set to high level. When the count value data shows "226", the output signal D5 is set to high level. When the count value data shows "113", the output signal D4 is set to high level. When the signal D6 is set to high level and the count value data shows "50", the output signal H
It is configured so that REF (see FIG. 2) is set to high level. The data selector 5 selects the H
The H counter 3 is reset by outputting one of the signals DO to D6 supplied from the decoder 4 and supplying it to the reset terminal R) of the H counter 3, as well as the vertical synchronization counter (V counter) 11
is supplied to the input terminal vKv of.

On the other hand, the output signal HREF of the H decoder 4 is supplied to the comparator 6 and the counter 7, and the comparator 6
C5ync supplied from REF and the input terminal l
The output signal CO~C is detected according to the phase difference.
Level 3 is defined as high level or low level, respectively.
It is supplied to the counter 7 and the controller 8.

That is, comparator 6 indicates that the phase of C5ync is HRE.
When the output signal C1 is ahead of F, the output signal C1 is set to high level, and when it is behind, the output signal C1 is set to low level.

In addition, the comparator 6 is connected to the supplied C5ync and HRv.
The levels of output signals CO, C2, and C3 are set to high or low levels, respectively, depending on the amount of phase difference between C5ync and HREF, and the phase difference between C5ync and HREF is output from the reference clock generator 2. If the number of clock pulses is 8 or more clock pulses, the output signal CO
is set to high level, if it is 4 to 8 clocks, output signal C2 is set to high level, if it is 0 to 4 clocks, output signal C3 is set to high level, and the levels of these output signals CO to C3 are It is designed to be held for one horizontal opening period.

The counter 7 is supplied with the output signal CO of the comparator 6 and the H REF output from the H decoder 4.
The counter 7 is in a reset state when the output signal CO of the comparator 6 is at a low level, and when it is at a high level, it counts the number of pseudo horizontal synchronizing pulses of H REF supplied from the H decoder 4, and the count value is "3'', a high level output signal is supplied to the controller 8.

By the way, C5ync (third
As mentioned above, the vertical synchronization signal detection circuit 9 is also supplied with the vertical synchronization signal detection circuit 9 during the vertical synchronization blanking period (b in FIG. 3) in the supplied vertical synchronization signal. This is to detect.

In other words, as shown in Figure 3, the vertical synchronization blanking period (b in Figure 3) has a longer bellow level period than the horizontal synchronization blanking period (a in Figure 3), so the vertical synchronization signal is not detected. The circuit 9 counts the period during which the level of the supplied C5ync is low, and if the count value indicates a period longer than the horizontal synchronous blanking period (a in Figure 3), the output signal is also set to high level. , is supplied to the subsequent delay circuit 10.

The delay circuit 10 delays the output signal of the vertical synchronization signal detection circuit 9 by several H (H is the horizontal synchronization period), and outputs the output signal from the vertical synchronization counter (V
The V counter 11 is reset while the signal supplied from the delay circuit 10 is at a high level.

By the way, C5ync input from input terminal l has an equalization pulse added to it, and during the equalization pulse period (C in Figure 3) in C5ync, a different type of timing signal is sent to H from other periods. Based on the count value data of the counter 3 and the v counter 11, the vertical synchronization signal detection circuit 9 detects the vertical blanking period as described above, and generates the equalization pulse of C5ync by the H decoder 4 and the decoder 12. If the V counter 11 is reset during the equalization pulse period, the continuity of the timing signal formed during the equalization pulse period may be lost. Therefore, in this embodiment, as described above, by delaying the output signal of the vertical synchronization signal detection circuit 9 by several H using the delay circuit 10, the V counter 11 is reset at a timing sufficiently delayed from the equalization pulse period of C5ync. It is structured like this.

As mentioned above, the output signal of the data selector 5 is supplied to the clock pulse input terminal CKv of the V counter 11, and the V counter 11 counts the number of times the high level signal is supplied from the data selector 5. The count value data is output to the V decoder 12.

■When the count value data supplied from the V counter 11 reaches the number of horizontal synchronizing pulses (i.e., 263) within one frame period, the decoder 12 outputs a pseudo vertical opening signal V REF, and also outputs a pseudo vertical open signal V REF. When the count value data supplied from the counter 11 reaches a predetermined count value, the output signal BO is set to high level and is supplied to the controller 8.

Incidentally, in the still video recording and reproducing apparatus of this embodiment, a magnetic disk is rotated by a motor, and a still image signal for one field period is recorded on one of recording tracks formed concentrically on the magnetic disk. It is structured like this.

Furthermore, although the motor is controlled by a motor servo circuit or the like so that it rotates at a predetermined rotational speed, it is not possible to completely eliminate rotational irregularities, so recording of still image signals on the magnetic disk is not possible. The start position and end position may not match accurately, resulting in unrecorded portions or overwritten portions.

In the above case, as shown in d in Fig. 3, C is separated from the still image signal reproduced from the magnetic disk.
The period of the horizontal synchronization signal is not IH at the switching point between the still image signal recording start position and end position of 5ync, that is, the position corresponding to the switching point, and the phase difference between C5ync and HREF becomes large in this part. I end up.

Therefore, in the V decoder 12 of this embodiment, the V counter 11
When the count value data supplied from C5ync reaches a count value corresponding to the vicinity of the switching point (several H period), the output signal B1 is set to high level,
is supplied to the controller 8.

Hereinafter, the signal input/output operation of the controller 8 in the embodiment shown in FIG. 1 will be explained using the operation broach yard shown in FIG. 4.

In Figure 1, C5ync input from input terminal l
and H REF output from the H decoder 4 are supplied to the comparator 6, where the phase difference between the two signals is detected, and from the comparator 6, signals CO to C3 corresponding to the detected phase difference are sent to the counter 7. and is supplied to the controller 8 (see step ST1 in FIG. 4).

On the other hand, the V counter 11 counts the output signal of the data selector 5 and outputs force and runt value data according to the count value to the V decoder 12, which receives the count value data supplied from the V counter 11. When the V counter 11 reaches a predetermined count value, the output signals BO and Bl are set to high level, and the V counter 11 reaches a predetermined count value.
” is counted, the BO output from the V decoder 12
becomes high level, and the controller 8 sends SO:1, Sl:1 . to the data selector 5. S2: Outputs the 1 select signal, and the data selector 5 indicates that the H counter 3 is “11”.
When counting 3#, the output signal D6 outputted from the H decoder 4 is selectively outputted, and the H counter 3 is reset and the V counter 11 is counted up.

By the above operation, for example, the composite synchronization signal to be handled is NTSC.
When conforming to the standard IH television signal, one field period is "262.5H", so the H counter 3 is set during the normal IH period (of the clock pulse output from the reference clock generator 2). (in terms of 226 clocks), half the period (i.e. 113 clocks)
To reset the H R output from the H decoder 4,
Even at the end of one field period, C5yn
It becomes possible to synchronize with c.

Further, when the V counter 11 counts a count value corresponding to the vicinity of the switching point of C5ync, B1 outputted from the V decoder 12 becomes the NO1 level, and the controller 8 outputs the C5ync outputted from the comparator 6.
Regardless of the signal Co-C5 corresponding to the phase difference between c and HREF, approximately 5 oil, Sl:
1. B2:O and SO: 1. Sl: O.

A B2:1 select signal is output alternately every IH period,
The data selector 5 indicates that the H counter 3 is 225s or “
The output signals D2 and D5 output from the H decoder 4 when counting 226'' are alternately selected and output every IH period, and the H counter 3 is reset and the V counter 11 is counted up (step ST in FIG. 4, ~ST7
reference).

By the above-described operation, the H REF output from the H decoder 4 can be synchronized with C5ync at the position corresponding to the switching point on the magnetic disk.

Then, when both BO and Bl output from the V decoder 12 are at low level, the controller 8 outputs an output from the comparator 6 according to the direction of the phase shift (leading or lagging) between C5ync and HREF and the amount of phase difference. The select signals SO to S2 corresponding to Co-03 are output.

First, in comparator 6, C5ync and HREF
When it is detected that the phase difference between the reference clock generator 2 and the reference clock generator 2 is 0 to 4 clocks in terms of the number of clock pulses output from the reference clock generator 2, CO and C2 become low level and C3 becomes high level. , furthermore, when the phase of C5ync is ahead of HREF, C1 becomes high level, and the controller 8 sends SO:O, Sl: to the data selector 5.
1. B2:0 select signal is output, data selector 5 selects and outputs output signal D2 output from H decoder 4 when H counter 3 counts "225", and the phase of C5ync lags behind HREF. If so, CI becomes low level, and the controller 8 outputs select signals of 5oil, 5ilo, and B2:1 to the data selector 5, and the data selector 5 outputs the H decoder 4 when the H counter 3 counts 226". It selects and outputs the output signal D5 outputted from the H counter 3 and increments the V counter 11 (see steps ST8 to ST5T14 in FIG. 4).

The signal D2 or B5 output from the data selector 5 by the above operation sets the H counter 3 to 1 for the normal reset period (226 clocks in terms of the number of clock pulses output from the reference clock generator 2). Since the reset is performed at a timing shorter by one clock, the H REF output from the H decoder 4 can be brought close to the phase of C5 sync and synchronized.

Next, when the comparator 6 detects that the amount of phase difference between C5ync and HRTy is 4 to 8 clocks in terms of the number of clock pulses output from the reference clock generator 2, CO becomes low level. , C2 become high level, and when the phase of C5ync is further ahead of HREF, C1 becomes high level, and the controller 8 sends SO:i, Sl:0 . B2:
The data selector 5 selects and outputs the output signal D1 output from the H decoder 4 when the H counter 3 counts '222', and the data selector 5 outputs the select signal of C5yn.
When the phase of c lags behind HREF, C1 becomes low level, and controller 8 outputs SO to data selector 5: O.

The data selector 5 outputs the select signal of Sl:O, B2:1, selects and outputs the output signal D4 output from the H decoder 4 when the H counter 3 counts '230', and resets the H counter 3. together with V counter 11
(Step ST8.ST in Figure 4)
, , ST, , ~ST, , reference).

Through the above operation, the H counter 3 is reset by the signal DI or B4 output from the data selector 5 for the normal reset period (226 clocks in terms of the number of clock pulses output from the reference clock generator 2). In order to reset with a timing as short as 4 clocks or as long as 4 clocks, the H REF output from H decoder 4 is set to C5y.
It becomes possible to synchronize close to the phase of nc.

Further, when the comparator 6 detects that the phase difference between C5ync and HREF is equal to or more than 8 clocks in terms of the number of clock pulses output from the reference clock generator 2, CO becomes high level.

Then, the counter 7 receives the C supplied from the comparator 6.
When O is at a low level, it is in a reset state, and when it is at a high level, it is in an operating state, and the number of H REF pulses output from the H decoder 4 is counted.1. A low level signal is outputted to the controller 8 until the count value reaches "3", and a high level signal is outputted to the controller 8 when the count value reaches "3".

In this embodiment, in the comparator 6, C5ync and H
If it is detected that the phase difference with REF is 8 clocks or more in terms of the number of clock pulses output from the reference clock generator 2, noise may be mixed into C5ync or dropout may occur. It is assumed that such an abnormal condition has occurred, and the counter 7 detects 3 such abnormal conditions.
It is monitored whether or not it occurs continuously for H period.

Note that in the counter 7 that detects the continuous period of the abnormal state as described above, while the continuous period of the abnormal state does not reach the 3H period (that is, the signal supplied from the counter 7 to the controller 8 is low). level), the controller 8 applies 5 oil to the data selector 5, Sl: 0.
S2: Outputs the 1 select signal, and the data selector 5 selects and outputs the output signal D5 output from the H decoder 4 when the H counter 3 counts "226", and resets the counter 3 and also resets the V counter 11. Make the count up.

The above operation is started when the count value of the counter 7 reaches "3" or when C5ync and H are detected in the comparator 6.
The phase difference with REF is less than 8 clocks,
This process is repeated until the output signal CO becomes low level.

Then, when the continuous period of the abnormal state reaches the 3H period in the counter 7 (that is, when the signal supplied from the counter 7 to the controller 8 becomes high level), the phase of C5ync is ahead of HREF. In this case, C1 becomes high level, and the controller 8 sends SO: 0, Sl: O, S2: to the data selector 5.
The data selector 5 selectively outputs the output signal Do output from the H decoder 4 when the H counter 3 counts "210", and the data selector 5 outputs the selector signal Do of C5yn.
When the phase of c lags behind HREF (j becomes low level, the controller 8 outputs a select signal of SO:1°Sl:1.S2:0 to the data selector 6, and the data selector 5 When the H counter 3 counts "242", the output signal D3 outputted from the H decoder 4 is selected and output, and the H counter 3 is reset and the V counter 11 is counted up (steps ST, 5T2o to 5T2o in FIG. 4). ST, see).

Even if C5ync goes into an abnormal state due to the above operation, the H counter 3 is reset at the normal reset period (reference clock generator 2) by the signal D6 output from the data selector 5.
Since it is reset by 226 clock pulses (converted to the number of clock pulses output from The H counter 3 is reset at the normal reset period (reference clock generator 2
In order to reset the clock at a timing that is 16 clocks shorter or longer than the number of clock pulses output from the clock pulse (226 clocks), the HREF output from the H decoder 4 should be synchronized close to the phase of C5ync. It becomes like Desha Ru.

By the way, each of the above-mentioned operations is performed by the data selector 5,
After one type of signal among the DO-D6 output from the H decoder 4 is output, step ST1 in FIG. 4 is performed again.
C5ync and HRE are returned to comparator 6.
A phase comparison with F is performed, and the above operation is repeated.

Then, H generated from the H decog 4 as described above.
REF is supplied to the mono multi-by break 13, and ■
V REF generated by the decoder 12 is supplied to the mono multivibrator 14, and each mono multi-high jI/
-Evening 13. 14-C'lt supplied H REF ,
Using the V REF pulse as a trigger, horizontal blanking pulses each having a preset pulse width (
HBL), vertical blanking pulse (V BLK )
It is used in processing to provide a horizontal or vertical blanking period to a still image signal reproduced from a magnetic disk in a still video recording/reproducing apparatus.

In the above embodiment, the synchronization signal generator in a still video recording and reproducing apparatus that handles still image signals based on NTSC television signals has been described as an example, but the present invention is not limited to this. A similar configuration can be used for a device that complies with the television signals of the various systems. What is necessary is to change the timing at which the H counter 3 and the V counter 11 are reset.

Furthermore, in this embodiment, a case has been described in which the synchronization signal generator generates horizontal and vertical blanking pulses synchronized with the composite synchronization signal C5ync included in the reproduced still image signal. Not only this, it can also be used to form various other timing signals such as clamp pulses, and in that case, the H counter 3 and V counter 1
The decoding values of the H decoder 4 and (1) decoder 12, which decode the count value data output from 1, may be set at desired timings. In particular, a composite synchronization signal C separated from a still image signal reproduced from a magnetic disk
Instead of 5sync, a new composite synchronization signal may be created using a horizontal synchronization signal and a vertical synchronization signal formed by decoding the count value data output from the H counter 3 and the v counter 11.

In addition, in this embodiment, the signal output from the comparator 6 according to the amount of phase difference between C5ync and HREF represents the amount of phase difference as a signal in three stages of Co, C2, and C3, but the signal is not limited to this. The number of stages may be increased or decreased.

By the way, in this embodiment, the low level period in C5ync included in the still image signal reproduced from the magnetic disk, that is, the vertical blanking period (b in FIG.
) is detected, and if a low level is detected for a predetermined period or more, V
Although the counter 11 is configured to be reset, the C5 included in the still image signal reproduced from the magnetic disk
It is necessary to prevent a dropout from occurring during sync, erroneously detecting this portion, and erroneously resetting the V counter II.

In addition, the magnetic disk used in the still video recording and reproducing apparatus of this embodiment has a PG on the circumference of the core of the magnetic disk.
A still video recording/reproducing device is equipped with a magnetic medium called a pin, and when recording a still image signal on a magnetic disk, the magnetic disk is rotated, and a coil detects the position of the PG bin on the rotating magnetic disk. The rotational phase of the magnetic disk is detected, and recording of still image signals onto the magnetic disk is started and ended at the detected position of the PG pin.

Therefore, when the V counter 11 is reset as described above, a window pulse or the like is generated when the PG pin of the magnetic disk is detected, and a low level period is detected only during the period defined by the window pulse, and during other periods. By not detecting the low level period, it is possible to prevent the V counter 11 from being reset erroneously.

As explained above, in the synchronization signal generator of this embodiment, the C5ync separated from the still image signal reproduced from the magnetic disk is generated by a counter or the like based on the reference clock generated by the reference clock generator. By comparing the phase with the synchronizing signal, changing the reset timing of the counter according to the phase difference, and changing the cycle of the synchronizing signal output from the counter, it is possible to generate a desired reproduction timing signal. As a result, the C5y contained in the still image signal reproduced from the magnetic disk
It is possible to obtain a reproduction timing signal that follows changes in nc.

In addition, even if the C5ync changes, the phase of the playback timing signal is not corrected instantaneously, but is corrected by a predetermined amount, so the playback timing is stable without being disturbed by disturbances such as noise. You will be able to get a signal.

Furthermore, as shown in this example, the circuit configuration is digital, so there is no need for adjustments, stable performance is obtained even with changes in the environment such as temperature and humidity, and the circuit size can be reduced. Since it is also small-scale, it is easy to integrate it into an IC, which makes it possible to reduce the mounting area and number of parts in the device.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to provide a synchronization signal generator that can generate various accurate timing signals even when the synchronization signal reproduced from a recording medium is deteriorated. become.

[Brief explanation of drawings]

FIG. 1 is a diagram showing, as an embodiment of the present invention, a schematic configuration of a synchronization signal generator in a still video recording and reproducing apparatus that handles still image signals based on NTSC television signals. FIGS. 2 and 3 are timing charts showing signal waveforms at various parts of the synchronizing signal generator shown in FIG. 1. FIG. 4 is an operational flowchart for explaining the operation of the synchronizing signal generator shown in FIG. FIG. 5 is a diagram showing an example of the configuration of a synchronizing signal generator in a still video recording/reproducing apparatus (FIG. 5(a)) and a timing chart showing its operation (FIG. 5(b)). 1...Composite synchronization signal input terminal 2...Reference clock generator 3...Horizontal synchronization counter 4...H decoder 5...Data selector 6...Comparator 7...Counter 8... Controller 9... Vertical synchronization signal detection circuit 10... Delay circuit 11... Vertical synchronization counter 12... V decoder

Claims (1)

[Claims] a clock signal generator that generates a clock signal; a counter that counts the clock signals generated by the clock signal generator and outputs the counting results; and a timing signal that generates various timing signals according to the counting results of the counter. a generator, and a phase comparator that compares the phases of the timing signal generated by the timing signal generator and the synchronization signal reproduced and input from a recording medium, and controls the counting period in the counter according to the comparison result. A synchronous signal generator characterized by: