JPH058910B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention provides an asynchronous system (a signal system obtained from a disc, etc.) when performing superimposition (for example, displaying a picture number) in a video disc playback device. The present invention relates to a device that prevents the fluctuation of the time axis from expanding in the synchronization system (the system in which picture numbers, etc., are generated within the device).

[Conventional technology]

In a video disc playback device, when an internal image signal such as a picture number (synchronous internal signal) generated inside the device is superimposed on a video signal played back from the disc (asynchronous external signal), these two images If the signals are not synchronized, problems such as image shift will occur. For this reason, the synchronizing signal included in the video signal is detected and the internal signal is superimposed on the external signal in accordance with this timing.

However, when generating images from internal signals using digital processing, it is necessary to quantize (digitize) the time axis, but the external signal from the disk originally contains jitter (fluctuations in the time axis). This is magnified during quantization, resulting in an error of one clock, which causes fluctuations in the image of the internal signal on the television screen.

FIG. 2 schematically shows a case where a superimpose function is added to a conventional video disc device.

The reproduced signal of the disk 12 detected by the optical head 10 (this signal has a jitter component reduced to some extent by the tangential servo of the optical head 10).
is demodulated into a composite video signal by the FM detection circuit 14, and the synchronization signal is separated by the synchronization separation circuit 16.
The separated synchronizing signal is quantized on the time axis in a register 18 driven by two-phase clocks φ ₁ and φ ₂ for digital processing. The vertical/horizontal synchronization detection circuit 20 extracts a vertical synchronization signal VSYNC and a horizontal synchronization signal HSYNC from the digitized synchronization signal. The motor control circuit 22 controls the rotation of the disk motor 24 by using an FG (Frequency
Rough control is performed by frequency and phase comparison between the rotation detection pulse from Generator) 26 and the reference clock φ _h1 based on the crystal oscillation output, and the extracted vertical synchronization signal VSYNC or horizontal synchronization signal
Relatively high precision control is achieved by phase comparison between HSYNC and the reference clock φ _h2 based on the crystal oscillation output.

A TBC (Time Base Corrector) 25 is a circuit that absorbs minute jitters remaining in the composite video signal, and is composed of an analog circuit such as a variable delay line.
The TBC control circuit 27 extracts a color burst signal from the output signal of the TBC 25, compares the phase of this with a reference clock φ _c based on a 3.58MHz crystal oscillation output corresponding to the color burst subcarrier, and adjusts the color burst signal according to the phase error. By variably controlling the delay time of the TBC 25, minute jitters in external signals can be absorbed.

The external signal output from the TBC 25 is output via the synthesis circuit 28.

The image generation circuit 30 stores an internal signal to be superimposed, and uses a vertical synchronization signal VSYNC and a horizontal synchronization signal detected from an external signal.
Read the internal signal at a timing synchronized with the external signal using HSYNC. The read internal signal is
A synthesis circuit 28 synthesizes the signal with an external signal and outputs the result. In this way, the image of the internal signal is superimposed on the predetermined position of the image of the external signal.

By the way, register 1 that connects the asynchronous system and the synchronous system
8, as shown in FIG. 3, the two-phase clock φ ₁ ,
φ ₂ (The clock is based on the crystal oscillation output and rises, for example, 455 times in one horizontal scanning period H.)
is used to capture the input signal (horizontal synchronization signal) at clock _φ1 and output it at clock _φ2 .

Therefore, a quantization error occurs within the range of one clock between clocks φ ₁ and φ ₂ . In this case, as shown in Figure 3, if the jitter of the input signal swings as shown in Figure 3, the change position of the input signal will be from the falling position _t1 of clock _φ1 to the rising edge of the next clock _φ1 . Since the input signal has entered between the downlink positions _t2 , changes in the input signal are taken in by the clock _φ1a and outputted by the clock _φ2a , resulting in both output signals. Therefore, in this case, the jitter of the input signal is absorbed, and the period of the output signal is always equal to 455 regular clocks. If the center of the jitter is exactly at the center of t ₁ and t ₂ , the jitter margin is P
− P value (peak-to-peak value) clock φ ₁ ,
φ ₂ clock (140 ns, which corresponds to a half period of the color burst subcarrier).

However, the phase between the input signal and the clocks φ ₁ and φ ₂ is not necessarily at the center. For example, if the phase of the input signal swings around the center, the output signal In contrast, this is expanded to make one cycle equal to 454 clocks (shortened).
Or it will be 456 clocks (extension).

For example, Figure 4 shows an example in which the input signal has a very small jitter τ ₁ as shown in , but in this case, the input signal changes before the fall of the clock φ _1a , so this Changes are captured on clock φ _1a and output on clock φ _2a . On the other hand, since the input signal changes after the fall of the clock φ _1a , this change is reflected in the next clock φ _1b .
The signal is then fetched and output at clock _φ2b . Therefore, although the jitter τ _i is very small as an input signal, it is expanded to become τ ₀ as an output signal. Therefore, the period of the output signal fluctuates by ±1 clock from the standard 455 clocks, and becomes 454 clocks or 456 clocks.

As a result, as shown in FIG. 2, when the internal signal is read out from the image generation circuit 30 using the horizontal synchronization signal HSYNC detected by the synchronization system and synthesized with the external signal by the synthesis circuit 28, the fifth signal appears on the TV screen. As shown in the figure, when the image of the internal signal is a vertical straight line, in an asynchronous system there is a slight fluctuation corresponding to the jitter τ _i of the input signal, as shown in ○A, but in a synchronous system this is magnified. The image is then displayed shifted by one clock with respect to the previous scanning line, as shown in the circle.

Furthermore, if the main cause of the jitter component is the residual amount of disk eccentricity, the jitter is reversed every half-circle of the disk (that is, every field), so in a synchronous system there is a one-clock shift, and a vertical straight line appears on the screen. As shown in FIG. 6, each scanning line is displayed in a jagged manner, making it noticeable.

One possible way to prevent the fluctuation of the time axis in an asynchronous system from expanding in a synchronous system is to use a window. This is done by predicting the synchronous signal timing of the asynchronous system in the synchronous system, setting a window in the synchronous system to include the predicted timing, and when the synchronous signal of the asynchronous system is obtained in that window, the expected timing is set. This is regarded as the synchronous signal timing of the asynchronous system and controls the synchronous system. According to this, when a synchronous signal from the asynchronous system is obtained within the window set for the synchronous system, even if it deviates from the expected timing from the perspective of the synchronous system, the expected timing will be changed to the synchronous system's expected timing. Since it is treated as a synchronous signal, it is possible to prevent fluctuations in the time axis in the asynchronous system from expanding in the synchronous system during superimposition.

[Problem to be solved by the invention]

The main component of the jitter included in the video disc playback signal is the residual jitter component of the TBC due to the disc's fluttering, and it fluctuates periodically in synchronization with the disc rotation. If you always generate a synchronization signal using the window described above for a video disc playback signal with such unique characteristics, synchronization correction operations may occur even though sufficient synchronization is originally achieved. occurs frequently,
Unnecessary synchronization fluctuations occur in the synchronization signal of the synchronization system.

The present invention has been made in view of the above-mentioned points, and is a synchronization device for a video disc playback device that can effectively prevent unnecessary period fluctuations in the horizontal synchronization signal of the synchronization system, especially for CAV (constant rotation speed) discs. It is intended to provide a circuit.

[Means to solve the problem]

The present invention provides an asynchronous horizontal synchronizing signal detecting means for detecting an asynchronous horizontal synchronizing signal included in a constant rotational speed disc reproduction signal, and an asynchronous horizontal synchronizing signal detecting means for detecting an asynchronous horizontal synchronizing signal included in a constant rotation speed disk reproduction signal, and a synchronizing horizontal synchronizing signal detecting means that counts a reference clock and determines the timing of the specific count value. a counter that generates timing information of the synchronous horizontal synchronizing signal; a window generating means that generates a window using a predetermined period including the timing of the synchronous horizontal synchronizing signal; an in-frame phase detection means for detecting a specific phase within the frame; and an asynchronous means for detecting whether the asynchronous horizontal synchronization signal is detected within the window or outside the window at the timing when a specific phase within the frame is detected. system horizontal synchronization signal position detection means, and when the asynchronous horizontal synchronization signal is detected within the window at the timing when a specific phase within the frame is detected, the synchronization horizontal synchronization signal is obtained at a regular period. The counter is reset and controlled based on the timing of the synchronous horizontal synchronizing signal so that the asynchronous horizontal synchronizing signal is detected outside the window. The timing of the synchronous horizontal synchronous signal is adjusted so that the synchronous horizontal synchronous signal is obtained at a regular cycle except at the timing when a specific phase within the frame is detected. and reset control means for reset-controlling the counter based on the counter.

[Effect]

In the case of a CAV format video disk, two fields and one frame are recorded in one rotation of the disk, and the fluctuation period of jitter due to wow and flutter matches the frame period. Therefore, if the synchronization correction operation is limited to a specific phase within one frame, the influence of jitter fluctuations due to wow and flutter can be eliminated. Therefore, synchronization correction operations are prevented from being performed frequently, and unnecessary synchronization fluctuations are prevented from occurring in the synchronization signals of the synchronization system.

Furthermore, if the period in which the synchronization correction operation is performed is limited in this way, a synchronous horizontal synchronization signal will be generated independently of the asynchronous horizontal synchronization signal outside this period, but in a stable state of the disk circuit, the asynchronous horizontal synchronization signal will be generated independently of the asynchronous horizontal synchronization signal. The timing of the synchronization signal is just a guide, and it is sufficient that the asynchronous horizontal synchronization signal and the synchronous horizontal synchronization signal do not deviate significantly, so even a synchronization correction operation limited to such a period is sufficient.

〔Example〕

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 7 shows the overall configuration of a signal processing circuit of a video disc device equipped with a superimpose function according to the present invention.

In FIG. 7, an external signal (video disc playback signal) is input to the main TBC 32.

The main TBC 32 removes jitter (time axis fluctuation) contained in the disc playback signal, and is composed of a continuously variable delay circuit for binary signals. As a continuously variable delay circuit for binary signals, for example, a CMOS gate circuit described in Japanese Patent Application No. 160784/1984 can be used. CMOS circuit consists of P channel MOS-FET and N channel
It is composed of MOS-FETs, and due to the load capacitance formed on the output side, charging and discharging current flows when the output is reversed, providing delay characteristics. This delay time changes depending on the power supply voltage (because the conductance of the element changes). A continuously variable delay circuit for a binary signal using a CMOS gate circuit utilizes this property to delay a binary signal.

The main TBC 32 compares the phases of the horizontal synchronization signal in the external signal with a reference clock whose period corresponds to the regular horizontal synchronization signal, and controls the power supply voltage according to the phase error (consisting of a CMOS gate circuit). control the delay time and absorb jitter in the external signal.

The external signal output from the main TBC32 is
A video signal component is extracted by a BPF (band pass filter) 34.

The color TBC36 is a circuit for absorbing minute jitters that cannot be absorbed by the main TBC32.
Like the main TBC, it consists of a continuously variable delay circuit for binary signals using CMOS gate circuits, etc.
The color TBC control circuit 40
Color subcarrier on the output side of TBC36
A frequency dividing circuit 44 divides the color burst in the external signal extracted by the BPF 38 and the oscillation output of the oscillation circuit 42.
The phase is compared with the 3.58MHz reference clock corresponding to the regular color subcarrier obtained by frequency division, and the power supply voltage is controlled according to the phase error (when configured with a CMOS gate circuit). The delay time of the color TBC 36 is controlled via the circuit 46 to correct minute jitters in the external signal.

The external signal output from color TBC36 is
The signal is FM demodulated by the FM demodulation circuit 48 and guided to contact a of the switch 52 via an LPF (low pass filter) 50. Further, for correction at the time of dropout, the 1H holding circuit 54 holds the external signal from one scan ago, and leads it to contact B of the switch 52 via the FM demodulation circuit 56 and LPF 58. A dropout detection circuit 60 detects a dropout in an external signal. The switch 52 is normally connected to the contact a, and when a dropout occurs, the switch 52 is connected to the contact b side by the dropout detection circuit 60.

The external signal output from the switch 52 is output via a pedestal clamp circuit 62, a superimposed video mute circuit 64, and a video output amplifier 66.

The external signal outputted from the BPF 34 is FM demodulated by an FM demodulation circuit 68, passed through an LPF 70, and then separated into a synchronization signal (external synchronization signal) by a synchronization separation circuit 72. The vertical/horizontal synchronization signal detection circuit 74 detects the horizontal synchronization signal EXHSY and the vertical synchronization signal EXVSY from the separated external synchronization signals.

Display timing control circuit 76
When superimposing, the external signal is synchronized with the internal signal by adjusting the generation timing of the internal signal.
Character generator 7 based on EXVSY
Read out the internal signals stored in 8. The read internal signal is input to the superimpose video mute circuit 64 via the LPF 80.

The display control circuit 82 controls the superimpose video mute circuit 64 and the character generator 78 based on commands sent from the microcomputer via the interface 84. That is, when there is no superimpose command, the character generator 78 is rendered inactive, and the superimposed video mute circuit 64 is output on the external signal side. Also,
When a superimpose command is received, the character generator 78 is activated, and the superimpose video mute circuit 64 outputs a composite signal of an external signal and an internal signal.

An embodiment of this invention is shown in FIG. this is,
This shows a part of the display timing control circuit 76 in FIG. 7, in which the output count value of the HGN counter is used as a signal indicating the position on one scanning line in the internal signal.

In this embodiment, the following control is performed.

○B Rounding of external horizontal synchronization signal EXHSY by window The timing of the asynchronous external horizontal synchronization signal is predicted by the synchronous HGN counter 86, which counts 455 times in one regular horizontal scanning period, and the timing before and after the predicted timing is calculated. Total including ±n clocks
If a 2n+1 clock window is set up and the external horizontal synchronization signal EXHSY enters the window,
Even if it deviates from the center position of the window, this predicted timing (that is, the center position of the window) is treated as the horizontal synchronization timing of the synchronous system (rounding operation). As a result, even if the minute jitter τ _i in asynchronous mode is expanded by one clock due to quantization error (Figure 4), the period of the horizontal synchronization signal in the synchronous system will not be 454 clocks or 456 clocks, but the standard It becomes 455 clocks. Therefore,
The absolute time from the previous scan line in the synchronization system is fixed to the standard 455 clock time, and if the TV is slow to respond to the horizontal synchronization signal (i.e. if it triggers on average) then superimposition will occur. The vertical linear signal of the internal signal at the time will be displayed as a straight line on the screen, and if the response is good, the actual positional deviation will be within the jitter τ _i (since the clock is synchronized with the horizontal synchronization signal, τ _i ), it is possible to prevent the vertical straight line from being bent by one clock as shown in the circles in FIG. 5 and in FIG. 6.

The n value that determines the window width is 1 (window width 3 clocks) or 2 (window width 5 clocks).
The degree is appropriate.

FIG. 8 shows a state in which jitter (enlarged by quantization) is contained in a window of n=1. Further, FIG. 9 shows a state in which jitter is contained in a window of n=2. The wider the window, the wider the jitter absorption range, but it is also undesirable to widen it too much.
In the embodiment shown in FIG. 1, n=2.

○B Window correction If the external horizontal synchronization signal EXHSY is out of the window, correct the window. As shown in Fig. 10, there are two ways to correct the window: When the external horizontal synchronizing signal EXHSY deviates from the window, it is corrected so that the external horizontal synchronous signal EXHSY that has deviated comes to the center of the window; As shown in Figure 11, if the clock is adjacent to the window, it is shifted in the direction away from the window by a predetermined amount (one clock in Figure 11), and if it is outside the window by more than that, the external horizontal synchronization signal EXHSY is shifted out of the window. 2 so that it is in the center
Possible methods include making corrections in stages.

According to the latter method, it is possible to draw a window into the center of the jitter, and even if the jitter exceeds the absorption limit value, the amount of change in the period of the horizontal synchronization signal in the synchronization system is small and changes smoothly. Therefore, shifts on the screen are less noticeable. Therefore, in the embodiment shown in FIG. 1, the method shown in FIG. 11 is used.

○C Limitation of the detection timing of the external horizontal synchronization signal EXHSY According to the present invention, the detection timing of the external horizontal synchronization signal EXHSY is set to a part of a specific phase of one frame of two fields (for example, the second field 18 to 36 scan timings). That is, the main component of the jitter is the residual jitter component of the TBC due to wow and flutter of the disk, and in the case of a CAV disk, the period is one rotation of the disk and two fields. Therefore, the detection timing of the external horizontal synchronization signal EXHSY is set to 2 fields 1.
If a part of the specific phase of the frame is selected, the detection results will have values that have almost the same tendency, and the range of change will be small, as can be seen from FIG.

According to this, when the external horizontal synchronization signal EXHSY is not detected, synchronization is achieved by running the internal counter (HGN counter in Figure 1) in the synchronous system, but in a stable state of disk rotation. , the detection of the external horizontal synchronization signal EXHSY is only a guideline, and it is sufficient to know that the external horizontal synchronization and internal horizontal synchronization are not significantly different, so detection in such a portion is sufficient.

○D Correction for still images and trick play When performing still images and trick play, use the trick pulse (1
Tracks (tracks) are used to strike the adjacent tracks in front and behind. The color burst signals of adjacent tracks are 180° out of phase. Therefore,
In order not to change the color of the superimpose,
For each track turn, it is necessary to control the color TBC 36 (FIG. 7) to advance or retard the phase by 180 degrees. (This control is for color TBC36
It is also possible to use the main TBC 32 instead of using the main TBC 32. ) 180° of color burst signal is
This corresponds to one clock of the 7.16MHz master clock MCK (455 clocks in one horizontal scanning time H). Therefore, if the color TBC 36 is controlled as described above, the count value of the master clock MCK for one line will fluctuate by ±1 every time the track is turned on, so if this continues, the character position will shift by ±1 clock.

Therefore, in the embodiment shown in FIG. 1, the count value of the display system timing control counter (HGN counter 86) is corrected at the time of track start. In other words, when the video signal is advanced by 180 degrees, the period for clearing the HGN counter 86 is reduced from the standard 455 clocks to 454 clocks.
When delayed by 180 degrees, it increases from 455 clocks to 456 clocks.

Through each of the above-mentioned controls, the image position of the internal signal at the time of superimposition can be stabilized even in a synchronous system.

The circuit shown in FIG. 1 will be explained.

(1) Free-running loop HGN counter 86 that performs the rounding operation using the window described above is counted up by the master clock MCK reference clock of 7.16 MHz (455 clocks in one horizontal scanning period). The standard timing is that the HGN counter 86 is cleared every time the count value reaches 454 (the 455th count counted from the cleared state) (that is, at the regular 1st count).
horizontal scanning period). In this embodiment, this standard timing is used as the timing of the synchronous horizontal synchronization signal, and the width of the window is ±2 clocks before and after including this timing (in terms of count value, 5 clocks of 452 to 456 counts). The width of the window is set.

The HGN counter 86 outputs a pulse signal at the 450th count. This pulse signal is sequentially transferred via an AND circuit 90 to a shift register 92 driven by clocks φ ₁ and φ ₂ (two-phase clocks having the same period as the master clock MCK). The output of the 453rd count of the shift register 92 is delayed by one clock in the register 96 via the AND circuit 94, and is output via the NOR circuit 98 when the count value of the HGN counter is 454 at the standard timing.
Clear HGN counter 86. This is the external horizontal synchronization signal during the window mentioned in ○B above.
This is a free-running loop with standard timing used in rounding operations when EXHSY is present. This free-running loop also uses the external horizontal synchronization signal mentioned in ○C above.
It is also used in areas other than EXHSY detection timing.

(2) The part related to the window correction operation in ○ and B The horizontal synchronization signal output from the horizontal synchronization signal detection circuit 74 and the asynchronous horizontal synchronization signal detection means is passed through the AND circuit 100 to the shift register 102.
External horizontal sync signal EXHSY is clock-delayed.
This is an asynchronous horizontal synchronization signal. When the 451 count output of the shift register 92 becomes "1" at the timing when this external horizontal synchronization signal EXHSY is output (that is, the timing one clock before the window), the AND circuit 104 is turned on, and the shift register 106 outputs two clocks. After a delay, the HGN counter 86 is cleared via the OR circuit 108, the AND circuit 110, the OR circuit 112, and the NOR circuit 98 at the timing of 453 counts of the HGN counter 86. In other words, when the external horizontal synchronization signal EXHSY is obtained at the timing of 451 counts one window before, by clearing the HGN counter 86 one clock before the standard timing, the next window is moved one clock before the standard timing. Shift.
This is the window correction operation when the external horizontal synchronization signal EXHSY is obtained adjacent to and one clock before the window described in (b) above.

In addition, at this time, the shift register 92 is HGN
At the 453rd count of the counter 86, the 453rd count output (output for the free running loop) becomes "1",
Although added to the AND circuit 92, the HGN counter 86
At the 453rd count, the output of the NOR circuit 98 is “0”
is applied to the HGN counter 86 and also to the AND circuit 94, so the AND circuit 94 is turned off and the clearing operation of the HGN counter 86 by the free-running loop is prohibited.

The 455 count output of the shift register 92 becomes "1" (i.e., horizontal sync signal
Window 1 based on the timing of EXHSY
(timing after the clock), the AND circuit 114 turns on, and the OR circuit 108 and the AND circuit 1 turn on.
10, via the OR circuit 112 and the NOR circuit 98
Clear HGN counter 86. In other words, when it is expected that the external horizontal synchronization signal EXHSY will be obtained at the timing of 457 counts after one window, the next Shift the window back one clock. This is the external horizontal synchronization signal adjacent to the window mentioned in ○B and one clock behind.
This is the window correction operation when EXHSY is obtained.

At this time, the 453 count output of the shift register 92 becomes "1" two clocks before the 455 count output becomes "1", and this becomes the AND circuit 94.
is delayed by one clock in register 96 via
HGN counter 86 at the timing of 454 counts
is cleared, but then it is cleared again at the timing of 455 counts by the above operation, so there is no problem because the clear timing of 455 counts will be the reference for the next horizontal scanning period, and the clear timing of 454 counts will be ignored.

When the 451 to 457 counts of the shift register 92 are all "0" (that is, the timing does not belong to either the window or the ±1 clock adjacent to it) and the output of the NOR circuit 116 is "1", the external horizontal synchronization When the signal EXHSY is obtained, the AND circuit 118 turns on and the OR circuit 10
8. Clear the HGN counter 86 via the AND circuit 110, the OR circuit 112, and the NOR circuit 98. That is, the next window is determined based on the timing of the external horizontal synchronization signal EXHSY. This is,
This is a window correction operation when the external horizontal synchronization signal EXHSY is obtained far outside the window described in (b) above.

Note that if the external horizontal synchronization signal EXHSY is generated before the 450 count timing of the HGN counter 86, the HGN counter 86 will be cleared before generating the 450 count output, so the free-running loop in A above will not operate. .

Furthermore, when the external horizontal synchronization signal EXHSY is generated at the 450 count timing of the HGN counter 86, a 450 count output is generated from the HGN counter 86, but at this time the external horizontal synchronization signal
Since the AND circuit 90 is turned off by the signal obtained by inverting EXHSY by the inverter 180, the 450 count output is not transferred to the shift register 92, and the free-running loop does not operate. Note that the input to the inverter 180 is the output signal of the OR circuit 112, which is substantially equivalent to the external horizontal synchronization signal EXHSY.
EXHSYNC may also be used.

(3) The part related to the operation of limiting the detection timing of the external horizontal synchronization signal EXHSY of ○C The AND circuit 110 is detected by an intra-frame phase detection means (not shown) (for example, the first
The count value of the VGN counter 218 shown in FIG. 3 can be used. ) The operation is possible only during a predetermined period of the second field (for example, the 18th to 36th scans), and in other periods, even if the external horizontal synchronization signal EXHSY is obtained, the HGN counter 86 is Not cleared. This is the operation to limit the detection timing of the external horizontal synchronization signal EXHSY mentioned in ○C above, and at this time,
The HGN counter runs at standard timing (0 to 454 counts) by the free running loop.

(4) Part related to the corrective operation at the time of track start (circle 2) The rising edge detection circuit 118 detects the rising edge of each track start command. The CBPCH register 120 is set by inputting the output signal of the rising edge detection circuit 118 via an AND circuit 122 and an OR circuit 124 in a reset state, and is self-held via an AND circuit 126. When the CBPCH register 120 is set and the next track command is issued, the AND circuit 126 is turned off via the inverter 128. At this time, since the AND circuit 122 is made inoperable via the inverter 130, the CBPCH register 120 is reset. In this way, CBPCH register 12
The 0 state is toggled on every track command.

The output of CBPCH register 120 is transferred to shift register 132. CBPCH register 12
When 0 is initially set, when the 1st and 2nd bit outputs of the shift register 132 become a combination of "1" and "0", the 1 bit output is inverted by the inverter 134 and becomes "0", so the NOR circuit 136 is activated. Turn on,
A rising edge of the output of CBPCH register 120 is detected. Furthermore, when the 1st and 2nd bit outputs of the shift register 132 become a combination of "0" and "1" when the CBPCH register 120 is reset, the AND circuit 138 is turned on and the fall of the output of the CBPCH register 120 is detected. Ru.

When the rising edge of the output of the CBPCH register 120 is detected, the CB+ register 144 is set via an AND circuit 140 and an OR 142, and self-held via an AND circuit 146. When the CB+ register 144 is set, the shift register 92
When the 453 count output is "1", the AND circuit 148 turns on and clears the HGN counter 86 via the OR circuit 150, the AND circuit 152, the OR circuit 112, and the NOR circuit 98. That is, since it is cleared one clock before the standard timing of 454 counts, the amount by which the video signal is advanced by 180 degrees is corrected. The CB+ register 144 is
At the same time as the HGN counter 86 is cleared, it is also cleared by a signal obtained by inverting the 453 count output of the shift register 92 by the inverter 152.

When the fall of the output of the CBPCH register 120 is detected, the CB-register 164 is set via an AND circuit 160 and an OR circuit 162, and self-held via an AND circuit 166. When the CB-register 164 is set, the AND circuit 168 is turned on at the timing when the 455 count output of the shift register 92 is "1", and the OR circuit 150,
nd circuit 152, OR circuit 112, NOR circuit 98
The HGN counter 86 is cleared via the HGN counter 86. That is, since it is cleared one clock after the standard timing of 454 counts, the amount of delay of the video signal by 180 degrees is corrected. CB-register 164 is
At the same time as the HGN counter 86 is cleared, it is also cleared by a signal obtained by inverting the 455 count output of the shift register 92 by the inverter 172.

In the manner described above, correction for still images and trick play is performed.

Note that when a track kick is being performed, the output of the NOR circuit 174 becomes "0" and the AND circuit 110 is turned off, so that the HGN counter 86 is no longer cleared by the external horizontal synchronizing signal EXHSY.

Each of the above operations is performed only when the superimpose command EXDSP is given; in other cases, EXDSP = "0" and the AND circuits 100 and 152 are turned off. , these operations will no longer be performed. (however,
The control of the color TBC 36 and the like during track kick is also performed other than during superimpose. ) According to the embodiment shown in FIG. 1, even if the external horizontal synchronizing signal EXHSY deviates significantly from the internal synchronization, it operates to correct it, but the external horizontal synchronizing signal EXHSY itself is originally not far from the internal synchronization If you use only signals that are not far apart,
The burden of corrective action by the circuit of FIG. 1 is reduced.

Figure 13 shows the internal counter (HGN counter)
The external horizontal synchronization signal EXHSY is used only when the standard timing of 200 (timing of 454 counts) and the external horizontal synchronization detection signal HSYO match. That is, in FIG. 13, a synchronization separation circuit 202 extracts a synchronization signal from an asynchronous composite video signal. The edge detection circuit 204 detects edges of the extracted synchronization signal and removes signals that are clearly determined to be noise. The horizontal synchronization detection circuit 206 sets a window, detects a horizontal synchronization signal from the edge detection output, and outputs a detection signal HSYO. The HGN counter 200 is
It is cleared by the horizontal synchronization detection signal HSYO, is driven by a reference clock based on the crystal oscillation output, counts 455 (0 to 454) in one horizontal scanning period, and outputs a signal when the count value is 454.

AND circuit 208 outputs a horizontal synchronization detection signal
When the timings of HSYO and 454 count output of HGN counter 200 match, it turns on and outputs external horizontal synchronization signal EXHSY via OR circuit 210. However, this only applies during normal play; during other trick plays, a certain amount of error is allowed, and if it is within the window, it is used as a synchronization signal. That is, the AND circuit 214 becomes operational via the inverter 212, and outputs the horizontal synchronization detection signal HSYO as the external horizontal synchronization signal EXHSY.

The synchronization protection circuit 216 detects the horizontal synchronization detection signal when the horizontal synchronization signal is not obtained within the window.
HGN counter 200 as an alternative signal for HSYO
It outputs 454 count output.

The signal HSYNC (HSYO or its substitute signal) outputted from the synchronization protection circuit 216 every horizontal scanning period causes the VGN counter 218 to count up. The count value of the VGN counter 218 corresponds to the scanning line number. Vertical synchronization detection circuit 220
sets a window based on the count value of the VGN counter 218 and outputs a vertical synchronization signal EXVSY from among the synchronization signals extracted by the synchronization separation circuit 202.

〔Effect of the invention〕

As explained above, according to this invention, CAV
In the case of a video disk using this method, two fields and one frame are recorded in one rotation of the disk, and by taking advantage of the fact that this matches the fluctuation period of jitter due to wow and flutter, the synchronization correction operation is limited to a specific phase within one frame. This eliminates the influence of jitter fluctuations due to wow and flutter, prevents synchronization correction operations from being performed frequently, and prevents unnecessary synchronization fluctuations from occurring in the synchronization signal of the synchronization system.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing a schematic configuration in which a superimpose function is added to a conventional video disc playback device. Figures 3 and 4 are
FIG. 3 shows a state in which jitter is absorbed, and FIG. 4 shows a state in which jitter is expanded. FIG. 5 is a diagram showing a state in which jitter is enlarged on the screen by the enlarging effect shown in FIG. 4. FIG. 6 is a diagram showing a state in which jitter due to disk eccentricity is magnified on the screen by the magnification effect of FIG. 4. FIG. 7 is a block diagram showing the overall configuration of a disc playback device to which the present invention is applied. 8 and 9 are diagrams showing the rounding operation in the embodiment of FIG. 1, and in FIG. 8, the window width is 3.
In the case of 5 clocks, FIG. 9 shows a case where the window width is 5 clocks. FIG. 10 is a diagram showing an example of a window correction operation. FIG. 11 is a diagram showing an example of a window correction operation employed in the embodiment of FIG. 1. FIG. 12 is a diagram showing the operation of limiting the detection timing of the external horizontal synchronizing signal EXHSY according to the embodiment of FIG. 1. FIG. 13 is a block diagram showing an example of a circuit for generating an external horizontal synchronizing signal EXHSY. 74...Horizontal synchronization signal detection circuit (asynchronous horizontal synchronization signal detection means), 86...HGN counter (counter), 92...Shift register (window generation means), 90, 94, 96, 98, 104,
106, 108, 110, 112, 114, 11
6,118...Asynchronous horizontal synchronization signal position detection means and reset control means, EXHSY...Asynchronous horizontal synchronization signal, MCK...Reference clock.

Claims (1)

[Scope of Claims] 1. Asynchronous horizontal synchronization signal detection means for detecting an asynchronous horizontal synchronization signal included in a constant rotation speed disc playback signal; a counter that generates timing information of a horizontal synchronizing signal; a window generating means that generates a predetermined period including the timing of the horizontal synchronizing signal as a window; intra-frame phase detection means for detecting a specific phase; and determining whether the asynchronous horizontal synchronization signal is detected within the window or outside the window at the timing when the specific phase within the frame is detected. an asynchronous horizontal synchronizing signal position detecting means for detecting the position of the asynchronous horizontal synchronizing signal; The counter is reset and controlled based on the timing of the synchronous horizontal synchronizing signal so as to be obtained in a period, and when the asynchronous horizontal synchronizing signal is detected outside the window, the asynchronous horizontal synchronizing signal detected thereafter is controlled. The counter is reset and controlled so that the synchronous horizontal synchronous signal is within the window, and the synchronous horizontal synchronous signal is obtained at a regular period except at the timing when a specific phase within the frame is detected. and reset control means for controlling the reset of the counter based on the timing of the synchronization circuit for a video disk reproducing apparatus.