JPH042539Y2 - - Google Patents

Description

[Detailed explanation of the invention] (a) Industrial application field
The present invention relates to a high-definition TV receiver that logarithms a MUSE signal obtained by band compression using the TIC multiplex subsampling method and then D/A conversion, and particularly to its muting circuit.

(b) Conventional technology Regarding MUSE type TV receivers as mentioned in the introduction, for example, the magazine ``Nikkei Electronics 1984, 3
As detailed in pages 112 to 116 of the ``Monthly 12th issue,'' MUSE signals in the analog signal format transmitted on the SHF broadcast channel or supplied from high-definition video disc players, high-definition VTRs, etc. Once converted to a digital signal, various corrections and TCI decoding are performed. For this reason, the receiver is provided with an A/D conversion circuit and a PLL (phase locked loop) controlled clock generation circuit for supplying a sampling clock to this circuit.

Then, the clock generation circuit receives the input
It generates a sampling clock synchronized with the MUSE signal, but in this case, the line synchronization signal, which is the reference for PLL control, is the MUSE signal after A/D conversion.
Since the signal is extracted by complex digital processing, it takes a relatively long time for the sampling clock to be completely synchronized with the line synchronization signal. For this reason, the TCI decoder may not be able to reproduce normal video signals, especially when the clock generating circuit starts operating immediately after power-on, or when accessing (searching) the MUSE signal from a high-definition video disk or high-definition VTR. There was a problem where the screen became distorted.

(c) Problems that the invention aims to solve This invention was created in view of the above points,
The purpose is to prevent distorted images from being displayed on the screen when the sampling clock is not synchronized with the input MUSE signal.

(d) Means for solving the problem The present invention includes a frame pulse detection circuit that separates and derives an external frame pulse from the MUSE signal after A/D conversion, and a frame pulse detection circuit that is reset by this external frame pulse and counts the sampling clock. a frame pulse generation circuit that generates an internal frame pulse; a synchronization state detection circuit that detects coincidence/mismatch between the external and internal frame pulses; A circuit is provided to prohibit the subsequent display of the video signal.

(e) Effects According to the above configuration, when the synchronization state detection circuit detects the asynchronous state of the sampling clock, displaying of the image is prohibited, so that a distorted image will not be displayed.

(F) Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the schematic configuration of the main parts of an embodiment of a high-quality TV receiver equipped with the muting circuit of the present invention. Circuit blocks 4 to 11 are signal interpolation (correction) parts for the MUSE signal, and each The circuit block has the functions described within the block, but since these parts have been explained in the aforementioned magazines, only the characteristic parts of this embodiment will be explained below.

In Figure 1, 2 is a clock generation circuit that supplies a sampling clock to the A/D conversion circuit 1 that performs analog/digital conversion of the input MUSE signal, and this circuit is configured as a PLL control type. Then, a phase comparison is made between an internal line synchronization pulse created by frequency division of the self-generated clock pulse and an external line synchronization pulse separated and derived from the output signal of the A/D conversion circuit 1 by the line synchronization pulse detection circuit 3. The frequency of the built-in oscillator is controlled according to the comparison output.

On the other hand, 12 is a frame pulse detection circuit that separates and derives an external frame pulse from the output signal of the A/D conversion circuit 1, and the external frame pulse from this circuit is inputted as one input of the synchronization state detection circuit 14. At the same time, it is also supplied to the frame pulse generation circuit 13. That is, as shown in FIG. 2, this frame pulse generation circuit 13 uses the external frame pulse (FIG. 3A) as a reset input, and receives the 16.2MHz sampling clock from the clock generation circuit 2 as a count input. It consists of a counter 19 to
×1125 (480 is the number of sampling points per line,
1125 outputs an internal frame pulse (FIG. 3(b)) every time it counts (the number of lines per frame). This internal frame pulse is used as a vertical drive pulse VD to a picture tube deflection circuit (not shown), and is also supplied as the other input of the synchronization state detection circuit 14.

The aforementioned line synchronization pulse generated within the clock generation circuit 2 is also used as the horizontal drive pulse HD of the deflection circuit.

The synchronization state detection circuit 14, as shown in FIG.
and a D flip-flop 21 which uses the output pulse of this AND gate as a reset input and the internal frame pulse pulse as a clock input.
The data terminal of the flip-flop 21 is connected to the +B power supply via a pull-up resistor 22 and is always held at "H". Therefore, the output of this detection circuit, that is, the output of the above-mentioned D flip-flop 21 (FIG. 3C), is the phase of both frame pulses I and B during the above-mentioned transition period, such as immediately after turning on the power or when accessing the video disk. In the illustrated periods A and C, where the signals do not match, the signal becomes "L".

Therefore, the AND gates 15a, which are opened and closed by the output of the synchronization state detection circuit 14 (FIG. 3C),
15b, 15c and 17 will all be closed during the aforementioned transition period. Therefore, during this transition period, the luminance signal Y and the wideband and narrowband color signals CW and CN are output from the TCI decoder 11 via the AND gates 15a, 15b, and 15c.
are blocked, and they are converted into A/D conversion circuits 16a, 1
6b and 16c, no video signal is applied to the picture tube from the video signal processing circuit provided after the A/D conversion circuit, and the screen of the picture tube becomes completely black. Further, since the audio data outputted from the audio decoder 18 at this time is also blocked by the AND gate 17 and not input to the audio signal processing circuit, noise from the speaker is also muted.

(g) Effects of the invention According to the muting circuit of the invention, high quality
Displaying images is prohibited when the sampling pulses created in the TV receiver are not synchronized with the input MUSE signal, so when such synchronization occurs when the power is turned on or when the It is possible to prevent distorted images from being displayed during a transition period such as when accessing a high quality video disk. Moreover,
Since the detection of the synchronization shift is carried out in frame cycles by comparing the phases of frame pulses, it can be detected accurately, and there is also the advantage that no malfunction occurs in the muting operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a high-quality TV receiver equipped with the muting circuit of the present invention, FIG. 2 is a block diagram showing the detailed configuration of its main parts, and FIG. It is a signal waveform diagram of each part. 1...A/D conversion circuit, 2...Clock generation circuit, 12...Frame pulse detection circuit, 14...
Frame pulse generation circuit, 14...Synchronization state detection circuit, 15a, 15b, 15c...AND gate, 16a, 16b, 16c...D/A conversion circuit.

Claims (1)

[Scope of utility model registration request] A high-definition TV video signal is band-compressed using the TCI multiplex subsampling method and then D/A converted.
In a high-definition television receiver that receives a MUSE signal, A/D converts the MUSE signal, and then TCI decodes it for display, the A/D
PLL that creates the sampling clock for conversion
A control type clock generation circuit, a frame pulse detection circuit that separates and derives an external frame pulse from the MUSE signal after A/D conversion, and an internal frame pulse that is reset by the external frame pulse and counts the sampling clock. a frame pulse generation circuit that generates a frame pulse; a synchronization state detection circuit that detects coincidence/mismatch between the external and internal frame pulses; A muting circuit for a high-definition television receiver, comprising a circuit for inhibiting projection.