JPH05316538A - Time axis fluctuation correction circuit - Google Patents

Abstract

PURPOSE:To correct the time axis fluctuation component by making an address from an address generating means correspondent to a unit number in response to the sequence of a 2nd synchronizing signal within a 1st synchronizing signal based on the 1st synchronizing signal. CONSTITUTION:An address counter 50 generates an address of a memory 60 by counting a horizontal timing signal TH fed from a terminal 41 and gives the address to the memory 60. Moreover, an address from the address counter 50 is also fed to a control section 70. A control section 70 controls the address counter 50 so that an address to the memory 60 corresponds to a line number of a horizontal line based on a vertical timing signal TV fed via a terminal 44 and an O/E signal fed via a terminal 45. Thus, only the time axis fluctuation component generated for a prescribed period is accumulated in the memory 60 and extracted therefrom.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis which is generated in a constant cycle and which is included in an input signal including at least a first synchronizing signal and a second synchronizing signal which divides the first synchronizing signal into smaller parts. Regarding a time axis fluctuation correction circuit that corrects fluctuations,
For example, the present invention relates to an impact error correction circuit that is included in an input video signal and corrects a so-called impact error that occurs when the rotary head enters and leaves the tape.

[0002]

2. Description of the Related Art Generally, in a VTR (video tape recorder), a rotary head is used to record and reproduce a color video signal. However, uneven rotation or eccentricity of the rotary head or wow during running of a magnetic tape is used. -Time axis fluctuation (jitter) may occur in the reproduced video signal due to flutter or the like. Therefore, in the conventional VTR, the reproduced video signal is transmitted to the TBC (Time Base Correlation).
rector; time axis correction device) to eliminate time axis fluctuations.

FIG. 7 shows an example of the structure of the TBC. In the TBC 10 of FIG. 7, the color video signal Sc reproduced by the VTR is supplied to the A / D (analog / digital) converter 2 via the terminal 1 of the TBC 10. Further, the A / D converter 2 is supplied with an alternating signal Sf from an APC circuit 14 described later as a clock. This alternating signal Sf is a signal that is synchronized with the horizontal synchronizing pulse Ph and the burst signal Sb in the video signal Sc and has a frequency four times the color carrier frequency fc. Therefore, the alternating signal Sf is the A / D signal. By being supplied as a clock to the converter 2, the above A / D
In the converter 2, the video signal Sc supplied via the terminal 1 is converted into a digital signal Pc at a speed including a time base fluctuation of the video signal Sc.

The digital signal Pc is supplied to the memory 3. Further, the alternating signal Sf is also sent to the address generator 15, so that the address generator 15 forms the write address signal Sw of the memory 3 based on the alternating signal Sf. The write address signal Sw is supplied to the memory 3. As a result, in the memory 3, the digital signal Pc is sequentially written for each sample at a speed including the time base fluctuation of the video signal Sc and at the address indicated by the write address signal Sw.

At this time, the clock generator 1
7, a clock signal Sk having a stable frequency 4fc and a phase serving as a reference is formed, and the clock signal Sk is supplied to the address generator 18. The address generator 18 forms a read address signal Sr for the memory 3 based on the clock signal Sk, and sends the read address signal Sr to the memory 3. As a result, the digital signal Pc is read from the memory 3 at a constant speed.

Thereafter, the digital signal Pc read from the memory 3 is D / A (digital / analog).
It is supplied to the converter 4. The clock signal Sk is supplied to the D / A converter 4 as a clock. Therefore, the digital signal Pc supplied to the D / A converter 4 is converted into an analog color video signal Sc. The video signal Sc from which the time base fluctuation has been removed by the TBC 10 is taken out from the terminal 5.

Here, the alternating signal Sf from the APC 14 is specifically formed as follows.

That is, the video signal Sc via the terminal 1 of the TBC 10 is also sent to the sync separation circuit 11, and the sync separation circuit 11 extracts the horizontal sync pulse Ph from the video signal Sc.

This horizontal synchronizing pulse Ph is generated by PLL (phase
It is sent to the terminal 27 of the locked loop 20. This terminal 2
The horizontal synchronizing pulse Ph via 7 is sent to the phase comparison circuit 21 as a jitter detector. The phase comparison circuit 21 is connected to the circuits 22, 23, 24 and 25 in the subsequent stages together with P
An LL (phase locked loop) 20 is configured. Further, in this PLL 20, VOC (voltage contr
The oscillation signal So of the free-running frequency Nfc (4fc) is taken out from the olled oscillator (voltage controlled oscillator) 24, and the oscillation signal So is sent to the 1 / N frequency division (1/4 frequency division) circuit 25 and is horizontally transmitted here. It is divided into frequency signals. This frequency-divided signal is sent to the phase comparison circuit 21, where the phase comparison circuit 21 compares the phase with the horizontal synchronizing pulse Ph, and the comparison output signal Sp is supplied to the low-pass filter 22 to remove unnecessary components. It The output from the low-pass filter 22 is sent as a control signal for the VCO 24 through the adder circuit 23. Therefore, the VCO 24
From, an oscillation signal So synchronized with the horizontal synchronizing pulse Ph and having a frequency 4fc is extracted.

The oscillation signal So is sent to the APC circuit 14 via the terminal 28 of the PLL 20. The burst signal Sb extracted from the video signal Sc at the terminal 1 by the burst gate circuit 13 is also supplied to the APC circuit 14. In addition, this A
The PC circuit 14 is, for example, V
The horizontal synchronizing pulse P is composed of a phase comparison circuit for the CO output and the oscillation signal So and the burst signal Sb.
h, in synchronism with the burst signal Sb, and forms the alternating signal Sf having a frequency of 4fc.

Therefore, in the TBC10,
The time axis correction of the color video signal Sc as described above is performed by the alternating signal Sf.

By the way, in the VTR, time base fluctuation occurs due to vibration of the tape which occurs when the rotary head hits the tape and leaves the tape. Such time-axis fluctuation is called a so-called impact error. When this impact error occurs, one horizontal scanning time (1H) of the reproduced video signal changes, and vertical lines appear to be curved on the monitor screen. become. This impact error is a periodic error having a frequency component of several kHz.

That is, when the drum of the rotary head has a structure as shown in FIG.
When the diagonal recording track on _P is reproduced by the recording / reproducing head HD _{R / P} and the reproduced video signal is displayed on the monitor screen as shown in FIG. 9, the recording / reproducing head HD _{R / P} and other Due to the relative positional relationship with each head such as the erasing head HD _E and the DT (dynamic tracking) head HD _DT , a certain portion of the monitor screen of FIG. In the example of FIG. 9, for example, a vertical line looks bent.

However, the PLL 2 of the TBC 10 is
There is a limit to the response speed of 0, and it is possible to correct only a low frequency jitter such as several hundred Hz. However, since the impact error as described above has a high frequency of several kHz, it cannot be followed by this PLL 20, and therefore the impact error cannot be corrected.

Therefore, an impact error correction circuit 30 for correcting the impact error is added to the PLL 20 of the TBC 10 described above. The impact error correction circuit 30 determines that the impact error has a frame correlation and that the comparison output signal Sp of the phase comparison circuit 21 causes a phase error φmn (nth horizontal of the mth frame) of the video signal currently being reproduced. Paying attention to the fact that the phase error φmn) of the horizontal synchronizing pulse in the line is shown, the impact error component Si is taken out by accumulating the comparison output signal Sp every one frame period, and thereby the phase of the oscillation signal So is obtained. It is possible to control and correct the impact error.

That is, in the impact error correction circuit 30, the comparison output signal Sp from the phase comparison circuit 21 of the PLL 20 is supplied to the A / D converter 31 through the terminal 35, and the A / D converter 31 concerned. Is converted into a digital signal Pp indicating the phase error φmn of the video signal Sc currently being reproduced for each horizontal synchronizing pulse Ph. The digital signal Pp is supplied to the accumulating circuit 32, where the calculation shown in the equation (1) is performed for each horizontal line.

Σm, n = aΣm-1, n + φmn ··· (1)

However, in this equation (1), Σm,
n is a cumulative value for the n-th horizontal line up to the m-th frame, where a is a constant 0 <a <1 and is, for example, a = 31/32.

In this case, the value Σm, n is written in the address corresponding to the value n in the memory of the accumulating circuit 32,
It is read as the value Σm-1, n in the next frame period.

Then, from the accumulator circuit 32, a value Σm, n-1 is extracted as an impact error component for the video signal Sc currently being reproduced, and this value Σm, n-1 is extracted.
4 and is converted into an analog impact error component Si. This impact error component Si is the terminal 36
Is sent to the addition circuit 23 of the PLL 20 via
It is supplied as a control signal to the VCO 24 through the adder circuit 23.

As a result, the TBC 10 also corrects the time base fluctuation due to the impact error.

The accumulation of the impact error component in the accumulation circuit 32 is specifically realized by the configuration shown in FIG. That is, in FIG. 10, the digital signal Pp from the A / D converter 31 is supplied to the terminal 300 of the accumulating circuit 32, and the digital signal Pp is supplied to the memory 302 via the adding circuit 301 line by line. Written. The digital signal Pp for each line read from the memory 302 is supplied to the amplifier 3
It is sent to the adder circuit 301 after being made a level of a times (= 31/32) by 04. That is, in the accumulating circuit 32, only the impact error component is extracted by applying a digital filter to each line of the video signal.

[0023]

As described above, in detecting the impact error component Si, the jitter obtained from the phase comparison circuit (jitter detector) 21 of the PLL 20 of the TBC 10 is accumulated and held for each line. It is done by things. That is, in the TBC 10, the impact error component Si detected in the impact error correction circuit 30 is added to each line in the addition circuit 23 of the PLL 20 to form a feedforward loop so that the impact error component is corrected. I have to.

Here, conventionally, as described above, since the impact error of a certain line is added to the same line which is advanced by one frame, a delay of one frame is performed. That is, for example, in the case of a system such as the NTSC system (hereinafter referred to as the 525/60 system), the number of lines in the normal reproduction is determined to be 525 lines, and a system such as the PAL system (hereinafter referred to as the 625/50 system). In this case, the number of lines in normal reproduction is determined to be 625 lines, so the timing of reading the impact error component of each line in the memory 302 of FIG. 10 may be fixed by one frame. .. In other words,
As shown in FIG. 11, if the sample hold 1H (H; horizontal scanning period) and the filter operation 1H are subtracted, the written data is stored in the memory 525/6 as the memory 302.
It is only necessary to read after 523H for the 0 system and 623H for the 625/50 system.

However, for example, during variable speed reproduction by a DT (dynamic tracking) head, the trace state of the head changes, so that the number of equivalent lines of the reproduced video signal changes, resulting in a one-frame delay, that is, the 525/60 system, for example. In that case, it is not possible to add the impact error components of the same line with a delay of 525 lines.
In the 50 system, the impact error components on the same line cannot be added with a delay of 625 lines.

That is, for example, as can be seen from FIG. 12 showing the state of the head trace during variable speed reproduction by the DT head, the head scanning locus HS _N during normal reproduction and the head scanning locus HS ₂ during x2 speed reproduction, for example. Comparing with the above, the × 2 × speed reproduction is longer than the normal reproduction. In other words, the track pattern is apparently longer in the × 2 speed reproduction than in the normal reproduction. Therefore, in such a case, the number of lines is equivalently reduced by the amount of missing lines. Also, for example, the head scanning locus HS during still reproduction
Comparing _S and the scanning locus HS _N of the head during the normal reproduction, the speed during the still speed reproduction is shorter than that during the normal reproduction. In other words, the track pattern is apparently shorter in the still reproduction than in the normal reproduction. Therefore, in such a case, the number of lines equivalently increases due to the lack of signals.

Also, for example, in the case of a system in which compatible reproduction is possible even if the drum diameter of the rotary head is different, the trace state of the head changes. Therefore, in the case of compatible reproduction in VTRs having different drum diameters, the impact error cannot be corrected even for normal reproduction, for the same reason as described above.

That is, in a system capable of compatible reproduction, for example, a tape recorded by the rotary head A having a certain drum diameter can be reproduced by using the rotary head B having a drum diameter larger than that of the rotary head A. When the tape recorded by the rotary head A is reproduced by the rotary head B, the relative speed between the tape and the head is increased, and the signal reproduced from the rotary head B is apparently time-compressed. Becomes So in this case,
The number of lines is increased by the amount of time compression.
On the contrary, in a system capable of compatible reproduction such that the tape recorded by the rotary head B can be reproduced by the rotary head A having a small drum diameter, the tape recorded by the rotary head B is reproduced by the rotary head A. In that case, the relative speed between the tape and the head becomes slow, and the signal reproduced from the rotary head A is apparently expanded in time. Therefore, in this case, the number of lines is reduced by the amount of time extension.

From the above, the conventional method of writing data in the memory 302 as described above, delaying the data by the fixed number of lines, and reading the data cannot cope with the state in which the number of lines changes, and accordingly, ,
In the past, the impact error correction had to be limited to normal reproduction only, or the impact error correction could not be performed.

Therefore, the present invention has been proposed in view of the above-mentioned circumstances, and an impact error is generated even during variable speed reproduction by a DT head or compatible reproduction with different drum diameters. It is an object of the present invention to provide an impact error correction circuit, that is, a time axis fluctuation correction circuit capable of correcting

[0031]

The time axis fluctuation correction circuit of the present invention has been proposed in order to achieve the above-mentioned object, and at least divides between the first synchronization signal and the first synchronization signal. A time axis fluctuation correction circuit for correcting a time axis fluctuation occurring in a constant cycle included in an input signal including a second synchronizing signal to be converted, the time axis being in units of the second synchronizing signal of the input signal. It has a memory for accumulating the fluctuation component and an address generating means for counting in the second synchronization signal unit and generating an address of the memory based on the count value, and a timing corresponding to the first synchronization signal. Based on the above, the address of the memory from the address generating means is controlled to be associated with the unit number according to the order of the second synchronizing signal between the first synchronizing signals, thereby generating at the constant cycle. That only the time base fluctuation component is obtained so as to accumulate in the memory.

Further, the time base fluctuation correcting circuit of the present invention counts the addresses from the address generating means so as to comply with the order of the second synchronizing signal between the first synchronizing signals of the input signal. A detection unit that detects a timing when the unit number becomes a predetermined unit number that is determined in advance based on the first synchronization signal, and a timing that is detected by the detection unit is determined in advance based on the first synchronization signal. When it comes before the timing of the predetermined unit number, the counting by the address generating means is stopped at the timing detected by the detecting means, and then the counting by the address generating means is restarted at the timing of the first synchronizing signal. Then
When the timing detected by the detecting means comes after the timing of the predetermined unit number which is predetermined based on the first synchronizing signal, the address of the address generating means is set at the timing of the first synchronizing signal. By including control means for presetting to an address corresponding to a predetermined unit number, the address of the memory from the address generating means is set to the first address based on the timing according to the first synchronization signal. The unit numbers are made to correspond to the order of the second synchronizing signals between the synchronizing signals.

Furthermore, the time base fluctuation correction circuit of the present invention is
Based on at least the first synchronizing signal and the second synchronizing signal of the input signal, the address of the memory from the address generating means is determined according to the order of the second synchronizing signal between the first synchronizing signals. It is also possible to have address control means for performing control corresponding to the unit number.

That is, the time base fluctuation correction circuit of the present invention is an impact error correction circuit for correcting an impact error that occurs in a constant cycle contained in an input video signal including at least a vertical synchronization signal and a horizontal synchronization signal. And a memory for accumulating the jitter component of each horizontal line of the input video signal, and an address generating means for counting each horizontal line and generating an address of the memory based on the count value. By controlling the address of the memory from the address generating means to correspond to the line number of the horizontal line based on a synchronization signal, only the impact error component generated in the constant cycle is accumulated in the memory. It is a thing.

Further, this impact error correction circuit is
Detecting means for detecting the timing when the line number of the horizontal line of the input video signal becomes a predetermined line number which is predetermined based on the vertical synchronizing signal by counting the address from the address generating means; When the timing detected by the means precedes the timing of a predetermined line number determined in advance on the basis of the vertical synchronizing signal, the count is stopped by the address generating means at the timing detected by the detecting means, and then the vertical When the timing of the address generating means is restarted at the timing of the synchronizing signal and the timing detected by the detecting means is later than the timing of a predetermined line number determined in advance based on the vertical synchronizing signal, the vertical synchronizing is performed. The address of the address generating means is set to the predetermined line at the timing of the signal. By having control means for presetting to an address corresponding to the number, the address of the memory from the address generating means is made to correspond to the line number of the horizontal line based on the vertical synchronizing signal. ..

Further, the impact error correction circuit associates the address of the memory from the address generating means with the line number of the horizontal line based on at least the vertical synchronizing signal and the horizontal synchronizing signal of the input video signal. It is also possible to have an address control means for controlling.

In other words, the impact error correction circuit controls the address of the memory holding the impact error in units of vertical synchronization, so that the impact error correction which has conventionally been performed only with the normal reproduction image is performed at double speed, for example. Phase locked DT like 3x speed
This is possible not only during playback, but also during playback compatible with models with different drum diameters and impact errors.

[0038]

According to the present invention, since the second sync signal is obtained by subdividing the first sync signals, the number of the second sync signals between the first sync signals is fixed. Should be. Further, if the time-axis fluctuation components of the second sync signal unit between the first sync signals are accumulated and stored in association with the respective addresses of the memory, only the time-axis fluctuation component generated in a constant cycle is generated. It becomes a large value and is accumulated in the memory. Therefore, even if the number of the second synchronization signals between the first synchronization signals increases or decreases, the address to the memory is changed to the address of the second synchronization signals between the first synchronization signals based on the timing of the first synchronization signals. If it is matched with the unit number according to the order, it becomes possible to extract only the time-axis fluctuation component that occurs in a fixed cycle.

[0039]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the time axis fluctuation correction circuit of the present invention. In the present embodiment, an impact error correction circuit such as that applied to the above-mentioned TBC is taken as an example of the time axis fluctuation correction circuit. Further, in the present embodiment, for example, the number of lines is 525 lines (525/60 system) as in the above-mentioned NTSC system, or 625 lines (625/50 system) as in the PAL system. It can be dealt with.

The impact error correction circuit of this embodiment is
As shown in FIG. 1, a time base fluctuation that occurs at a constant period included in an input video signal including at least a vertical synchronization signal that is a first synchronization signal and a horizontal synchronization signal that is a second synchronization signal (for example, as described above). Memory 60 for correcting the above-mentioned impact error) and accumulating jitter as a time-axis fluctuation component of the input video signal in units of horizontal lines.
And an address counter 50 which is an address generating means for counting each horizontal line and generating an address of the memory 60 based on the count value. The address counter 50 is provided based on the timing according to the vertical synchronizing signal. By controlling the address from the counter 50 to the memory 60 so as to correspond to the line number of the horizontal line (the line number according to the order of the horizontal synchronizing signals between the vertical synchronizing signals), only the impact error component is obtained. The data is accumulated in the memory 60.

In FIG. 1, the terminal 42 is supplied with a digital signal Pp as a write signal through the adder circuit 301 shown in FIG. 10, for example, and the terminal 43 receives the digital signal Pp read from the memory 60. Is output. That is, the memory 60 of the present embodiment corresponds to the memory 302 of FIG. 10 described above, and therefore, although not shown in the drawing, the memory 60 of the present embodiment includes the addition as shown in FIG. Circuits, amplifiers, and the like are connected to form an impact error component cumulative operation circuit.

The memory 60 for detecting and holding the impact error component has a capacity of, for example, one frame, and is currently being reproduced for each horizontal line jitter (error component), that is, for each horizontal synchronizing pulse Ph. The digital signal Pp indicating the phase error φmn of the video signal Sc is stored.

In the present embodiment, attention is paid to the fact that even if the number of horizontal lines is increased or decreased, the required horizontal lines are from the vertical synchronizing signal of the video signal to a certain fixed number of lines.
The address of the memory 60 is controlled according to the vertical synchronizing signal. That is, in the present embodiment, paying attention to the vertical sync signal at the beginning of the diagonal recording track on the tape, the write and read addresses of the memory 60 are controlled at the timing of the vertical sync signal for each field. ing. Specifically, one frame is divided into two fields (eg, odd field and even field), and the number of horizontal lines is, for example, 263 lines (odd field) and 262 lines (even field) in the 525/60 system.
In the 625/50 system, for example, the address of the memory 60 is controlled by 313 lines (odd field) and 312 lines (even field).

In this embodiment, the control of the address of the memory 60 according to the timing of the vertical synchronizing signal is realized by the structure described below.

Returning to FIG. 1 again, the terminal 41 is supplied with the horizontal timing signal TH formed at the timing of the horizontal synchronizing signal, and the terminal 44 is formed at the vertical timing signal TH formed at the timing of the vertical synchronizing signal. Timing signal TV
However, the terminal 45 is supplied with an O / E signal indicating an odd field and an even field.

The address counter 50 has the horizontal timing signal T supplied via the terminal 1.
By counting H, the address of the memory 60 is formed and sent to the memory 60. The address from this address count 50 is also sent to the control unit 70.

The control section 70 controls the vertical timing signal TV supplied via the terminal 44 and the terminal 44.
The address counter 50 is controlled so that the address to the memory 60 corresponds to the line number of the horizontal line based on the O / E signal supplied via the.

That is, in the control section 70, the timing at which the line number of the horizontal line becomes the predetermined line number n determined in advance based on the vertical synchronizing signal by counting the address from the address counter 50. Is detected and the detected timing is a predetermined line number n which is predetermined based on the vertical synchronizing signal.
When it comes before the original timing of the above, the count operation in the address counter 50 is stopped (disabled) at the detected timing, and then the count operation in the address counter 50 is restarted at the timing of the vertical synchronization signal. (Enable), when the detected timing is later than the original timing of the predetermined line number n determined in advance based on the vertical synchronizing signal, the address of the address counter 50 is set at the timing of the vertical synchronizing signal. The address is preset to an address corresponding to a predetermined line number n.

More specifically, the control unit 70 shown in FIG. 1 is constructed as shown in FIG. In FIG. 2, the same components as those in FIG. 1 are designated by the same reference numerals.

In FIG. 2, the control unit 70 of the impact error correction circuit of this embodiment has a detection block 71.
And a judgment control block 72.

The detection block 71 counts the address from the address counter 50 so that the line number of the horizontal line of the input video signal becomes a predetermined line number which is predetermined based on the vertical synchronizing signal. Is to detect. Specifically, in the case of the 525/60 system, for example, when the O / E signal supplied through the terminal 45 indicates an odd field, the count value of the address from the address counter 50 is, for example, a value. When the O / E signal indicates an even field, the timing at which the count value of the address from the address counter 50 reaches the value 262 is detected. In other words, when the O / E signal indicates an odd field, the line number 263 is set as a predetermined line number which is predetermined based on the vertical synchronizing signal, and the address from the address counter 50 sets the line number 263. Detect the timing when it becomes as shown,
When the O / E signal indicates an even field, the predetermined line number is set to, for example, the line number 525, and the timing at which the address from the address counter 50 indicates the line number 525 is detected. Further, in the case of the 625/50 system, for example, when the O / E signal indicates an odd field, the timing at which the count value of the address from the address counter 50 becomes the value 313 is detected, and the O / E is detected. When the signal indicates an even field, the count value of the address from the address counter 50 is 6
The timing of 25 is detected. In other words, when the O / E signal indicates an odd field, the predetermined line number is set to, for example, the line number 313, and the timing at which the address indicates the line number 313 is detected, and the O / E signal is detected. When an even field is indicated, the predetermined line number is set to, for example, the line number 625, and the timing at which the address indicates the line number 625 is detected.

The output of the detection block 71 is sent to the judgment control block 72. This judgment control block 7
2 enables / disables and presets the address counter 50 based on the timing detected by the detection block 71. Specifically, for example, in the case of the 525/60 system, the determination control block 72 is the detection block 7
The timing detected in 1 is earlier than the original timing of a predetermined line number (for example, the line number 263 in the case of the odd field and the line number 525 in the case of the even field) determined based on the vertical synchronizing signal. Sometimes, the count operation in the address counter 50 is disabled at the timing detected by the detection block 71, and then the count in the address counter 50 is enabled at the timing of the vertical synchronizing signal.
That is, in the case of an odd field, the judgment control block 72 disables the address counter 50 when the address from the address counter 50 becomes the address corresponding to the line number 263, and then, by the vertical timing signal TV, When the address counter 50 is enabled and the counting is restarted to output from the address corresponding to the line number 264, in the case of an even field,
When the address becomes the address corresponding to the line number 525, it is disabled, and then the vertical timing signal TV
And enable the output from the address corresponding to the line number 1.

Further, in the case of the above-mentioned 525/60 system, this judgment control block 72 has a predetermined line number (for example, the above-mentioned odd field) at which the timing detected by the above-mentioned detection block 71 is predetermined based on the above-mentioned vertical synchronizing signal. , The line number 263 in the case of the even field, and the original timing of the line number 525 in the case of the even field, the address of the address counter 50 is set to the predetermined line number (263/525) at the timing of the vertical synchronizing signal. Preset to the address corresponding to. That is, the determination control block 72
Is an odd field, the vertical timing signal T
The address counter 50 is preset by V to output the address corresponding to the line number 264 from the address counter 50, and in the case of an even field, the address counter 50 is changed to the line number 1 by presetting according to the vertical timing signal TV. Output the corresponding address.

In the case of the 625/50 system, the predetermined line number determined on the basis of the vertical synchronizing signal in the decision control block 72 is, for example, the line number 313 when the odd field and the even field. Sometimes line number 625 and other operations are the same as the 525/60 system.

As described above, the impact error correction circuit of FIG. 2 (FIG. 1) makes the address of the memory 60 from the address counter 50 correspond to the line number of the horizontal line based on the vertical synchronizing signal. I have to.

As described above, in the impact error correction circuit of this embodiment, for example, as shown in FIG.
When the number of lines is equivalently increased by the period indicated by Li in the figure as compared with the normal reproduction such as the still reproduction of the variable speed reproduction by the head, as shown in FIG. 4 and FIG. Based on the signal TV, a certain number of horizontal lines (line number n, eg line number 263 / line number 525 for 525/60 system, 62
In the case of the 6/50 system, when the line number 313 / line number 625 is counted, the count of the address counter 50 of the memory 60 is stopped (disabled).
When the vertical sync signal comes again, it is enabled at that timing and counting is restarted (for example, in the case of a 525/60 system, line number 264 / line number 1 is 62
In the case of the 6/50 system, if the line number 313 / line number 1) is set, one frame is always used as the memory 60 for 525 or 625 lines, and the concept is exactly the same as in normal reproduction. Will be. On the contrary, when the number of lines decreases, as shown in FIGS. 4 and 5, the vertical timing signal TV is preset before the address counter 50 is stopped. 6
Although the number of lines used is less than 25, the error component of a specific line can be written and read in exactly the same manner as in normal reproduction.

Further, the impact error correction circuit is
As shown in another embodiment of FIG. 6, unlike the configurations of FIGS. 1 and 2 described above, a configuration (control unit 70 of FIGS. 1 and 2) for controlling the address counter 50 is independently provided. It is also possible.

That is, as shown in FIG. 6, the impact error correction circuit produces at least a vertical timing signal TV corresponding to the vertical synchronizing signal of the input video signal and a horizontal timing signal TH corresponding to the horizontal synchronizing signal. On the basis of the above, it is possible to have a decode counter 75 as an address control means for controlling the address from the address counter 50 to the memory 60 to correspond to the line number of the horizontal line.
The decode counter 75 shown in FIG.
Vertical timing signal TV from 4 and O from terminal 45
The horizontal timing signal TH is supplied from the terminal 46 together with the / E signal. The impact error correction circuit according to the other embodiment of FIG. 6 can effectively take out the impact error component with a simple configuration, especially in the case where the number of lines is increased.

From the above, according to the impact error correction circuit of each embodiment of the present invention, the phase-locked DT head such as ± 1 × speed, ± 2 × speed, etc. including the normal reproduction is used. Impact error correction at the time of reproduction, that is, as a specific example, when improving the image quality when a tape recorded by a VTR for high-speed shooting is reproduced at double speed and viewed as a normal image, or when performing compatible reproduction between systems having different drum diameters. It is possible to correct the impact error during normal reproduction and variable speed reproduction by the DT head, and further improve the image quality of the reproduced image of the digital VTR.

Further, according to the time-axis variation correction circuit of the present invention, not only the above-mentioned impact error correction but also any time-axis variation component (error) that occurs periodically can be corrected. Becomes

[0062]

As described above, in the time axis fluctuation correction circuit of the present invention, at least the first synchronization signal and the first synchronization signal
And a memory for accumulating a time-axis fluctuation component of a second synchronization signal unit of an input signal including a second synchronization signal for subdividing between the synchronization signals, and generating an address of the memory based on the second synchronization signal. And an address generating unit for generating an address from the address generating unit based on the first synchronization signal.
By associating with the unit number according to the order of the second synchronization signal between the synchronization signals of, the time axis variation component generated in a fixed cycle can be accumulated in the memory and taken out. The component can be corrected. For example, even during variable speed reproduction by the DT head or compatible reproduction with different drum diameters, it is possible to correct the impact error as a time axis fluctuation component that occurs in a constant cycle.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a basic configuration of an impact error correction circuit according to an embodiment of the present invention.

FIG. 2 is a block circuit diagram showing a more specific configuration of FIG.

FIG. 3 is a diagram for explaining an apparent increase in the number of lines during still reproduction by the DT head and address control by the circuit of this embodiment.

FIG. 4 is a diagram for explaining a relationship between line numbers, enable / disable of an address counter, and preset when the number of lines is increased or decreased.

FIG. 5 is a diagram showing line numbers and timings of vertical synchronization signals.

FIG. 6 is a block circuit diagram showing the configuration of another embodiment.

FIG. 7 is a block circuit diagram showing a schematic configuration of a TBC.

FIG. 8 is a diagram showing an arrangement of rotary heads.

FIG. 9 is a diagram showing a monitor screen for explaining an impact error.

FIG. 10 is a diagram showing a specific configuration of a cumulative circuit of a conventional impact error correction circuit.

FIG. 11 is a diagram for explaining the timing of writing / reading the impact error component of each line in the memory of the conventional accumulating circuit.

FIG. 12 is a diagram for explaining a head scanning locus and a track pattern during normal reproduction, × 2 speed reproduction, and still reproduction.

[Description of Codes] 50 ... Address counter 60 ... Memory 70 ... Control unit 71 ... Detection block 72 ... Judgment control block 75 ... Decode counter

Claims (3)

[Claims] 1. A time axis that corrects a time axis fluctuation that occurs in a constant cycle included in an input signal that includes at least a first synchronization signal and a second synchronization signal that subdivides the first synchronization signal. A fluctuation correction circuit, comprising: a memory for accumulating a time-axis fluctuation component of the input signal in units of the second synchronization signal; and an address generating means for generating an address of the memory based on the second synchronization signal. And having the address of the memory from the address generating means correspond to a unit number according to the order of the second synchronization signal between the first synchronization signals based on the first synchronization signal. Characteristic time axis fluctuation correction circuit. 2. A unit number according to the order of the second synchronizing signal between the first synchronizing signals of the input signal is converted into the first synchronizing signal by using the output from the address generating means. A detection unit that detects a timing at which a predetermined unit number is predetermined based on the detection unit, and a timing detected by the detection unit is earlier than a timing at which the predetermined unit number is determined based on the first synchronization signal. Then, the address output from the address generating means to the memory is stopped at the timing detected by the detecting means, and then the address output from the address generating means to the memory is restarted at the timing of the first synchronizing signal. However, when the timing detected by the detecting means is later than the timing of the predetermined unit number determined in advance based on the first synchronization signal. The control means for presetting an address from the address generating means to the memory to an address corresponding to the predetermined unit number at the timing of the first synchronizing signal. Time axis fluctuation correction circuit. 3. The address to the memory from the address generating means is set to the second synchronization signal between the first synchronization signals based on at least the first synchronization signal and the second synchronization signal of the input signal. 2. The time axis fluctuation correction circuit according to claim 1, further comprising address control means for performing control so as to correspond to a unit number corresponding to the order of the synchronization signals.