JP4011685B2 - Signal processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal processing apparatus, and more particularly to processing of a video signal input from the outside.
[0002]
[Prior art]
Conventionally known as this type of apparatus is a digital VTR that uses an image signal as a digital signal, compresses the amount of information, and records / reproduces it on a magnetic tape.
[0003]
In recent years, it has been considered to supply and record a digital image signal in such a state that information consideration is compressed to this type of digital VTR.
[0004]
By supplying and recording a digital image signal in such a compressed state, it is possible to prevent deterioration of the signal due to compression / decompression of the image signal and to reduce the amount of information of the image signal to be transmitted. It is possible to communicate image signals such as dubbing at a low transmission rate.
[0005]
In recent years, the IEEE 1394 format has attracted attention as a digital transmission communication format of this type.
[0006]
FIG. 5 is a timing chart when an image signal compressed by 1394 is transmitted. As shown in the figure, it is transmitted as a packet divided into a plurality of blocks.
[0007]
In the figure, t0, t1,... Indicate times of time slots obtained by dividing one frame period by the number of packets, and each packet is transmitted in a time slot determined as much as possible according to traffic on the transmission path. To be controlled. Also, a person number indicating a frame is transmitted in a predetermined packet only once in one frame period. In the case of an analog signal, both a horizontal synchronizing signal and a vertical synchronizing signal are supplied from the outside, whereas in a digital input signal, only a frame signal is inputted.
[0008]
[Problems to be solved by the invention]
In the digital VTR as described above, when the video related to the input video signal from the digital transmission path is displayed on the monitor, the frame period on the transmission side is not accurate. It is necessary to generate the vertical synchronization signal internally.
[0009]
For that purpose, it is conceivable to generate a clock synchronized with an external frame signal by a PLL circuit and divide this to obtain a horizontal synchronizing signal and a vertical synchronizing signal.
[0010]
However, in the case of an analog signal, the PLL circuit can be driven using a horizontal synchronization signal, whereas in the case of a digital signal, a PLL circuit using a frame signal having a very large interval with respect to the horizontal synchronization signal period. It is difficult to obtain a clock that is phase-synchronized with the input digital signal (external frame signal) accurately.
[0011]
Further, depending on the response of the PLL, if there is jitter or the like in the external frame signal, there is a problem that the screen on the monitor is disturbed due to the influence.
[0012]
An object of the present invention is to solve the above-described problems.
[0013]
Another object of the present invention is to synchronize the frame timing inside the apparatus with the frame timing on the transmission side when displaying video related to the video signal from the digital transmission path.
[0014]
Still another object of the present invention is to eliminate screen distortion when displaying an image related to a video signal from a digital transmission line.
[0015]
[Means for Solving the Problems]
In order to solve the problems as described above and achieve the above object, the present invention comprises an input means for inputting a digital video signal supplied from a digital transmission line and a frame period signal indicating a frame period of the digital video signal; First frequency dividing means for generating a first signal corresponding to a horizontal synchronization period by dividing a clock having a predetermined frequency, and a second signal corresponding to a vertical synchronization period by dividing the first signal A second frequency dividing means for generating a horizontal synchronizing signal using the first signal and a vertical synchronizing signal using the second signal, and for the input digital video signal The output means for adding and outputting the horizontal synchronizing signal and the vertical synchronizing signal, and detecting the phase difference between the frame period signal inputted by the input means and the second signal so as to eliminate the phase difference. The first Control means for controlling the frequency dividing ratio of the frequency dividing means, wherein the control means sets the frequency dividing ratio of the first frequency dividing means to a predetermined frequency dividing ratio during a first period during one frame period. In the second period, the first frequency dividing means is controlled so as to obtain a frequency dividing ratio determined based on the phase difference.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0017]
FIG. 1 is a block diagram showing the configuration of a digital VTR to which the present invention is applied. The VTR in FIG. 1 is a device conforming to the DV format proposed by the HD Digital VCR Council.
[0018]
First, the normal reproduction operation in FIG. 1 will be described.
[0019]
In FIG. 1, a reproduction circuit 103 reproduces a video signal from a tape 101 using a head (not shown), performs a demodulation process corresponding to the digital modulation process performed at the time of recording, and converts it into an original digital signal. Then, the reproduced digital signal is written in the memory 105 in accordance with the clock synchronized in phase with the reproduced digital signal.
[0020]
The error correction circuit 107 accesses the memory 105 and corrects an error in the reproduced signal by performing error correction decoding processing on the reproduced digital signal that has been subjected to error correction coding by allocating parity data during recording.
[0021]
The decoding circuit 109 reads the error-corrected reproduced signal from the memory 105 in an order suitable for the decoding process, performs a reverse process such as a variable length code decoding process and an inverse DCT process, and expands the amount of information. Write to the memory 111.
[0022]
The output circuit 113 reads the reproduced video signals from the memory 111 in an order suitable for display on the monitor 20, adds horizontal and vertical synchronization signals, converts them into analog signals, and outputs them to the monitor 20.
[0023]
Further, the digital I / F 117 is written in the memory 105, and the encoded digital video signal that has been subjected to the error correction processing by the error correction processing circuit 107 is converted into a transmission form in accordance with the above-described IEEE 1394 format. And output to the digital transmission line 30 as shown in FIG.
[0024]
Next, a case where a video signal transmitted from the digital transmission path 30 is output will be described.
[0025]
A signal input from the digital transmission path 30 is separated in the digital I / F 117 into a main signal such as a clock signal CLK and a video signal, and the frame synchronization signal (hereinafter referred to as an external FR signal). The digital I / F 117 writes the video signal in the memory 105 according to this CLK, and outputs the external FR signal to the control circuit 115.
[0026]
The video signal written in the memory 105 is decoded by the decoding circuit 109 and written in the memory 111 as described above.
[0027]
The read control circuit 115 generates a read address of the memory 111 using an external FR signal from the digital I / F, and generates and outputs an internal H signal and an internal frame signal (hereinafter referred to as an internal FR signal) as will be described later. Output to the circuit 113. The output circuit 113 adds a horizontal / vertical synchronization signal to the video signal read according to the read address from the read control circuit 115, using the internal H signal and internal FR signal output from the digital I / F 117. Output to the monitor 20.
[0028]
Next, the read control circuit 115 will be described with reference to FIG.
[0029]
FIG. 2 is a block diagram showing the configuration of the read control circuit 115.
[0030]
In FIG. 2, 203 is a crystal oscillator, which generates a clock with a fixed frequency (13.5 MHz in this embodiment). The H counter 205 counts the clock from the oscillator 203, generates a pulse when the predetermined number is counted, and resets to divide the clock from the oscillator 203 to generate an internal H signal corresponding to the horizontal synchronization period. . Normally, when the NTSC video signal is handled, the count value of the H counter is set to 858.
[0031]
The V counter 207 counts the internal H signal from the H counter 205, generates a pulse when the predetermined number is counted, and resets to divide the internal H signal from the H counter 205. An internal FR signal corresponding to is generated. When handling an NTSC video signal, the count value of the V counter is set to 525.
[0032]
The address generation circuit 209 generates a read address of the memory 111 using the internal H signal and the internal FR signal from the H counter 205 and the V counter 207, reads a video signal from the memory 111, and outputs it to the output circuit 113.
[0033]
Further, the internal H signal and the internal FR signal are output to the output circuit 113. The output circuit 113 generates a horizontal / vertical synchronization signal using these signals and adds it to the video signal read from the memory 111.
[0034]
The control circuit 201 detects the phase difference between the external FR signal output from the digital I / F and the internal FR signal from the V counter 207 as described above, and changes the count value of the H counter 205 according to the phase difference. Thus, the frequency division ratio is changed by the H counter 205.
[0035]
That is, when the phase of the internal FR signal is delayed, the count value is made smaller than 858 to increase the frequency of the internal H signal, and when the phase of the internal FR signal is advanced, the count value is made smaller than 858. Increase the frequency to lower the frequency of the internal H signal.
[0036]
However, in this embodiment, the count value of the H counter 205 is not changed uniformly, but the count value is set to a value different from 858 only during the period corresponding to the vertical blanking period, and is fixed to 858 during the effective display period. To do.
[0037]
As shown in FIG. 3, in the NTSC video signal, the number of horizontal scanning lines in one frame is 525, of which 480 are effective scanning lines and the remaining 45 are vertical blanking sections. Generally, 480 effective scanning line portions are displayed on the screen of the monitor 20, and the video signal of the vertical blanking portion is not displayed. For example, when the monitor 20 is a CRT display, the electron beam scanned to the bottom of the screen during this vertical blanking period is returned to the top of the screen.
[0038]
Therefore, in this embodiment, when there is a phase difference between the external FR signal and the internal FR signal, the control circuit 201 determines the period for 45 lines of the vertical blanking unit based on the internal H signal from the H counter 205. The count value of the H counter 205 is changed so as to eliminate the phase difference, and the count value remains fixed at 858 for the period of the other 480 lines.
[0039]
As a result, the cycle of the internal H signal output from the vertical blanking unit varies, the length of the horizontal synchronization period varies, and the length of the vertical blanking period also varies. However, in the monitor 20, the vertical blanking period Even when the length of the screen fluctuates, the fluctuation can be absorbed outside the effective display period, and the screen is not disturbed during the effective display period. Further, the cycle of the internal FR signal can be made to follow the external FR signal.
[0040]
For example, in the case of a CRT display, even if the vertical blanking portion 45 line is shortened to about 40 lines, it can be displayed in a sufficiently stable state by the effective display period.
[0041]
As described above, in this embodiment, when the video signal supplied from the digital transmission path is output to the external monitor, only the period corresponding to the vertical blanking unit is obtained according to the phase difference between the external FR signal and the internal FR signal. Since the length of the vertical blanking period is changed by changing the frequency division ratio by the H counter 205 and the phase fluctuation is absorbed, an internal frame signal that is phase-synchronized with an external frame signal can be obtained. Therefore, the disturbance of the effective display screen can be reduced as compared with the case where the division ratio is changed uniformly over the entire screen.
[0042]
In the above-described embodiment, only the count value of the H counter 205 is changed. However, the count value of the V counter 207 may be changed.
[0043]
For example, when the position of the frame signal of the supplied digital signal changes greatly, such as when the apparatus on the supply side is changed, it takes a very long time for the internal FR signal to follow the external FR signal. For this reason, in this embodiment, the count value of the V counter 207 is also controllable. When the position (phase) of the external FR signal changes greatly, the count value of the V counter 207 is first controlled to obtain the external FR signal. When the internal FR signal catches up with the external FR signal almost immediately, the count value of the V counter is fixed at 525, and the operation returns to the operation of controlling the count value of the H counter 205 as in the above-described embodiment.
[0044]
FIG. 6 shows this state.
[0045]
FIG. 6 is a timing chart showing the appearance of the external FR signal and the internal FR signal, and the frame position of the input video signal is greatly changed at the time T1 in the figure. Therefore, the fluctuation of the external FR signal is detected by the control circuit 201, and the count value of the V counter 207 is controlled.
[0046]
In the example of FIG. 6, four frame periods are required for the internal FR signal to follow, but this follow-up period can be controlled by setting the count value of the V counter 207. That is, even the reset operation of the V counter 207 that immediately follows when the input signal is switched can be operated so as to minimize the change in the frequency of the FR signal because the tracking period may be long.
[0047]
The count value of the V counter 207 is fixed at 525 in the case of an NTSC signal. However, if the number of horizontal scanning lines is different, such as a signal from a consumer game device, the count value is set according to the number of scanning lines. By setting, it is possible to perform the same processing as in the above-described embodiment.
[0048]
Note that the phase comparison processing by the control circuit 201 may be performed once per frame, which is suitable for processing by a microcomputer, and the processing of the control circuit 201 may be performed by software processing by the microcomputer.
[0049]
【The invention's effect】
As described above, according to the present invention, in one screen period, the first division period has a predetermined division ratio, and the second period has a division ratio determined according to the phase difference. Without disturbing the display screen, the frame period of the internal image signal and the frame period of the digital signal transmitted from the outside can be synchronized.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration example of a playback apparatus to which the present invention is applied.
FIG. 2 is a diagram illustrating a configuration of a read control circuit in FIG. 1;
FIG. 3 is a diagram for explaining the operation of the circuit of FIG. 2;
4 is a diagram showing another configuration of the read circuit in FIG. 1; FIG.
5 is a timing chart showing the state of signals input to and output from the apparatus of FIG.
6 is a timing chart for explaining the operation of the circuit of FIG. 4;
[Explanation of symbols]
115 Read Control Circuit 201 Control Circuit 205 H Counter 207 V Counter

Claims (4)

Input means for inputting a digital video signal supplied from a digital transmission line and a frame period signal indicating a frame period of the digital video signal;
First frequency dividing means for dividing a clock of a predetermined frequency to generate a first signal corresponding to the horizontal synchronization period;
Second frequency dividing means for dividing the first signal to generate a second signal corresponding to a vertical synchronization period;
A horizontal synchronizing signal is generated using the first signal and a vertical synchronizing signal is generated using the second signal, and the horizontal synchronizing signal and the vertical synchronizing signal are added to the input digital video signal. Output means for outputting,
Control means for detecting a phase difference between the frame period signal inputted by the input means and the second signal, and for controlling a frequency dividing ratio of the first frequency dividing means so as to eliminate the phase difference; Prepared,
The control means sets the frequency division ratio of the first frequency dividing means to a predetermined frequency division ratio in the first period during one frame period, and frequency division determined based on the phase difference in the second period A signal processing apparatus that controls the first frequency dividing means to obtain a ratio. Input means for inputting a digital video signal supplied from a digital transmission line and a frame period signal indicating a frame period of the digital video signal;
A first counter that counts a clock having a predetermined frequency and generates a first signal corresponding to a horizontal synchronization period in response to the count value reaching a first set value;
A second counter that counts the first signal and generates a second signal corresponding to a vertical synchronization period in response to the count value reaching a second set value;
A horizontal synchronizing signal is generated using the first signal and a vertical synchronizing signal is generated using the second signal, and the horizontal synchronizing signal and the vertical synchronizing signal are added to the input digital video signal. Output means for outputting,
Control means for detecting a phase difference between the frame period signal inputted by the input means and the second signal, and changing the first set value and the second set value so as to eliminate the phase difference. And a signal processing device.   The control means further sets the first set value to a predetermined value in a period other than the vertical blanking period in one frame period, and sets the first set value in a period corresponding to the vertical blanking period. The signal processing apparatus according to claim 2, wherein the value is determined based on the phase difference. Input means for inputting a digital video signal supplied together with a frame period signal from a digital transmission line;
A memory for storing a digital video signal input by the input means;
A first counter that counts a clock having a predetermined frequency and generates a first signal corresponding to a horizontal synchronization period in response to the count value reaching a first set value;
A second counter that counts the first signal and generates a second signal corresponding to a frame period in response to the count value reaching a second set value;
Output means for reading out and outputting the digital video signal stored in the memory according to the first signal and the second signal;
Detecting means for detecting a difference between a frame period signal input by the input means and a frame period of a video signal output by the output means;
In order to eliminate the difference detected by the detection means, the first set value is changed to change the horizontal synchronization period of the output video signal, and the second set value is changed to the output. A signal processing apparatus comprising control means for changing a frame period of a video signal.

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