JPS6052499B2 - memory device - Google Patents

Description

[Detailed description of the invention] The present invention relates to memory devices.

The purpose of the present invention is to detect overflow or underflow caused by a shift in one of the periods of RAM (Random Access Memory) when writing and reading are performed alternately, and by this detection, write At least one of the address and the read address is returned to a predetermined address. Another object of the present invention is to provide means for detecting and processing overflow or underflow caused by fluctuations in the frequency of the write clock or read clock when compressing or expanding the time axis of data. As an example, a device has been proposed that uses a VTR capable of recording and reproducing wideband signals to record and reproduce acoustic signals using the PCM method, making the recorded signal for the VTR identical in format to the television signal. . In such devices, it is necessary to use a memory device to compress data on the time axis when recording, and expand the data on the time axis when playing back, but time axis fluctuations such as jitter remain in the reproduced signal. Therefore, overflow or underflow occurs during decompression processing. The present invention constitutes a memory device suitable for use in data expansion during reproduction. Fig. 1 shows an outline of a device for recording and reproducing acoustic signals in PCM format using a VTR, in which 1 indicates a helical scan rotary two-head VTR, 2i its recording signal input terminal, and 20 its reproduction signal output terminal. It is 7.

Further, 3L indicates an input terminal for an audio signal, for example, the left signal of a two-channel stereo signal, and this signal is passed through a low-pass filter 4L, so that the high frequency range is somewhat limited.
Sampled by the sampling hold circuit 5L, A
The sampling output is converted into a parallel code by the D converter 6L, further converted into a serial code by the parallel-to-serial converter 7, and written into the memory device 8. On the other hand, the right signal is supplied from the input terminal 3R, is converted into a parallel code by passing through the low-pass filter 4R1, the sampling hold circuit 5R, and the pigeon converter 6R, and is further converted into a serial code by the parallel-serial converter 7. 8 is written. The readout output of the memory device 8 is supplied to a mixer 9, where an equalization pulse and a synchronization signal are added.
The signal is supplied to the recording signal input terminal 21 of the VTR1, and is sequentially recorded as an inclined track on the magnetic tape by two rotating magnetic heads via the recording system of the VTR1, which includes an FM modulator (not shown). Note that 10 is a pulse generator that generates gate pulses supplied to sampling and hold circuits 5L and 5R, clock pulses for AD converters 6L and 6R and parallel-serial converter 7, clock pulses for memory device 8, equalization pulses, and synchronization signals. , and 11 indicates a fixed reference clock generator.

During playback, a playback signal with a waveform similar to the above-mentioned recording signal waveform appears from the output terminal 20 and is supplied to the synchronization separation circuit 29, and only data is obtained at its output, which is written into the memory device 28.

The memory device 28 expands the data along the time axis, contrary to the time of recording, and removes time axis fluctuations such as jitter, so that the read output of the memory device 28 has no missing data and no time axis fluctuations. ．． It will be removed,
This is converted into a parallel code by the serial/parallel converter 27, and D
A converters 26L, 26R and low pass filter 24L,
Terminals 23L and 23R are connected through terminals 24R and 24R, respectively.
Continuous stereo left signal and stereo right signal! is demodulated and obtained. The synchronization signals separated by the synchronization separation circuit 29 are supplied to the pulse generator 20, and based on these synchronization signals, clock pulses and control pulses for the memory device 28, the serial/parallel converter 27, and the DA converter 26 are generated.
Four clock pulses are formed for L and 26R. As described above, when an audio signal is recorded and reproduced by the PCM method using TRl, the recording signal waveform including digital information is formally the same as the television signal.

This has a signal processing circuit for recording and reproducing audio signals using the PCM system in the form of an adapter, and in addition to the original function of recording and reproducing television signals, by attaching the above adapter, you can perform the following functions without making any changes to the VTR itself. This is to enable recording and reproduction of high-quality audio signals. FIG. 2A shows a recording signal waveform considered based on such considerations, in which a horizontal synchronizing signal HD, a vertical synchronizing signal VD, and data are arranged in series in units of one field of a television signal.

As an example, based on the frequency characteristics of a VTR1, the highest transmission bit rate is 1.4r1V4b/SeC, and the number of bits required to encode an audio signal is 26 bits per word, which is 1 word (hereinafter referred to as 1 block). )
For each: The number of bits allocated to the inserted horizontal synchronization signal mark is 2 bits, and the sampling rate is 40kHz.
In addition, the transmission rate f for each block is
The transmission rate F for each block that satisfies the condition that is an integral multiple of the horizontal frequency (15.75kHz) is 4.
The frequency becomes 7.25kHz. In addition to the above conditions, the sampling frequency L is determined by adding the condition that the sampling rate Fs of the analog signal and the transmission rate f1 are selected in an integer ratio relationship in order to compress and expand the time axis of data within one field. Therefore, the sampling rate L is 44.1
kHz is selected. At this time (F,:Fs=15:14
). Therefore, the data sampled during one field (Tec) is 735 samples. Since this is sent at a transmission rate F, which is three times the horizontal period H of the television signal, the data in one field is 735 blocks (245H in time) as shown in FIG. 2A. Therefore, the data missing period 1RG in the l field is (2
62.5FI-245H=17.5H). In this period 1RG, as shown in FIG. 2C, an equalization pulse is inserted over a targeted period similar to the equalization pulse of the television signal, and a vertical synchronizing signal VD is inserted in the targeted period following this equalization pulse. is inserted. The equalization pulse is a negative pulse with a pulse width equivalent to 1 bit and a period of 14 bits, and the vertical synchronization signal D includes a positive pulse with a pulse width equivalent to 2 bits and a period of 14 bits. Note that the equalization pulse following the vertical synchronization signal VD in the television signal is not particularly required and is therefore not inserted. Also, data is input from a point 3 blocks away from the trailing edge of the vertical synchronization signal VD for even fields and 2.5 blocks for odd fields.
One RG period is set to be 17.5H on average. Furthermore, no data is inserted in the period of about 101{ before the equalization pulse, and only the horizontal synchronization signal HD is inserted, so that it is not affected by noise caused by head switching, etc. that occurs near the vertical synchronization signal VD. It is being done. Further, the number N of bits allocated to one block of data is selected to be 28 bits from the highest transmission bit of VTR1.

FIG. 2B shows this one block, in which one word of 26-bit data is inserted after a horizontal synchronizing signal having a pulse width equivalent to 2 bits. In this case, the left and right signal data of the two-channel stereo signal are 13 bits each, and the left signal data is inserted in the first half of one block, and the right signal data is inserted in the second half. There is. The horizontal synchronizing signal has a more negative level than the data ゜"O゛, and the amplitude ratio of the two is (3:7).
In the above PCM recording and reproducing apparatus for audio signals, the memory devices 8 and 28 are required to be able to perform writing and reading asynchronously in order to convert the time axis of data.

For this reason, first-in-first-out (FirstInFirstO) that can write and read simultaneously.
ut) type shift register can be applied. However, this shift register is disadvantageous compared to RAM in terms of cost when applied when a capacity of several kilobits or more is required. On the other hand, when operating a RAM, it is impossible to perform writing and reading asynchronously because there is a risk that writing and reading will overlap for the same address. However, by devising control over the RAM, writing and reading can be performed asynchronously. Furthermore, in the audio signal recording/reproducing apparatus shown in FIG. 1, the memory devices 8, 28, etc. can be used in common during recording and reproduction.

FIG. 3 shows the memory device and its peripheral circuits in this case. In Fig. 3, 30 is an input amplifier, 31 is a RAM
32 is a memory control circuit including an address counter, etc.;
7 is a serial/parallel converter. 41, 42, 43, 44, 4
5 indicates a switching circuit that is switched depending on the operating state of the TRl, that is, whether the VTRl is in a recording state or a reproducing state;
In a recording state, it is connected to the REC side, in a state other than recording, it is connected to the output side, and in a playback state, it is connected to the PLB side.

The switching circuits 41 to 45 output a mode signal REC generated by a mode signal generator 47 based on the operation of the recording switch 46.
, and controlled by PLB. And when recording,
The recording switch 46 is turned on, and the parallel data from the AD converter is converted into a serial code by the serial/parallel converter 37, and written to the RAM 3l via the switching circuit 41.
The time-base compressed data from I is supplied to the mixer 9 via the switching circuit 42, a synchronizing signal is added thereto, and the data is supplied to the VTR I as a recording signal. A synchronization signal is generated by a synchronization signal generator 33 from the output of the reference clock generator 11. In addition, since the conversion of the time axis of data is performed in conjunction (synchronization) with the synchronization signal, the synchronization signal is transmitted to the switching circuit 4.
5 and is supplied to the memory control circuit 32. At the same time, a start/stop signal from the start/stop signal generator 35 is supplied to the memory control circuit 32 and the serial/parallel converter 37, thereby defining the timing of data processing for one field. For this purpose, mode signals REC and PLB are supplied to the start/stop signal generator 35, as well as a synchronization signal via the switching circuit 43 and the synchronization separation circuit 36. Further, a clock pulse generator 34 generates clock pulses for the RAM 31 and the serial/parallel converter 37. l Next, during reproduction, the recording switch 46 is turned off, and the switching circuits 41 to 45 are in a state in which they are connected to the PLB side or the rainbow side, unlike the state shown in the figure.

Then, the reproduced signal from the VTR1 is written to the RAM 31 via the input amplifier 30 and the switching circuit 41, and the synchronization signal is separated from the reproduced signal by the synchronization separation circuit 36. In conjunction with this synchronization signal, a clock pulse generator 34 generates a clock pulse, and a start/stop signal generator 35 generates a start/stop signal.
Then, the time axis of the data is expanded by the RAM 73l, and the data is supplied to the serial/parallel converter 37 via the switching circuit 42, where it is converted into a parallel code and then supplied to the DA converter. The mode signal generator 47 generates a mode signal based on the on/off state of the recording switch 46, and in this case is configured so that the actually generated mode signal is synchronized with the synchronization signal.

Further, in addition to the mode signal, a standby signal STBY is generated to clear the address counter of the memory control circuit 32 and the serial/parallel converter 37. FIG. 4 shows the configuration of the mode signal generator 47. When the recording switch 46 is turned on, its output becomes ゜゜0゛ as shown in Fig. 5A, which becomes the signal °C.

The signal is then supplied to a NAND circuit 52 via an inverter 51, delayed by an integrating circuit 53, and supplied to an inverter 54. The output of this inverter 54 is as shown in FIG. 5B, and since this is supplied to the NAND circuit 52, the output of the NAND circuit 52 is as shown in FIG. 5C. Further, the output of the inverter 54 is supplied to the inverter 56 via the integrating circuit 55, and the output of the inverter 56 becomes as shown in FIG. 5D, which becomes the signal REC. Further, when the output of the inverter 51 is "0", the reproduced vertical synchronizing signal PSVD is separated from the reproduced signal shown in FIG. 5E.
A monostable multivibrator (referred to as monomulti) MMIO is provided which is triggered by the rising edge of . Mono multi r! 4r! The time constant of 410 is selected to have a metastable period longer than one field (Music C), and the structure is such that it can be retriggered. Therefore, the mono-multi MMlO is triggered by the first reproduced vertical synchronizing signal PSVD, and thereafter is retriggered, so its output Q maintains the state of "゜1゛" as shown in Fig. 5F. is supplied to the NAND circuit 57 and is also supplied to the NAND circuit 57 via the integrating circuit 58 and the inverter 59.The output of the inverter 59 is as shown in FIG. The output is as shown in H in the same figure.In addition, the output of the inverter 59 is output to the integrating circuit 60.
The signal is supplied to the inverter 61 via the inverter 61, and its output (FIG. 5, 1) becomes the mode signal PLB. In addition, the NAND circuit 52
and 57 are supplied to a NAND circuit 62, the output of the NAND circuit 62 is supplied to an inverter 63, and the output of the inverter 63 shown in FIG. 5J is a standby signal STBY.
becomes. With the above configuration of the mode signal generator 47, the mode signal REC, drunkenness? , PLB, and a standby signal STBY that is generated when the recording switch 46 is turned on and when it is turned off and the first reproduction vertical synchronization signal PSVD is generated. FIG. 6 shows an example of the clock pulse generator 34 for forming clock pulses from the mode signal from the mode signal generator 47 mentioned above and the reference clock pulse from the reference clock generator 11. The reference clock generator 11 is configured as a stable oscillator such as a crystal oscillator, and has a transmission lock frequency (28ft=
Generates a signal of 1.32aMHZ). During recording, the mode signal REC is supplied to the frequency divider 94 via the NAND circuits 91 and 92, and the frequency is divided into a sampling signal RSMP of the sampling frequency Fs (44.1kHz).
L is formed. Furthermore, a clock pulse (2
) are the phase comparator 95, the pass filter 96, and the VC
It is formed by a PLL circuit 107 consisting of an O (voltage controlled variable frequency oscillator) 97 and a frequency divider 98 with a point frequency division ratio. This clock KWC also serves as a write clock for the RAM 3l during recording, and is taken out via a NAND circuit 99. PLL circuit 107 is used to synchronize sampling signal RSMPL and clock KWC. Read clock of RAM3l during recording
Then, the output of the reference clock generator 11 is connected to the gate circuit 100.
It is formed by passing through. During playback, the horizontal synchronization signal PHD separated from the playback signal is passed through the phase comparator 101, low-pass filter 102, VCOIO3, and frequency divider 104.
horizontal synchronization signal P
Transmission lock frequency female synchronized with HD? , which is taken out through the NAND circuit 105 only during reproduction, and obtained by the write clock RWC5 of the RAM 3l. At the same time, the output of the PLL circuit 108 is supplied to the frequency divider 94 via the NAND circuits 93 and 92, so that the sampling signal P during reproduction is similar to that during recording.
An SMPL is formed, and the output of the PLL circuit 107 is supplied to a NAND circuit 106, from which a read clock for the RAM 31 and a clock repeater for converting serial data into parallel data are obtained. Here, PLL circuit 10
8 is designed to sufficiently respond to relatively fast time axis fluctuations such as jitter included in the reproduced signal, and even if the horizontal synchronization signal PHD is lost due to dropout etc.
The lock range is designed to be narrow so that the oscillation frequency of OlO3 does not deviate significantly.

On the other hand, the PLL circuit 107 is designed not to respond to time axis fluctuations in the reproduced signal, and generates a clock signal C of a constant period even during reproduction. As an example, if correction for time axis fluctuations is to be performed on components of 0.2 Hz or more, it is designed to respond only to slower components below that. Therefore, although clock realignment during reproduction may include slow time axis fluctuations of 0.2 Hz or less, no adverse effects will occur when the demodulated signal is reproduced by a speaker or the like. With the above configuration, the clock pulse generator 34 can be used both during recording and during reproduction. FIG. 7 shows a start/stop signal generator 35 that generates a start/stop signal for controlling the start and stop of writing and reading of the RAM 3l.
09, 110, 111 are binary counters connected in series. During recording, the horizontal synchronizing signal generated by the synchronizing signal generator 33 is counted by counters 109, 110, 111 via NAND circuits 112, 113, and during playback, it is counted by counters 109, 110, 111 via NAND circuits 114, 113. The reproduced composite synchronization signal PSYNC is counted by counters 109, 110, and 111. The reproduced composite synchronization signal PSYNC is a synchronization signal obtained by supplying a signal reproduced from the VTRl to the synchronization separation circuit 36 and separating it, and includes a horizontal synchronization signal and a vertical synchronization signal. Figure 8A shows the mode signal (REC or PL).
B), and B in the figure shows the counted horizontal synchronizing signal (R1I
D or PSYNC). counters 109, 110,
A predetermined output of 111 is supplied to a NAND circuit 115, and when 7 horizontal synchronizing signals are counted, the output becomes ゜"0゛, and is further passed through a waveform shaping circuit 116 to produce the output shown in Fig. 8D. A pulse shown is obtained, and this pulse is supplied to the NAND circuit 117. Also, the NAND circuit 118,
119 and 120 supply the vertical synchronization signal RSVD or PSVD shown in FIG. 8C from the synchronization separation circuit to the NAND circuit 117 during recording or reproduction. The output of the NAND circuit 117 is used as a clear input for the counters 109, 110, 111, and therefore, the counters 109, 110, 111 are cleared at the rising edge of the vertical synchronizing signal RSVD or PSVD or the rising edge of the output of the waveform shaping circuit 116.
At the same time, the vertical synchronizing signal obtained at the output of the NAND circuit 119 is inverted by the inverter and is R
When the S-type flip-flop FFL is set and the counting power of the counter 111 reaches 512, the lower flip-flop F1 is set by the fall of the output shown in FIG. The output Q becomes the window signal WND.The window signal WND defines the period of one field, as shown in the enlarged view in FIG.
The duration of the count is 1, and the remaining period of the field is 0, which defines the length of data to be processed in one field (735 blocks). During recording, the window signal WND is generally not phase-synchronized with the sampling signal RSMPL that samples the analog signal, so the window signal WND cannot be used as it is as a RAM write start/stop signal, and the signal RSMPL is changed by the D-type flip-flop DFl. Figure 9B synchronized with
The signal RWND shown in FIG.
A write start/stop signal RWG of "°1" is formed from the trailing edge (rising edge) of WND.

The read start/stop signal RRG during recording is shown in Figure 9D.
As shown in Figure 2, it is delayed by τ1 from the rising edge of the signal RWND.As shown in Figure 2, this is 3 blocks away in the case of an even field and 25 blocks away in the case of an odd field. However, the vertical synchronization signal RSVD from the synchronization separation circuit 36 is one block from the trailing edge of the actual vertical synchronization signal in the case of an even field, and 0 in the case of an odd field.
．． Since it is assumed that there is a delay of 5 blocks, τ1 is 2
Protsuku is fine. Therefore, the signal RWND is passed through the NAND circuits 121 and 122 to the D-type flip-flop DF.
3 and its output Q is supplied to the D-type flip-flop DF.
4, while these D flip-flops DF3
and a NAND circuit 124,1 as a clock input of DF4.
A horizontal synchronizing signal (m) is supplied through the D-type flip-flop DF4, and a read start/stop signal RRG at the time of recording is obtained at the output of the D-type flip-flop DF4. During playback, the window signal WND is connected to the NAND circuits 123 and 122.
The reproduced composite synchronization signal is supplied to the D-type flip-flops DF3 and DF4 via the NAND circuits 126 and 125, and is used as the clock input of these D-type flip-flops DF3 and DF4, thereby providing a write start/stop similar to that during recording. A signal PWG is formed.

The read start/stop signal PRG during reproduction is set to 66r at the same timing as the write start/stop signal PWG.
However, considering that the reproduced signal includes time axis fluctuations due to jitter, etc., the monomulti MMll is generated at the falling edge of the window signal WND passed through the NAND circuit 123. delayed by triggering,
The output thereof is supplied to a D-type flip-flop DF5 so as to be synchronized with the sampling signal PSMPL. FIG. 9E shows the read start/stop signal PRG. The start/stop signals RWG, RRG, PWG, and PRG formed as described above are transmitted to the memory control circuit 3.
2, and the start and stop of write and read operations of the RAM 3l are controlled. That is, during recording, the write start/stop signal RWG is used as the write clock RWC.
Writing is performed continuously by gating the read start/stop signal RRG, while reading is started with a delay of τ1 and the time necessary for data compression after writing is started by gating the read clock RRC using the read start/stop signal RRG. . The timing at which writing of one field's worth of data (735 blocks) ends coincides with the timing at which reading thereof ends. During playback, writing is started by gating the write clock PWC with the write start/stop signal PWG, and then the read clock PRC is activated with the read start/stop signal PRG after a time delay necessary to compensate for time axis fluctuations. Reading is initiated by gating. FIG. 10 shows a RAM and its peripheral circuits (indicated by 31 in FIG. 3) that write and read data based on the above-mentioned start-stop signal and clock pulse, and 131 is, for example, (32×32=1024
This is a static MOS/RAM (bit). Here, the capacity CA (book) required to compress or expand the time axis of data processed in units of one field, CB (block) the capacity required to correct time axis fluctuations, and the total capacity CM = ( CA+CB), then the capacity CM is nothing but what is required of the RAM.

As mentioned above, the rate at which data is written to the memory device during recording is equal to the sampling rate (44.1kHz).
The reading rate is equal to the transmission rate, F, (4
7.25kHz). However, the frequencies Fs and F are in block units. The memory device is configured so that writing and reading can be performed independently, and reading is started after 7 seconds have elapsed from when writing was started by the start/stop signals RWG and RRG mentioned above.
Since the timing at which data for 35 blocks is written is made to coincide with the timing at which reading thereof is finished, the minimum capacity CA required for time axis compression and expansion can be found using the following formula.C^=49 proc = 127
During the next 4-bit playback, the start/stop signals PWG and PR
Check the compensation range for time axis fluctuations using G.
If so, does reading start in advance? (Sec) is delayed.

As an example, approximately 12 blocks of CB are required to compensate for time axis fluctuations, so the capacity CM is CM=CA+C
B=61 blocks=1586 bits.

In one embodiment of the present invention, from the viewpoint of cost, a RAM having a long cycle time is used, and two RAMs each having 1024 bits per package are operated in parallel.
Therefore, it is necessary to convert serial data into 2-bit parallel data and write it into the RAM, and to convert the 2-bit parallel read output of R and AM into serial data. However, since this consideration is not an essential problem for the present invention, the following description will be made with respect to one RAM 13l. In FIG. 10, 132 is an X address decoder, 133 is a Y address decoder, 134 is a write circuit, and 135 is a read circuit. Data input DIN is input buffer register 1
36, it is made into data BRi synchronized with the write clock WC and is supplied to the write circuit 134. The readout output via the readout circuit 135 is supplied to an output buffer register 137, from which an output BRO is taken out in synchronization with the address selection signal ADSLCT.
Furthermore, the output data DOUT is supplied to the D flip-flop DF6 and converted to a constant rate by the read clock RC. Note that the write/read control signal WI is supplied to the write circuit 134. The memory control circuit 32 for the above-mentioned RAM 13l and its peripheral circuits has a first
As shown in FIG. 1, a memory control signal generating circuit 138 and an address code A generate address selection signals ADSLCT and ADS pressure T and a write/read control signal W from a write clock WC and a read clock RC.

-A, and an address signal generating section that generates. Here, the write clock WC is the write clock KW during recording generated by the clock pulse generator shown in FIG.
The read clock RC is obtained by supplying the write clock C during recording and the write clock C during reproduction to the NAND circuit 139, and the read clock RC is obtained by supplying the read clock C during recording and the read clock C during reproduction to the NAND circuit 141. That's what you get. In addition, in FIG. 11, 143 is the 10-bit output WAO
-Write address counter that generates WA9, 1
44 is a read address counter that generates a 10-bit output RAO-R input. During recording, a write clock WC gated by a write start/stop signal RWG is supplied to the write address counter 143 via NAND circuits 145 and 147, and a read start signal is supplied to the read address counter 144 via NAND circuits 148 and 150. A read clock RC gated by a stop signal RRG and a horizontal synchronization signal RHD is provided. The purpose of gating using the horizontal synchronizing signal RHD is to form a period in which the horizontal synchronizing signal is inserted between each block, as is clear from the recording signal waveform in FIG. During playback, the NAND circuits 146 and 14 are input to the write address counter 143.
A write clock WC gated by a write start/stop signal PWG and a composite synchronization signal PSYNC separated from the playback signal is supplied via NAND circuits 149 and 150 to the read address counter 144.
A read clock RC gated with a read start/stop signal PRG is supplied via the read start/stop signal PRG. The reason why it is gated by the composite synchronization signal PSYNC is that there is no data between the blocks of the data written to the RAM. The output of these write address counters 143 WAO-
WA9 and read address counter 144 output RAO
-RA9 is supplied to the address selector 151, and WAO to WA9 are address codes A during writing. -A9 is supplied to the address decoders 132 and 133, and at the time of reading, RAO-RA9 is supplied as an address code.
It is supplied as A9 to address decoders 132 and 133. Therefore, address selection signals ADSLCT and ADSLCT are supplied to address selector 151. Write address counter 143 and read address counter 1
44 is cleared by the standby signal STBY generated by the mode signal generator 47 mentioned above.

In other words, the standby signal STBY is the first vertical synchronization signal PSVD when the recording switch 46 is turned on and during playback.
The write address counter 143 and the read address counter 144 are cleared at each point in time. Furthermore, a memory device consisting of a RAM and a memory control circuit can be written and read independently.

This will be explained with reference to the time charts of FIGS. 12 and 13. FIG. 12 shows a time chart during recording, in which the period Tw of the write clock RWC is in the relationship (Tw>TR) with the period TR of the read clock RRC, and the time axis of the data is compressed. The figure shows the time chart during playback, and the write clock PWC.
This is a case where the period Tw of the read clock PRC has a relationship (Tw<TR) with the period TR of the read clock PRC, and the time axis is extended. However, the period Tw of the write clock RWC during playback
(has a time axis variation), the time axis variation is corrected by reading data with a read clock PRC having a constant period TR. To explain the time charts in FIGS. 12 and 13, input data D and N are input to the write clock WC (RWC or PWC) (by passing through the input buffer register 136).
Data BRi (Figure 12B or Figure 13B) synchronized with
12A or 13A).

The write address is determined by the address code WAO-W. It is determined sequentially by A9. A mark signal MARK (FIG. 12D or FIG. 13D) having a pulse width of about half the period Tw is generated in the memory control signal generation circuit 138 by the write clock WC. Also, read clock RC (RRC or PRC) (12th
Read address counter 1 according to Figure E or Figure 13E)
44, the read address is sequentially changed as shown in FIG. 12F or FIG. 13F.

In detail, as will be described later in conjunction with FIGS. 14 to 16, the write/read control signal WR shown in FIG. 12G or FIG.
A write cycle Twc is defined by adding the Al write enable pulse width Tpw. Also, the address selection signal, AD
When SLCT (FIG. 12H or FIG. 13H) is ゜“1”, the write address code is output to the address decoder 132,
The read address code is supplied to address decoders 132 and 133 at "°0", and this "0" period becomes a read cycle TRC. Then, write/read control signal WV and address selection signal ADS
Data is written into the RAM-131 bit by bit by the LCT, and data is read out bit by bit from the RAM 13l. Read using address selection signal ADSLCT
Buffer register 13 outputs data in synchronization with the rising edge of
7, and therefore its output BRO is as shown in FIG. 1 or . 13 The period becomes irregular as shown in FIG. If this continues, later data processing will be troublesome, so
D flip-flop DF6 and read clock R
The output data D of a constant period shown in FIG. 12 J or FIG. 13 J using C. Convert to lJT. RAMl like this
3l can be operated independently (asynchronously) for writing and reading. Then, the start/stop signal RWG,
By processing data in units of one field using RRG, PWG, and PRG, if the accumulated amount of time axis fluctuation exceeds the pre-estimated correction range, the next data will be processed before reading the data from RAM. An overflow for writing or an underflow for reading previous data before data is written to the RAM occurs, but as long as the correction range is not exceeded, no overflow or underflow occurs and the time axis can be compressed and expanded. The write cycle or the read cycle is determined as follows, as is clear from FIG. 12 or FIG. 13.

First, when the read clock RC comes while the mark signal MARK is ゜゜1゛, the write cycle starts with the write clock WC, and in this case, the read clock RC does not immediately enter the read cycle but yields to the write cycle. do.

Next, when the read clock RC comes when the mark signal MARK is 0.degree., the effective read cycle starts from this point. That is, in this case, the write cycle is yielded to the read cycle as much as necessary (maximum Tw). In this case, the write cycle Twc is
The time necessary for the write operation to be performed reliably is the sum of address setup time TsAl, address hold time THAl, and write enable pulse width Tpw. Further, the read cycle is set to be longer than the time required for the read operation and less than 112 Tw. Write/read control signal WR and address selection signal ADSLCT for performing such operations are generated by memory control signal generation circuit 138.

FIG. 14 shows the structure of the memory control signal generation circuit 138, where MM1 to MM5 each represent a monomultiplier, and the monomultiplier MMl is triggered at the rising edge of the write clock WC to form a mark signal MARK. The monomulti MM3 is triggered by the fall of the output Q of the monomulti MM2, and defines the writable pulse width Tpw.
The output O is taken as the signal WV. Monomulti MM4 defines address hold time THA. Mono multi M
M5 defines a read cycle T8C after the end of the write cycle Tvvc, and has a retriggerable configuration. The output η of the monomulti MM5 is the signal ADSLC
T, and the output Q is made into a signal, ADSLCT. 15 and 16 are time charts of the above-mentioned control circuit. FIG. 15 shows the time of recording, and FIG. 16 shows the time of playback. The timing is right. FIG. 15A or FIG. 16A is a write clock WC (RWC or PWC);
FIG. 15C or FIG. 16C is the read clock RC (RR).
The mark signal MARK shown in FIG. 15B or 16B is generated by triggering the monomulti MM1 by the write clock WC. Since the control circuit shown in FIG. 14 has a loop configuration, the signal W shown in FIG. 15D or FIG.
Assume that R has been obtained. At this time, monomulti M
The output Q of M3 becomes as shown in FIG. 15E or FIG. As shown in FIG. 15F or FIG. 16F, a pulse WEΔ, which is a differential pulse of the rising edge of the signal WV, appears at the output of the signal WV. Since this pulse WEΔ and signal MARK are supplied to the NAND circuit 154, its output becomes as shown in FIG. 15G or FIG. The output Q is as shown in FIG. 15H or FIG. 16H. The output Q of the monomulti MMl is supplied as it is to the OR circuit 155, and is also supplied to the OR circuit 155 via the integrating circuit and the inverter 156. Therefore, the output of the OR circuit 155 is as shown in FIG.
Or, as shown in Fig. 16, MonoMulti Mr! A pulse MM4QΔ which is obtained by differentiating the falling edge of the output Q of 44 appears. Further, the read clock RC and the signal MARK are supplied to the NAND circuit 157, and the read clock RC is output as shown in FIG. 15J or FIG. 16J when the signals M and ARK are "0". When it arrives, a negative pulse is generated.

The outputs of the OR circuit 155 and the NAND circuit 157 are supplied to the NAND circuit 158.
A pulse shown in FIG. 5K or FIG. 16K is generated, and the monomulti MM5 is triggered at the rising edge of this pulse. In this case, since the monomulti MM5 is retriggerable, its output Q, that is, the signal ADSLCT, and its output mutually, that is, the signal ADSLCT are
, M. Signal ADSLCT is supplied to NAND circuit 159 together with signal MARK, so the output of NAND circuit 159 is as shown in FIG. 15N or FIG. 16N. On the other hand, the signal ADSLCT and the clock WC are supplied to a NAND circuit 160, the output of which and the output of the NAND circuit 159 are supplied to a NAND circuit 161, and when the output falls, the monomulti MM. is triggered. By doing this, when the clock WC comes while the signal ADS level is RHJ, a write cycle starts. Mono multi MM
The output Q of 2 becomes as shown in FIG. 15 0 or 16 0, and since the mono-multiple MM 3 is triggered at its fall, the write/read control signal W shown in FIG. 15 D or FIG. will be formed. In the above-mentioned PCM-based audio signal recording and reproducing apparatus, reading is performed in advance before writing when reproducing! For example, if the time is delayed by 6 blocks and the time axis variation is within the correction range of ±6 blocks, overflow or underflow will not occur.

However, there is a possibility that a time axis variation exceeding the standard may occur, and in more cases, the accumulated time axis variation may exceed the correction range. For example, when the cycle of the write clock PWC, which is synchronized with the horizontal synchronization signal during playback, becomes shorter, the cumulative fluctuation increases, and when it exceeds a certain value, the write address catches up with the read address, and after that, an overflow occurs.Conversely, when writing When the period of the clock PWC becomes longer, the read address catches up with the write address and an underflow occurs thereafter.The present invention uses this overflow or underflow to outputs WAO to WA9 of the write address counter 143 and the outputs of the read address counter 144. It is detected by comparing the output RAO-RA9, and the content of at least one of the write address counter 143 or the read address counter 144 is set to a predetermined state based on this detection output.

FIG. 17 shows an embodiment of an overflow or underflow detector, in which 70 to 79 are exclusive OR circuits, respectively.

Exclusive OR circuits 70-79 are supplied with bits having equal weights from outputs WAO-WA9 of write address counter 143 and outputs RAO-RA9 of read address counter 144, respectively. Furthermore, the outputs of the exclusive OR circuits 70 to 79 are supplied to NOR circuits 64 to 68 two by two, and the outputs of the NOR circuits 64 to 68 are supplied to a NAND circuit 69. These logic operation circuits detect the match between WAO-WA9 and RAO-RA9, and when all the bits of both match, the NAND circuit 6 is activated.
The output of 9 becomes 6608 from 6r3, which makes it possible to detect overflow or underflow. The output of the NAND circuit 69 is supplied to a NOR circuit 80 and also to the NOR circuit 80 via an integrating circuit 81 and an inverter 82 , and the output of the NAND circuit 80 is supplied to an inverter 83 . The output of this inverter 83 is
At the time when WAO-WA9 and RAO-RA9 match, a detection pulse STBY'' having the same waveform as the standby signal STBY (FIG. 5 J) can be obtained. It is supplied together with the standby signal STBY. This AND circuit 84
The output of is the write address counter 143 and the read address counter 1 as in the case of the standby signal STBY.
44 clear input. According to this configuration, overflow or underflow is detected by the coincidence of the output W, AO-WA9 of the write address counter 143 and the output RAO-RA9 of the read address counter 144, and the detection pulse STBY' is used to detect the address. counter. is cleared and the standby signal STBY
'' is supplied to the synchronization separation circuit 36, and the vertical synchronization signal SVD
is set.

This causes the window signal WND to go low and the write and read clocks to be supplied to the write and read counters. However, the next field starts normal operation, resulting in a maximum of about one field of signal loss each time an overflow or underflow occurs. However, such short-term signal loss has almost no effect, and is not a phenomenon that occurs frequently. Furthermore, when an overflow or an underflow occurs, clearing the address counter means switching the center of the standard correction range for time axis fluctuations. That is, as shown in FIG. 18, the first period T1 (
TO-t1) is operating normally, and if an overflow occurs beyond the standard correction range +7 at t1, the playback is returned to the start state at this time, so if the correction range is centered around TAN (0 ~+CB), and the next period 12
Normal operation is performed in the range (t1 to T2). T
In No. 2, an underflow occurs and the playback is returned to the start state, returning to the standard correction range (period T3). Next, when underflow occurs at T3, the correction range is 1? (0 to -CB) (period T4). Further, when an overflow occurs at T4, the correction range returns to the standard (period T5). Since the center of the correction range is switched in this way, the correction range corresponding to +q is always maintained.
-2. I can prove it, and I'm a master from the restart!
Even if the above-mentioned time axis fluctuation occurs, signal dropouts can be made less likely to occur.

In order to reduce as much as possible the effect of signal loss when overflow or underflow occurs as described above, the code arrangement of one block is arranged starting from the MSB (most significant bit) as shown in FIG. B (least significant bit)
It is desirable that the order is as follows.

[Brief explanation of the drawing]

Fig. 1 is a system diagram of a signal recording/reproducing apparatus using the PCM method to which the present invention can be applied, Fig. 2 is a diagram showing the recorded signal waveform, and Fig. 3 is a main part of a signal recording/reproducing apparatus considering dual use for recording and reproducing. Figures 4 and 5 are the system diagram of the mode signal generator and its time chart, Figure 6 is the system diagram of the clock pulse generator, and Figures 7, 8, and 9 are the start/stop diagram. A system diagram of the signal generator and its time chart, Figure 10 is a system diagram of the RAM and its peripheral circuits, and Figure 11 is a system diagram of the signal generator and its time chart.
12 and 13 are time charts of the memory device. FIGS. 14, 15, and 16 are system diagrams of the memory control signal generation circuit and their time charts. The figure is a system diagram of one embodiment of an overflow or underflow detector, and FIGS. 18 and 19 are route diagrams used for explaining the same. 1 is a VTR, 21 is a VTR recording signal input terminal, 20 is a VTR playback signal output terminal, 31 is a RAM 32 is a memory control circuit, 33 is a synchronizing signal generator, 34 is a clock pulse generator, 35 is a start/stop signal generator vessel, 3
6 is a synchronous separation circuit, 37 is a serial/parallel converter, 46 is a recording switch, 47 is a mode signal generator, 143 is a write address counter, 144 is a read address counter, 15
1 is an address selector.

Claims (1)

[Scope of Claims] 1. A memory, a write address counter for writing data to a predetermined address of the memory in accordance with a write clock, and a time axis that is compressed or expanded in accordance with a read clock having a cycle different from that of the write clock. a read address counter to read the data from a predetermined address of the memory; an address selector that selects the outputs of the write address counter and the read address counter; and a comparison between the output of the write address counter and the output of the read address counter. and a comparison circuit that detects overflow or underflow by the comparison circuit and generates a standby signal, and the standby signal clears a write address counter and a read address counter to bring both counters to an initial state. memory device. 2. Claim 1, in which a comparator circuit detects overflow or underflow and clears a write address counter or a read address counter.
Memory devices listed in section. 3. The memory device according to claim 1 or 2, wherein the comparison circuit is constituted by a coincidence detection circuit.