JP3519824B2 - Magnetic recording / reproducing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic recording / reproducing apparatus, and more particularly to, for example, VHS-HiFi, β-HiFi,
The present invention relates to a magnetic recording / reproducing apparatus which is applied to a VTR adopting the SVHS and 8 mm video HiFi system, and which records on a magnetic tape the third audio data generated based on the first and second audio data.

[0002]

2. Description of the Related Art In the conventional VTR 1 shown in FIG.
The audio signal of the channel is F using a carrier of 1.3 MHz.
In addition to being modulated by the M modulation circuit 2, the audio signal of the second channel is modulated by the FM modulation circuit 3 using a carrier of 1.7 MHz, and the respective modulated signals are added and recorded on the magnetic tape 4. Further, at the time of reproduction, the reproduction signal from the magnetic tape 4 is supplied to a 1.3 MHz band pass filter (BP).
F) through the FM demodulation circuit 6 through 5,
The signal was demodulated by the FM demodulation circuit 8 through the BPF 7 of 1.7 MHz, and thereby the audio signals of the first channel and the second channel were output.

[0003]

However, such a conventional technique cannot record a 4-channel audio signal such as a BS broadcast or a high-definition broadcast. Also,
A method of using four types of carrier waves to record a four-channel audio signal is also conceivable, but this will affect the video signal. That is, in the VHS method, the FM audio signal jumps into the luminance signal and the chroma signal, and in the beta method, the frequency of the luminance signal needs to be shifted to a high frequency range, resulting in poor frequency characteristics.

[0004]

According to the present invention, there is provided a magnetic recording / reproducing apparatus for reproducing from a magnetic tape a composite audio signal in which plural kinds of audio signals are intermittently multiplexed by a predetermined amount at a predetermined amount. First extracting means for extracting a plurality of types of audio signals, a plurality of memory means individually assigned to a plurality of types of audio signals, and a plurality of memories for storing a plurality of types of audio signals extracted by the first extracting means at a first clock frequency Writing means for individually writing to the means, reading means for simultaneously reading a plurality of types of audio signals stored in a plurality of memory means at a second clock frequency lower than the first clock frequency, and a plurality of reading means for a plurality of memory means It is equipped with a plurality of output means for individually outputting different types of audio signals. The pilot signal is multiplexed at a rate of once in a predetermined amount, the first extracting means controls the extraction timing of the audio signal corresponding to the predetermined amount based on the pilot signal, and the writing means controls the extraction timing based on the pilot signal. The magnetic recording / reproducing apparatus is characterized in that the writing timing of an audio signal corresponding to a fixed amount is controlled.

[0005]

SUMMARY OF THE INVENTION The present invention is a magnetic recording / reproducing apparatus for recording on a magnetic tape the third audio data generated based on the first and second audio data,
First recording system memory means for accumulating first audio data,
Second recording system memory means for accumulating second audio data,
A first recording system writing means for writing the first audio data to the first recording system memory means at the first clock, and a second recording system for writing the second audio data to the second recording system memory means at the first clock. Recording system writing means, first recording system reading means for reading the written first audio data at predetermined intervals with a second clock having a frequency that is at least twice the frequency of the first clock, second audio written A second recording system reading means for reading the data at the second clock during a period in which the first audio data is not read, and the read first audio data and the second audio data are added to generate a third audio data. The magnetic recording / reproducing apparatus is provided with an adding means for generating the audio data.

[0006]

When recording, the first audio data (first channel or second channel) and the second audio data (third channel or fourth channel) are first recorded in the first and second recording systems at the first clock. The first and second audio data written in the memory means and then written are alternately read at the second clock. Then, the first and second audio data are added by the adding means, and the third audio data thus generated is recorded on the magnetic tape.

At the time of reproduction, the first and second audio data contained in the reproduced third audio data are written in the first and second reproduction system memory means at the second clock, for example. After that, the written first and second audio data are read out and output, for example, at the first clock.

[0008]

According to the present invention, the first and second audio data are once written in the first and second recording system memory means at the first clock and then alternately read at the second clock. By this, the third audio data including the first and second audio data is generated, so that the 4-channel audio data can be recorded without affecting the video signal.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0010]

EXAMPLE Referring to FIG. 1, a HiFi-V of this example.
TR10 includes noise reduction circuits 12a to 12d. The audio signals of the first channel and the third channel are given to the digital signal processing circuit 14a via the noise reduction circuits 12a and 12b, and the audio signals of the second channel and the fourth channel are supplied to the noise reduction circuit 1.
Digital signal processing circuit 14 via 2c and 12d
given to b. The audio signal processed by the digital signal processing circuits 14a and 14b is next processed by the FM modulation circuit 16
a and 16b are FM-modulated using a carrier of 1.3 MHz and 1.7 MHz, and the respective modulated signals (FM
The audio signal) is added by the adder 18. Then, the added FM audio signal is recorded on the magnetic tape 24 by the recording heads 22a and 22b through the preamplifier 20.

The FM audio signal recorded on the magnetic tape 24 in this manner is reproduced by the reproducing heads 26a and 26b and given to the terminals C1 and C2 via the preamplifiers 28a and 28b. The switch SW1 controlled by the switching signal (RFSW)
Depending on the connection status of the BPF30
a and 30b. BPF 30a and 30
b passes signals of 1.3 MHz and 1.7 MHz, respectively, and the FM audio signals passed through the respective BPFs 30a and 30b are demodulated by the FM demodulation circuits 32a and 32b. Thereafter, the demodulated signals are processed by the digital signal processing circuits 34a and 34b, respectively,
As a result, the audio signals of the first channel and the third channel are output via the noise reduction circuits 12e and 12f, and the audio signals of the second channel and the fourth channel are output via the noise reduction circuits 12g and 12h. It

The digital signal processing circuit 14a is constructed as shown in FIG. Referring to FIG. 3, the frequency doubler circuit 36
RFSW is given to the
A signal s1 obtained by multiplying by 2 is output. This signal s1 is further doubled by the doubler circuit 38, and the signal a1 obtained thereby is used as a read enable signal for the odd number memory 40.
And the memory 42 for even numbers, and the mono-multis 44 and 46 and the AND circuits 48 and 50 and NO.
And the T circuit 52. Then, the output of the monomulti 44 is given to the oscillator 54 as a reset signal, and NOT
The inverted signal / a1 from the circuit 52 is applied to the odd-numbered memory 56 and the even-numbered memory 58 as a read enable signal, and also to the mono-multi 60 and the AND circuits 62 and 66. Here, “/” means inversion. The signal s1 output from the doubler circuit 36 is also
Signal obtained by inverting by NOT circuit 65
b1 is applied as a write enable signal to odd-numbered memories 40 and 56, as well as to AND circuits 48 and 64 and AND circuit 66.

The signal c1 output from the oscillator 54 is 2.5
It is applied to the multiplication circuit 68 and AND circuits 64 and 74. The signal 2.5 is generated in the 2.5 multiplication circuit 68, and this is given to the AND circuits 48, 50, 62 and 66.
The mono-multi 46 creates a signal o1 based on the signal a1 and supplies it to the NOT circuit 70. In addition, the monomulti 60 creates the signal p1 based on the inverted signal / a1, and the NOT circuit 7
Give to 2. Then, the inverted signal / o by the NOT circuit 70
1 is applied to AND circuits 48 and 50, and an inverted signal / p1 of signal p1 by NOT circuit 72 is applied to AND circuits 62 and 66. AND circuit 74 receives signals s1 and c1 and applies signal e1 to OR circuits 76 and 78. The AND circuit 48 receives the signal a1, the signal b1, the signal d1 and the inverted signal / o1 and gives the signal f1 to the OR circuit 76.

AND circuit 64 receives signals b1 and c1 and applies signal h1 to OR circuits 80 and 82. AND
The circuit 50 includes a signal s1, a signal a1, a signal d1 and an inverted signal / o1.
In response, the signal i1 is applied to the OR circuit 80. AND circuit 6
2 receives inverted signals / p1 and / a1 and signals s1 and d1 and applies signal t1 to OR circuit 82. AND circuit 66
Receives the inverted signals / a1 and / p1 and the signals b1 and d1 and applies the signal k1 to the OR circuit 78. The OR circuit 76 receives the signal e1 and the signal f1 and gives the signal g1 as a clock to the even memory 42. The OR circuit 80 receives the signal h1 and the signal i1 and uses the signal j1 as a clock to generate the odd memory 40.
Give to. The OR circuit 82 receives the signal h1 and the signal t1 and gives the signal n1 to the odd number memory 56 as a clock. O
The R circuit 78 receives the signal e1 and the signal k1 and gives the signal m1 as a clock to the even memory 58.

Referring to FIG. 4, the audio signal of the first channel is given to A / D conversion circuit 84, and A / D conversion circuit 8 is supplied.
The voice data A1 is output from 4. The A / D conversion circuit 86 is supplied with the audio signal of the third channel,
The conversion circuit 86 outputs the audio data B1. The odd-numbered memory 40 and the even-numbered memory 42 respectively have the signal j1.
Since the signal g1 and the signal g1 are supplied as clocks, the audio data D1 is written in the odd memory 40 according to the clock j1, the write enable signal b1, and the read enable signal a1, and then the audio data F1 is output.
In the even-numbered memory 42, the audio data C1 is written and the audio data E1 is read according to the clock g1, the write enable signal s1, and the read enable signal a1.

Odd memory 56 and even memory 58
Since the signal n1 and the signal m1 are applied as clocks to the odd number memory 56, the audio data H1 is written to the odd number memory 56 according to the clock n1 and the write enable signal and the read enable signal, and then the audio data J1 is read. In the even-numbered memory 58, the audio data G1 is written and the audio data I1 is read according to the signal m1, the write enable signal, and the read enable signal. The odd-numbered memories 40 and 56 and the even-numbered memories 42 and 58 are preferentially written. The audio data F1 and E1 read from the odd-numbered memory 40 and the even-numbered memory 42 are processed by the OR circuit 86, whereby the OR circuit 86 outputs the audio data K1. Also, the odd memory 56 and the even memory 5
The voice data J1 and I1 output from 8 are OR circuits 88.
And the audio data L1 is output.

Referring to FIG. 5, monomultis 46 and 6
The signal o1 and the signal p1 output from 0 are given to the monomulti 94 through the OR circuit 92. Therefore, the signal q1 is output from the mono-multi 94 and the mono-multi 9
6 receives the signal q1 and outputs the signal r1. This signal r1 and the frequency signal output from the oscillator 98 are AND circuit 10
After being processed by 0, the pilot signal is given to the OR circuit 102. On the other hand, the audio data output from the OR circuit 90 is supplied to the OR circuit 102 after being converted into an analog audio signal by the D / A conversion circuit 104. Therefore, the OR circuit 102 outputs the signal M1, which is F
It is given to the M modulation circuit 16a.

The digital signal processing circuit 14b is
Since the digital signal processing circuit 14a is similar to the digital signal processing circuit 14a except that it receives the audio signals of the second and third channels, duplicated description will be omitted. The digital signal processing circuit 34a is configured as shown in FIG. Referring to FIG. 7, the audio data A2 demodulated by the FM demodulation circuit 32a is
The pilot signal is given to the BPF 106,
m2 is extracted. This pilot signal is then compared with a reference value in the comparator 108, whereby the counter 1
A pulse n2 is applied to 10. The counter 110 is a loop counter having a count number of “3”, resets itself when three pulses are input, and gives a reset pulse p2 to the oscillator 112 and the counter 114.
Therefore, the oscillator 112 outputs the signal q2, which is
It is given to the ND circuit 116 and the counter 114. The counter 114 outputs a high level signal when n ≦ count value ≦ N, and gives it to the AND circuit 116. By this, A
The signal r2 shown in FIG. 8 is output from the ND circuit 116.

Referring to FIG. 8, the doubler circuit 118 has an R
FSW is given, and the doubler circuit 118 receives the signal s2 obtained by multiplying RFSW by two, the doubler circuit 120, the NOT circuit 124,
It is given to the AND circuits 122, 126 and 128 and also given to the even number memory 130 as a read enable signal. The doubler circuit 120 is a signal a2 obtained by multiplying the signal s2 by two.
Is given to the NOT circuit 132, the mono-multi circuit 134, and the AND circuit 136. The AND circuit 122 receives the signal s2 and the signal a2 and supplies the signal b2 to the AND circuit 138 and the write enable signal to the odd memory 140. The AND circuit 136 receives the inverted signal / s2 and the signal a2 and supplies the signal c2 to the AND circuit 142 and the write enable signal to the even memory 130.
The AND circuit 144 receives the inversion signal / a2 and the inversion signal / s2, creates the signal d2, and supplies the signal d2 to the AND circuit 146 and the write enable signal to the even-numbered memory 148. The AND circuit 128 receives the inverted signal / a2 and the signal s2, gives the signal e2 to the AND circuit 150, and outputs the odd number memory 1 as the write enable signal.
Give to 52.

The AND circuit 126 receives the oscillation frequency signal and the signal s2 from the oscillator 154 which operates according to the reset signal from the monomulti 134, and outputs the signal f2 from the OR circuit 1
56 and 158. The AND circuit 160 receives the inverted signal / s2 and the frequency signal from the oscillator 154,
Signal g2 is applied to OR circuits 162 and 164. AND
The circuit 138 receives the signal b2 and the signal r2 and ORs the signal h2.
This is given to the circuit 162. The AND circuit 150 receives the signal e2 and the signal b2 , supplies the signal j2 to the OR circuit 164, and
The circuit 146 receives the signal d2 and the signal b2 and ORs the signal k2.
This is given to the circuit 158. As a result, the OR circuit 162 gives the OR signal of the signal g2 and the signal h2 as a clock to the odd memory 140, and the OR circuit 156 gives the OR signal of the signal i2 and the signal f2 to the even memory 130 as a clock. Further, the OR circuit 164 gives the OR signal of the signal j2 and the signal g2 to the odd memory 152 as a clock,
The OR circuit 158 supplies the even signal memory 148 with the OR signal of the signal k2 and the signal f2 as a clock.

The odd-numbered memories 140 and 152 and the even-numbered memories 130 and 148 receive the write enable signal, the read enable signal, and the clock as described above, so that the low pass filter (LPF) 16 is provided.
5 removes pilot signal and A / D converter 167
The voice data B2 (FIG. 9) converted into digital form is processed. That is, referring to FIG. 9, the odd memory 140
Is the write enable signal b2 and the signal h2 included in the clock
The audio data C2 is written in response to the read enable signal / s2 and the audio data D2 is output in response to the read enable signal / s2 and the signal g2 included in the clock. The even memory 130 receives the write enable signal c2 and the signal i2 included in the clock to write the audio data E2, and receives the read enable signal s2 and the signal f2 included in the clock to read the audio data F2. The odd number memory 152 is a write enable signal
e2 and voice data by receiving the signal j2 included in the clock
Write G2, receive read enable signal / s2 and signal g2 included in the clock, and output audio data H2.
The even memory 148 receives the write enable signal d2 and the signal k2 included in the clock, writes the audio data I2, and reads the read enable signal s2 and the signal included in the clock.
Upon receiving f2, the audio data J2 is read.

The audio data D2 and F2 output from the odd memory 140 and the even memory 130 are
After passing through the OR circuit 166, it is converted into an analog audio signal by the D / A conversion circuit 168, and then output as an audio signal of the first channel. Also, the audio data H2 and J2 output from the odd memory 152 and the even memory 148
Is converted into an analog audio signal by the D / A converter 172 via the OR circuit 170, and then output as an audio signal of the third channel. The digital signal processing circuit 3
4b receives the demodulation signal from the FM demodulation circuit 32b
Outputs the audio signal of the channel and the fourth channel,
Since the digital signal processing circuit 34b has the same configuration as the digital signal processing circuit 34a, duplicate description will be omitted.

By configuring the VTR 10 in this way, at the time of recording, the audio data C1 and D1 of the first channel are written in the even memory 42 and the odd memory 40 as shown in FIG. E1 and F1 are read from each. The audio data G1 and H1 of the third channel are written in the even-numbered memory 58 and the odd-numbered memory 56, and thereafter, the audio data I1 and J1 are read from each. Then, the signal M1 shown in FIG. 5 in which the respective audio data and the pilot signal are mixed
Is read from the digital signal processing circuit 14a,
It is modulated by the modulation circuit 16a. After that, this modulated signal is added to the modulated signals for the second and fourth channels output from the FM modulation circuit 16b by the adder 18, and the output of the adder 18 is recorded on the magnetic tape 24.

During reproduction, the audio signal demodulated by the FM demodulation circuit 32a via the BPF 30a is converted into audio data by the A / D converter 167 included in the digital signal processing circuit 34a.
Converted to B2. Then, the audio data C2 and E2 are written in the odd memory 140 and the even memory 130, and then the audio data D2 and F2 are read from each. In addition, voice data G2 and I2 are odd memory 1
52 and the even-numbered memory 148, and then the audio data H2 and J2 are read from each. Then, the audio data D2 and F2 are mixed and converted into an analog signal, and then output as the audio signal of the first channel. The audio data H2 and J2 are mixed and converted into an analog signal, which is then output as an audio signal of the third channel. The audio signal demodulated by the FM demodulation circuit 32b via the BPF 30b is also processed by the digital signal processing circuit 34.
The same processing is performed in b, and thereby the audio signals of the second channel and the fourth channel are output.

According to this embodiment, since the 4-channel audio signal is compressed into the 2-channel audio signal, the 4-channel audio signal can be recorded on the magnetic tape without affecting the video signal. Also, by expanding the audio signal recorded in this way, it can be output in four channels. In addition, this invention is VHS-Hi.
Fi, β-HiFi, SVHS and H of 8 mm video
It can be applied to a VTR that employs the iFi system.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a part of FIG. 1 embodiment.

FIG. 3 is a timing chart showing a part of the operation of the embodiment in FIG.

FIG. 4 is a timing chart showing a part of the operation of the embodiment in FIG.

5 is a timing chart showing a part of the operation of the embodiment in FIG.

FIG. 6 is a block diagram showing another part of the embodiment shown in FIG. 1;

FIG. 7 is a timing chart showing a part of the operation of FIG. 1 embodiment.

FIG. 8 is a timing chart showing a part of the operation of the embodiment in FIG.

FIG. 9 is a timing chart showing a part of the operation of the embodiment in FIG.

FIG. 10 is a block diagram showing a conventional technique.

[Explanation of symbols]

10 ... VTR 14a, 14b, 34a, 34b ... Digital signal processing circuit 16a, 16b ... FM modulation circuit 32a, 32b ... FM demodulation circuit

Claims (2)

(57) [Claims] 1. A composite audio signal in which plural kinds of audio signals are intermittently multiplexed by a predetermined amount each is reproduced from a magnetic tape .
In a magnetic recording / reproducing apparatus, first extracting means for extracting the plurality of types of audio signals from the composite audio signal, a plurality of memory means individually assigned to the plurality of types of audio signals, and extracted by the first extracting means. Writing means for individually writing the plurality of types of audio signals to the plurality of memory means at a first clock frequency; and a plurality of writing means for writing the plurality of types of audio signals stored in the plurality of memory means lower than the first clock frequency. A read means for simultaneously reading out at two clock frequencies, and a plurality of output means for individually outputting the plurality of types of audio signals read by the plurality of memory means are provided, and the composite audio signal includes the plurality of types of audio signals. The pilot signals are multiplexed at different timings and once in the predetermined amount, and the first extracting unit has The extraction timing of the audio signal corresponding to the predetermined amount is controlled based on the pilot signal, and the writing unit controls the writing timing of the audio signal corresponding to the predetermined amount based on the pilot signal. , Magnetic recording / reproducing apparatus. 2. The apparatus further comprises second extracting means for extracting the pilot signal from the composite voice signal, wherein the first extracting means determines the extraction timing based on the latest pilot signal extracted by the second extracting means. 2. The magnetic recording / reproducing apparatus according to claim 1, wherein the writing unit controls the writing timing based on the latest pilot signal extracted by the second extracting unit.