JP2828158B2 - Signal reproducing apparatus and signal recording / reproducing apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal reproducing apparatus and a signal recording / reproducing apparatus.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram for explaining a main part of an audio signal system of a conventional magnetic recording / reproducing apparatus, FIG. 9 is a block diagram for explaining an example of a conventional interpolation circuit, and FIG.
Is a timing chart of FIG. 9, FIG. 11 is a block diagram for explaining another example of the conventional interpolation circuit, and FIG.
6 is a timing chart of FIG. Hereinafter, a conventional technique will be described with reference to the drawings.

In a recent home video signal magnetic recording / reproducing apparatus (hereinafter abbreviated as "VTR"), an FM-modulated audio signal is pre-recorded on a deep portion of a magnetic tape,
An FM-modulated video signal is subsequently recorded in the upper layer. Such a conventional VTR audio signal system will be described with reference to FIG.

[0004] From a transmission line (not shown), the first and second input audio signals aa and bb of a set of R and L channels are sent to the first and second channels.
Are supplied to recording audio signal processing circuits 1 and 2, respectively, where the signals obtained by performing recording processing such as predetermined noise reduction and pre-emphasis are subjected to predetermined FM modulation.
First and second FM modulated signals 3a and 4a are obtained via second FM modulators 3 and 4, respectively. The first and second FM modulated signals 3a and 4a are, for example, 1.7 MHz and 1.3 MHz.
Each occupies a deviation of 150 KHz with z as the center frequency. Then, these signals are frequency-multiplexed by the addition circuit 5 and then amplified by the recording amplifier 6 to a predetermined level to obtain the recording audio signal 6a.

[0005] The recording audio signal 6a is supplied to a REC terminal in the first and second switch circuits SW1 and SW2.
The first and second switch circuits SW1 and SW2 are switched between recording and reproduction, and in the former case, the movable piece is RE.
In the latter case, the movable piece is connected to the PB terminal. And these output signals are the first and second
Are recorded on the magnetic tape T via the magnetic heads H1 and H2. The magnetic tape T is wound 180 degrees or more around a rotating drum on which the magnetic heads H1 and H2 are arranged to face each other, and records the recording audio signal 6a in an overlapping manner. At the time of reproduction, the magnetic heads H1, H
2, the signals reproduced from the magnetic tape T are supplied to the preamplifiers 7 and 8 via the first and second switch circuits SW1 and SW2, respectively, and are amplified to a predetermined level to obtain the first and second signals. Are supplied to the third switch circuit SW3. Then, based on a selection signal SP with a duty of 50% synchronized with the rotation cycle of the rotating drum supplied from the SW pulse generation circuit 9, these signals are selected and supplied to the first and second BPFs 10 and 11. . The circuit subsequent to the first BPF 10 is for the R channel, while the circuit subsequent to the second BPF 11 is for the L channel.

The first and second BPFs 10 and 11 extract signals corresponding to the bands of the first and second FM modulated signals 3a and 4a, respectively, and demodulate these signals into first and second FM demodulations. Demodulated by the demodulators 12 and 13 and the first and second reproduced signals 12a and 12a
3a has been obtained. These signals are supplied to first and second interpolation circuits 14 and 15 for removing switching noise caused by discontinuity of the FM reproduction signal generated by the switching operation of the third switch circuit SW3. Note that these circuits are supplied with a first interpolation timing signal 18a, which is at a low level only for a predetermined period from the timing of the rising and falling edges of the selection signal SP, from the mono-multi 18.

Then, the first and second interpolation circuit output signals 1
4a and 15a are first and second reproduced audio signal processing circuits 1
Predetermined reproduction processes such as day emphasis and noise reduction are performed in 6, 17 and are output as first and second output audio signals cc and dd for the R and L channels to a transmission path (not shown).

Here, the first and second interpolation circuits 14,
15 will be described in detail with reference to FIGS.
Since the first and second interpolation circuits 14 and 15 have the same configuration, only the first interpolation circuit 14 will be described here.

In FIG. 9, a first reproduction signal 12a on which switching noise is superimposed by a first FM demodulator 12 is shown.
(Shown in FIG. 10 (A)) is converted into a low impedance output by the buffer amplifier 20 and the fourth switch circuit SW
4 is supplied. This fourth switch circuit SW4 is shown in FIG.
The signal is controlled by an interpolation timing signal 18a shown at 0 (B), and only when this signal is at a high level, the movable piece and the contact are connected to charge the output signal of the buffer amplifier 20 to the hold capacitor 25 and supply it to the buffer amplifier 21. I do. Therefore, the output signal of the buffer amplifier 20 is held during the low-level period T1 in FIG.
5, and the switching noise is removed.

The output of the buffer amplifier 21 is a first interpolation circuit output signal 14a (shown in FIG. 2C).
The signal is output to the first reproduction signal processing circuit 16 and supplied to the inclination prediction circuit 22. Here, the prediction signal 22a shown in FIG. 3D obtained by differentiating the first interpolation circuit output signal 14a and advancing the phase is supplied to the delay circuit 24 via the voltage-current conversion circuit 23. The delay circuit 24 supplies a hold capacitor 25 with a delay signal 24a shown in FIG. During the period when the interpolation timing signal 18a is at the high level, the fourth switch circuit SW4 is in the connected state, and the impedance at the connection point Z has a low impedance equal to the output impedance of the buffer amplifier 21, so that the delay is delayed by the hold capacitor 25. The charge of the signal 24a is stored during the period T1 in which the switching noise exists. Therefore,
The waveform of the current supplied to the hold capacitor 25 in relation to the delay signal 24a is as shown in FIG.

In this manner, a feedback loop is formed only during a period in which switching noise is present, and interpolation is performed using a signal based on the prediction signal 22a instead of switching noise.

Next, another example of the first interpolation circuit 14 will be described with reference to FIGS. 11 and 12. In FIG. 11, the first FM demodulator 12 superimposes the switching noise from the first FM demodulator 12. The reproduction signal 12a is supplied to a first sample hold circuit 30 (shown in FIG. 11A), and a signal obtained by holding the interpolation timing signal 18a shown in FIG. Adder 35
To supply. Then, the first sample and hold circuit 30
Are supplied to the positive and negative inputs of the error detection amplifier 32, respectively, and the error signal obtained by detecting the difference is supplied to the second sample and hold circuit 33.

The second sample and hold circuit 33 has a second interpolation timing signal which is low from the first timing generation circuit 31 only during the period T1 / 2 immediately after the rising edge of the first interpolation timing signal 18a. 3
1a (shown in FIG. 7F) is supplied, and during this low-level period, the error signal is held, and h shown in FIG.
Is obtained. Then, based on the potential difference h and the second interpolation timing signal 31a, the pulse generation circuit 34 generates an interpolation signal 34a shown in FIG. 3C, and the interpolation signal 34a and the first sample hold circuit 30
Are added by an adder circuit 35 to obtain a signal shown in FIG. Then, a first interpolation circuit output signal 14a obtained by passing this signal through a low-pass filter (not shown) is supplied to a first reproduced sound processing circuit 16.

In this manner, the potential immediately before the start of the switching noise is held, and immediately after the end, the potential difference between the potential immediately after the end and the potential immediately before the start with a pulse width of ホ ー ル ド of the hold period is regarded as the pulse potential. The interpolation noise 34a to be added is configured to be added, and the switching noise is interpolated by making the area α and the area β substantially equal in FIG.

[0015]

However, in one example of the conventional first and second interpolation circuits 14 and 15,
The inclination prediction circuit 22 is constituted by a differentiating circuit and a prediction signal 22a
, The prediction signal 22a is obtained by emphasizing a high-frequency noise component. On the other hand, in another example, an error occurs when the switching noise occurrence position deviates from the zero cross of the audio signal. In particular, when the switching noise occurs near the peak of the audio signal, the interpolation signal is generated as shown in FIG. There was a problem because it could not be obtained at all.

Therefore, the present invention forcibly generates switching noise near the zero cross of the audio signal, and further, when there is no zero cross during the signal overlap period, attenuates the prediction signal to improve the quality of the reproduced audio signal. The purpose is to:

[0017]

SUMMARY OF THE INVENTION The present invention provides the following structure to solve the above problems.

[0018]

[0019]

A signal reproducing apparatus for reproducing a continuous signal by integrating a plurality of divided reproduced signals obtained by sequentially reproducing a recording medium in which a plurality of divided recording signals obtained by modulating and dividing a continuous signal are overlap-recorded. Selecting means for switching the plurality of divided reproduction signals within an overlap period to output a selected output signal, and selecting a plurality of the demodulated signals based on an average level of the demodulated signal obtained by demodulating the selected output signal. Zero-cross detection means for detecting the zero-cross timing of
A zero-cross timing identifying means for identifying one of the plurality of zero-cross timings obtained by the zero-cross detecting means, and an interpolation amount corresponding to a detection result of the inclination of the demodulated signal being variable with the one zero-cross timing Interpolating means for interpolating the switching noise generated in the demodulated signal, and when the one zero-cross timing is within the overlap period, the selecting means selects the plurality of signals at the one zero-cross timing. While switching and selecting the reproduction signal, the interpolation means interpolates the noise based on the one zero-cross timing. On the other hand, when the one zero-cross timing is not within the overlap period,
A signal reproducing apparatus, wherein the plurality of reproduction signals are switched and selected at a timing within the overlap period, and the interpolation means attenuates the interpolation amount.

A recording system for overlappingly recording a plurality of divided recording signals obtained by modulating and dividing a continuous signal on a recording medium;
A reproduction system for reproducing the continuous signal by integrating a plurality of divided reproduction signals obtained by sequentially reproducing the recording medium, wherein the plurality of divided reproduction signals are transmitted within an overlap period. Selecting means for switching and outputting the selected output signal, zero-cross detecting means for detecting a plurality of zero-cross timings of the demodulated signal based on the average value level of the demodulated signal obtained by demodulating the selected output signal, and the zero-cross detecting means A zero-cross timing specifying means for specifying one of the plurality of zero-cross timings obtained by the method; and an interpolating amount corresponding to the detection result of the slope of the demodulated signal being varied at the one zero-cross timing. Interpolating means for interpolating the switching noise generated in the signal, the one zero-cross timing being within the overlap period. In this case, the selecting means switches and selects the plurality of reproduction signals at the one zero cross timing, and the interpolation means interpolates noise based on the one zero cross timing, while the one zero cross timing is A signal recording / reproducing apparatus characterized in that, when it is not within the overlap period, the plurality of reproduction signals are switched and selected at the timing within the overlap period, and the interpolation means attenuates the interpolation amount.

[0022]

FIG. 1 is a block diagram for explaining a main part of an audio signal system of a magnetic recording and reproducing apparatus according to a first embodiment of the present invention. FIGS. 2 and 3 are timing charts of FIG.
FIG. 5 is a block diagram for explaining a main part of an audio signal system of a magnetic recording / reproducing apparatus according to a second embodiment of the present invention, FIG. 5 is a timing chart of FIG. 4, and FIG. 6 is first and second interpolation circuits. FIG. 7 is a block diagram for explaining a main part of an audio signal system of a magnetic recording and reproducing apparatus according to a third embodiment of the present invention. The first embodiment will be described below in order with reference to the drawings. Note that the same components as those in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted.

[First Embodiment] The configuration of FIG. 1 is different from the configuration of FIG. 8 in that the switching of the magnetic head is performed independently in the reproduction system for the R channel and the reproduction system for the L channel. The fifth switch circuit SW5 and the sixth switch circuit SW6 are provided in place of the conventional third switch circuit SW3, and a zero-cross detecting means B and a zero-cross detector for forcibly generating switching noise near the zero-cross of the audio signal. The point is that timing specifying means A is newly provided. Hereinafter, the differences will be described in detail with reference to FIGS. Since the reproduction system for the R channel and the reproduction system for the L channel have the same configuration, only the former will be described. The recording system of the audio signal is the same as that of the above-described conventional technology, and the description thereof is omitted.

In FIG. 1, the first and second preamplifiers 7 and 8 shown in FIG.
Are selected by the fifth switch circuit SW5 to obtain the output signal shown in FIG. Since the phase of this signal is discontinuous at the switching timing as shown in the figure, the first reproduced signal 12a obtained by demodulating the signal is a signal on which switching noise is superimposed as shown in FIG. In addition, FIG.
T2 is the first and second preamplifier output signals 7a and 8a.
Is an overlap period, which is a period of about 500 μsec.

FIG. 3A is an enlarged view of the time axis of FIG. 3D. This signal is supplied to the positive input of the hysteresis comparator 40 in the zero-cross detecting means B, and the resistance 41 is connected. One end is supplied to a negative input connected to the other end of the capacitor 42 whose one end is grounded. The first reproduced signal 12a is formed by the resistor 41 and the capacitor 42.
Is integrated, the average value is supplied to the negative input. As a result, the first input is supplied to the hysteresis comparator 40.
Of the reproduced signal 12a of FIG.
A zero cross detection signal 40a shown in FIG.

Then, the zero-crossing detection signal 40a is supplied to the edge extraction circuit 44 in the zero-crossing timing specifying means A, where the rising edge of the zero-crossing detection signal 40a is detected.
An output signal shown in FIG. 9C obtained by detecting the falling edge is supplied to the input of the OR circuit 45. Incidentally, the zero-cross timing specifying means A outputs the first and second preamplifier output signals 7a, 8a of the plurality of zero-cross timings.
Are used to specify one zero-cross timing during a period in which they overlap each other.

On the other hand, the switching pulse generating circuit 9 shown in FIG.
(Illustrated in (D)) is supplied to the mono-multi 43, where approximately 20 are synchronized with the rising and falling edges of the selection signal SP.
A signal 43a shown in FIG. 7E which is at a low level for a period of 0 μsec is obtained and supplied to the input of the OR circuit 45. The low-level period of the signal 43a is a part of the overlap period of the first and second preamplifier output signals 7a and 8a, and the amplitudes of the first and second preamplifier output signals 7a and 8a are sufficiently large. The central time of the overlap period and the signal 43
The center time of the low-level period of “a” is set so as to substantially coincide with the center time.

Further, the signal 43a is supplied to the OR circuit 45.
Is a high level for a period substantially equal to the low level period, the signal shown in FIG.
7 is supplied as a masking signal 47a, and is ORed with the above-mentioned signal to obtain a logical sum signal 4 shown in FIG.
5a is obtained and supplied to the clock terminal of the D flip-flop 46.

The D flip-flop 46 operates to invert in synchronization with the rising edge of the OR signal 45a to obtain the second selection signal 46a shown in FIG. Here, the rising edge of the OR signal 45a is the first edge.
Since the first reproduction signal 12a first coincides with the zero-cross timing after the edge of the selection signal
The generation of the switching noise can be near the zero cross. Even if the first reproduced signal 12a does not cross zero and the output signal of the edge extraction circuit 44 has no pulse, the second selection signal 46a is inverted at the rising edge of the monomulti 43, so The first and second preamplifier output signals 7a and 8a are selected.

Then, the second selection signal 46a is supplied to the second timing generation circuit 47, where the second selection signal 46a is shown in FIG.
The hold signal 47b, which is at a low level for a period of about 15 μsec, is supplied to the first interpolation circuit 14.

Here, when the first interpolation circuit 14 has the configuration shown in FIG. 9, the hold signal 47b is supplied to the fourth switch circuit SW4, and the switching noise is removed by the above-described operation. One interpolator output signal 14a is obtained and supplied to the first reproduced audio signal processing circuit 16.

On the other hand, when the first interpolation circuit 14 has the configuration shown in FIG. 11, the hold signal 47b is supplied to the first sample and hold circuit 30 and the first timing generation circuit 31, and The first interpolator output signal 14a from which switching noise has been removed by the operation is obtained and supplied to the first reproduced audio signal processing circuit 16. In this way, the position where the switching noise is generated can be forcibly set near the zero crossing of the audio signal. As a result,
When the first interpolation circuit 14 has the configuration shown in FIG. 9, the differentiation of the slope prediction circuit 22 can be stopped at a relatively low frequency. Interpolation is performed using an interpolation signal that is not affected by the so-called increasing triangular noise, so that the quality of the output audio signal can be improved.

On the other hand, when the first interpolation circuit 14 has the configuration shown in FIG.
Since the area α of the signal loss due to 0 and the area β of the interpolation signal can be made substantially equal, the quality of the output audio signal can be improved.

In the embodiment described above, a band-pass filter that passes a band of 2 KHz to 20 KHz is interposed between the connection point X and the connection point Y in FIG. Signal is superimposed for approximately 200 μsec
Even if the zero crossing does not occur during the period, the switching noise can be forcibly generated at the average value of the high frequency signal, so that the quality of the output audio signal can be improved.

In the above-described embodiment, the audio signal is described as an example, but the input signal may be a continuous signal such as a video signal.

[Second Embodiment] In the first embodiment, the quality of the output audio signal is improved by forcibly setting the position where the switching noise occurs near the zero crossing of the audio signal. However, when there is no zero crossing during the overlap period, the gradient prediction performed in the first and second interpolation circuits 14 and 15 is continuously performed by the first differentiation, so that the interpolation error increases and the S / N of the reproduced audio signal is reduced. There is a risk of deterioration. Therefore, in the second embodiment, when there is no zero cross in the overlap period, the prediction signal is attenuated.

FIG. 4 differs from FIG. 1 in that an interpolation control signal for detecting the presence or absence of a zero crossing in the overlap period and controlling the prediction signal 22a in the first and second interpolation circuits 14 'and 15'. The point at which the generating means C is newly provided, and then the first and second interpolation circuits 14 'in which the outputs of the inclination prediction circuits in the first and second interpolation circuits 14 and 15 can be controlled by the interpolation control signal 54a. , 15 ′, and finally, the selection signal SP is directly supplied to the data terminal of the D flip-flop 46. The last difference is merely an example for specifying the position of the first zero cross when a plurality of zero crosses occur in the overlap period, and is not an essential difference from the first embodiment. .

The operation of the interpolation control signal generating means C will be described in detail with reference to FIG. The selection signal SP shown in FIG. 9A is supplied to the AND circuit 49 and also to the mono-multi 43 in the configuration B, where the signal 43a which becomes a low level during a part of the overlap period is provided. Generate The signal 48a obtained by inverting the signal 43a by the inverting circuit 48
(Shown in FIG. 2B) to the exclusive OR circuit 50 and the AND circuit 49.

The other input of the exclusive OR circuit 50 is supplied with a rising or falling edge at the timing when there is a zero crossing during a period when the signal 48a is at a high level. The signal 46a shown in FIG. 4C is supplied after the signal 48a is delayed by a high-level period (200 μsec). Here, the timings t1 and t2 shown in FIG.
8a is a case where there is a zero cross during the high level period, while timings t3 and t4 are cases where there is no zero cross.

The selection signal S is output from the AND circuit 49.
A signal 49a shown in FIG. 3D obtained by obtaining the logical product of P, the signal 48a, and the signal 46a is supplied to one input of the logical sum circuit 52. In this manner, when the signal 48a after the rising edge of the selection signal SP has a zero-cross period in one input of the OR circuit 52, the input is synchronized with the zero-cross timing and is at a high level for a predetermined period. A signal 49a is provided.

The output of the exclusive OR circuit 50 is a signal 50a shown in FIG. 7E, and the signal 50a shown in FIG. The signal 51a obtained by obtaining the logical product of the logical product 53a and the logical product circuit 51 is supplied to the other input of the logical sum circuit 52. In this way, when the other input of the OR circuit 52 has a zero cross during the period in which the signal 48a after the falling edge of the selection signal SP is at the high level, the other input is synchronized with the zero cross timing and set to the high level for a predetermined period. Is supplied.

Then, the logical sum of the signal 49a and the signal 51a is added to the signal 52a shown in FIG.
a. During the period when the signal 52a is at the high level, the signal 4a starts from the rising or falling edge of the signal 46a.
Since the period up to the falling edge of the signal 8a occurs, if the zero-cross timing occurs immediately before the end of the high-level period of the signal 48a, the pulse width of the signal 52a becomes narrower and the control of the first and second interpolation circuits described later is performed. May not be performed sufficiently. Thus, the signal 52a is supplied to the pulse width expansion circuit 54, where the pulse width of the signal 52a is expanded at least to ensure control during the interpolation period (15 μsec). Specifically, the pulse width expansion circuit 54 integrates the falling edge of the signal 52a, and is composed of, for example, a diode, a resistor, a capacitor, and the like as shown in FIG. ) Is generated. The interpolator control signal 54a thus obtained and the hold signal 47b shown in FIG.
5 '.

Here, the first and second interpolation circuits 14 'and 15' will be described with reference to FIG. Configuration 14 of the first embodiment,
15 is different from the switch circuit composed of the transistors Tr1 and Tr2 and the resistors R2 to R4 in that the capacitor C
And a resistor R1 between the slope prediction circuit 22 and the voltage-current conversion circuit 23.
And a filter circuit including a capacitor C is interposed.

Since this switch circuit is in the connected state during the period when the interpolation control signal 54a is at the low level, if there is no zero crossing during a part of the overlap period (the high level period of the signal 48a), the prediction signal Reference numeral 22a denotes a signal from which the high frequency component of the output signal of the inclination prediction circuit 22 has been removed by the filter circuit.

On the other hand, this switch circuit operates the interpolation control signal 5
Since the filter 4a is in the released state during the high-level period and the filter circuit is not configured, the prediction signal 22a becomes the output signal of the inclination prediction circuit 22 when there is a zero crossing in a part of the overlap period.

As described above, since the frequency characteristic of the prediction signal is varied depending on the presence or absence of a zero cross during a part of the overlap period, when the zero cross does not exist during a part of the overlap period, Interpolation can be performed without increasing the interpolation error. If there is no zero cross, it is only necessary to attenuate the output signal of the inclination prediction circuit 22, so that the filter circuit may be omitted and only the switch circuit may be used.

[Third Embodiment] In the above-described second embodiment, the zero-crossing specifying means A and the interpolation control generating means C are configured as the Lch system and the configuration 1 related to the configurations 10, 12, 14 'and the like.
Rch systems 1, 13, and 15 ', respectively, but are simplified in the third embodiment.

That is, as shown in FIG. 7, in the Rch system, zero-crossing specifying means A other than the edge extracting circuit is used.
And the interpolation control generating means C is shared to reduce the circuit scale.

Since the interpolation error of the switching noise is most noticeable in the auditory sense when the L and R channels are the same single frequency signal, the third embodiment is further simplified, and the zero-cross specifying means A and the zero-cross detection are performed. The means B and the interpolation control generating means C may be shared by the L and Rch systems.

[0050]

As described above, according to the configuration of the present invention,
Since a plurality of divided reproduction signals are switched and selected at one of the plurality of zero cross timings detected by the zero cross detection means, switching noise generated at the time of switching selection is forcibly generated near the zero cross of the demodulated signal. In addition, in order to interpolate and remove noise based on the one zero cross timing,
Since high frequency noise can be suppressed or interpolation accuracy can be improved,
There is an effect that the quality of the output signal can be improved.

Further , according to the configuration of the present invention, interpolating means for interpolating the switching noise generated in the demodulated signal by changing the interpolation amount according to the detection result of the inclination of the demodulated signal at one zero cross timing. Therefore, even if there is no zero crossing within the overlap period, interpolation can be performed without increasing the interpolation error, and the quality of the output signal can be further improved.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a main part of an audio signal system of a magnetic recording and reproducing apparatus according to a first embodiment of the present invention.

FIG. 2 is a timing chart of FIG.

FIG. 3 is a timing chart of FIG.

FIG. 4 is a block diagram for explaining a main part of an audio signal system of a magnetic recording and reproducing apparatus according to a second embodiment of the present invention.

FIG. 5 is a timing chart of FIG.

FIG. 6 is a block diagram of first and second interpolation circuits;

FIG. 7 is a block diagram for explaining a main part of an audio signal system of a magnetic recording and reproducing apparatus according to a third embodiment of the present invention.

FIG. 8 is a block diagram for explaining a main part of an audio signal system of a conventional magnetic recording / reproducing apparatus.

FIG. 9 is a block diagram illustrating an example of a conventional interpolation circuit.

FIG. 10 is a timing chart of FIG.

FIG. 11 is a block diagram for explaining another example of a conventional interpolation circuit.

FIG. 12 is a timing chart of FIG.

[Description of Signs] 14, 14 ', 15, 15' First and second interpolation circuits (interpolation means) 7a, 8a First and second preamplifier output signals (split reproduction signals) 12a, 13a First, second 2 reproduction signal (demodulation signal) A zero-cross detecting means B zero-cross timing specifying means T magnetic tape (recording medium) SW5, SW6 selecting means

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11B 20/06 G11B 20/02 H04N 5/93 G11B 5/027

Claims (2)

(57) [Claims] A signal for reproducing a continuous signal by integrating a plurality of divided reproduction signals obtained by sequentially reproducing a recording medium in which a plurality of divided recording signals obtained by modulating and dividing a continuous signal are overlap-recorded. A reproducing device, comprising: selecting means for switching the plurality of divided reproduced signals within an overlap period to output a selected output signal; and a demodulated signal having an average level of a demodulated signal obtained by demodulating the selected output signal. Zero cross detection means for detecting a plurality of zero cross timings, zero cross timing specifying means for specifying one of the plurality of zero cross timings obtained by the zero cross detection means, and a detection result of the inclination of the demodulated signal Interpolating means for interpolating a switching noise generated in the demodulated signal by varying an interpolation amount according to the first zero-cross timing. When the one zero cross timing is within the overlap period, the selection means switches and selects the plurality of reproduction signals at the one zero cross timing, and the interpolation means performs the one zero cross timing. If the one zero-cross timing is not within the overlap period, the plurality of reproduction signals are switched and selected at a timing within the overlap period, and the interpolation means performs interpolation. A signal reproducing device characterized by attenuating an interpolation amount. A recording system for overlappingly recording a plurality of divided recording signals obtained by modulating and dividing a continuous signal on a recording medium;
A reproduction system for reproducing the continuous signal by integrating a plurality of divided reproduction signals obtained by sequentially reproducing the recording medium, wherein the plurality of divided reproduction signals are transmitted within an overlap period. Selecting means for switching and outputting a selected output signal; zero-cross detecting means for detecting a plurality of zero-cross timings of the demodulated signal based on an average value level of the demodulated signal obtained by demodulating the selected output signal; A zero-cross timing specifying means for specifying one of the plurality of zero-cross timings obtained by the method; and an interpolating amount corresponding to the detection result of the inclination of the demodulated signal being varied by the one of the zero-cross timings. Interpolating means for interpolating switching noise generated in the signal, wherein the one zero-cross timing is the overlap period. The selection means switches and selects the plurality of reproduction signals at the one zero cross timing, and the interpolation means interpolates the noise based on the one zero cross timing, while the one zero cross timing is A signal recording / reproducing apparatus characterized in that, when the time is not within the overlap period, the plurality of reproduction signals are switched and selected at the timing within the overlap period, and the interpolation means attenuates the interpolation amount.