JPS60160276A - Video signal processing unit - Google Patents

Abstract

PURPOSE:To prevent shift of timing at a connecting point at return by providing a sub-memory different from a main memory outputting a replacing video signal so as to adsorb the shift of timing at a signal connecting point. CONSTITUTION:A control circuit 4 including a sub-memory 17 is provided. A signal (a) is applied to the sub-memory 17. The memory 17 is a circuit whose delay time is controlled variably by a clock pulse. Since a horizontal synchronizing signal in a digital signal of a composite video signal reproduced at present within a timing adjusting time is controlled so that its phase is made coincident with the horizontal synchronizing signal in the preceding digital signal before >=1 field read from the main memory 6, the read section of the memory 6 is finished and the mode enters the write section and also when the mode is switched so as to output selectively a signal reproduced at present from an output terminal of the control circuit 4, the signal is connected without timewise shift.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal processing device, and particularly to a video signal processing device that reads out horizontal scanning period information on one or two pairs of composite video signals that are input from time to time. The present invention relates to a video signal processing device that replaces a composite video signal with information of a substantially equivalent period one field or more earlier than the previous composite video signal, and then restores the original composite video signal again.

Prior art and its problems In a helical scanning type VTR, during variable speed playback in which a recorded magnetic tape is run (or stopped) at a tape running speed different from that during recording and the recorded edge video signal is played back, the tape head It is well known that the head scanning locus is drawn at a different slope from the recording track trace because the relative velocity between the head and the recording track is different from that during recording. For this reason, magnetic tape has a track pattern in which adjacent tracks are recorded by rotating heads having gaps with different azimuth angles, and there is no guard band or only a very small guard band between the tracks. During variable-speed playback, the reproducing rotary head performs one track scanning period on two tracks: a track recorded by a rotary head with a gap of the same azimuth angle as the reproducing rotary head, and a track recorded with a rotary head with a gap of a different azimuth angle (reverse track). Therefore, during reverse track scanning, the reproduced signal level becomes extremely low due to the azimuth loss effect and the S/N ratio deteriorates. Similarly, during variable speed playback of a magnetic tape with a track pattern in which a guard band of a sufficient constant width is formed between adjacent tracks, the guard band is crossed more than once per track scanning period, so when the guard band is scanned, The reproduced signal level becomes extremely low and the S/N ratio deteriorates.

Therefore, in the patent application filed on January 18, 1980 (name of the invention "Video Signal Processing Device"), the present applicant previously stated that the section where the reproduced FM signal level became extremely low during variable speed reproduction etc. proposed a video signal processing device in which the reproduced composite video signal is replaced with a reproduced composite video signal of approximately the same interval one track scanning period ago, which is read from the memory. In this proposed device, when writing a reproduced composite video signal into the memory through an AD converter or reading a digital video signal of the reproduced composite video signal from one track scanning period ago from the memory, an address command signal is sent based on the horizontal synchronization pulse and the vertical synchronization pulse. is being generated.

However, the reproduced FM level of the reproduced composite video signal that comes in from time to time has become extremely low. When replacing the video signal with information from approximately the same period of time, and then returning to the original playback video signal as soon as the process is completed, there is a problem in that the timing often deviates at the video signal connection point at the time of the restoration. .

Therefore, the present invention provides a second memory (sub memory) different from the first memory (main memory) that outputs the replacement digital video signal to absorb the timing deviation at the signal connection point. An object of the present invention is to provide a video signal processing device that solves the above problems.

Means for Solving the Problems The present invention provides at least F.
an AD converter that converts a demodulated composite video signal that has been reproduced in a signal format having an M signal into a digital video signal; a first memory having a capacity that can store at least one field of digital video signals; and an AD converter. delay circuit means having a second memory for selectively outputting an output signal of the device by giving a designated delay time to the output signal; and a switch for selectively outputting one of the output signals from both the delay circuit means and the first memory. means for causing the switch means to selectively output the read output signal of the first memory during a period in which the level of the reproduced composite video signal is lower than a certain value and for a certain period around the same, and for other than the above period, a delay circuit means. a first control means for causing the switch means to select the output signal of the first memory and write operation of the first memory; a second control means that detects a relative phase difference between the signals and causes the delay circuit means to selectively output a digital video signal to which a delay time such that the phase difference becomes zero or extremely small is selectively output; and the switch means. an output means for obtaining a reproduced composite video signal from the output signal of the
One embodiment will be described below with reference to the drawings.

Embodiment FIG. 1 shows a block system diagram of an embodiment of the apparatus of the present invention. In the figure, a reproduced composite color video signal is input to an input terminal 1. This reproduced composite color video signal is produced by, for example, frequency modulating (FM) the luminance signal, frequency converting the carrier color signal to a low frequency band, frequency division multiplexing of both signals, and transmitting one field to one track using a rotating head. The magnetic tape recorded on successive tracks is played back at variable speed, and the FM! [! The trace signal is FM-demodulated, the low-frequency conversion carrier color signal is frequency-converted to the original band, and these two signals are multiplexed to obtain a reproduced composite color video signal substantially compliant with the standard method. In addition, when the variable speed playback described above is applied to a VTR using an azimuth recording/playback method, the magnetic tape is run at a speed that moves the magnetic tape by an even number of track pitches per one track scanning period (one field).
or by stopping the traveling), thereby establishing that a reproduction signal was normally obtained by another rotary head in the corresponding section one track scanning period before the section in which the rotating head consisting of at least one scans the reverse track. Become.

The reproduced composite color video signal inputted to the input terminal 1 is supplied to the AD converter 3 via the amplifier 2, where it is analog-to-digital converted into a digital video signal, and then sent to the memory and control circuit described below. 4, the pass line controller 5 is supplied to the memory 6, the first timing control circuit 7, and the DA converter 12, respectively. The timing control circuit 7 is supplied with a control signal from an input terminal 8 together with the output digital video signal of the pass line controller 5. This control signal is, for example, at a high level during a period in which the amplitude of the FMi degree signal reproduced from a rotary head that is scanning a magnetic tape becomes smaller than a certain value due to reverse track scanning, and at a low level during a period in which the amplitude exceeds this certain value. This is the 2fia signal generated so as to be, for example, the signal shown in FIG. 5(A). The timing control circuit 7 outputs a pulse synchronized in phase with the control signal k to the second timing control circuit 10 from the output terminal 9a.

Further, the timing control circuit 7 outputs the horizontal synchronization pulse from which the equalization pulse and the vertical synchronization pulse have been removed from the output terminal 9b and supplies it to the timing control circuit 1o, while shaping the vertical synchronization pulse from the output terminal 9c. The generated pulse is output and supplied to the address signal generation circuit 11. The timing control circuit 10 generates a signal controlled by the color subcarrier frequency based on the signal from the terminal 9a and supplies it to the pass line controller 5 for switching control, and also controls the memory based on this signal. (main memory) Generates the CAS (column address strobe) signal, RAS (row address strobe) signal, WE (read/write control signal, etc.) necessary for reading and writing to the memory 6, and supplies them to the memory 6. , and also outputs a signal to the address signal generation circuit 11.The address signal generation circuit 11 generates an address signal and supplies it to the memory 6.The memory 6 is, for example, a random access memory (R
AM) is a field memory with a storage capacity capable of storing one field's worth of digital video signals, and its readout output signal (digital video signal) is supplied to the pass line controller 5 and taken out from the pass line controller 5. Write digital bitio signal.

The DA converter 12 performs digital-to-analog conversion on the input digital video signal and returns it to a composite color video signal, which is an analog signal, and passes it through an amplifier 13 to an output terminal 14.
Output to. Here, the memory 6 is normally written with the memory supplied via the pass line controller 5 and the output digital video signal from the control circuit 4, but when the rotary head performing variable speed playback scans a reverse track, As described above, the memory 6 is switched to read control during at least the period including the scanning section, and
Since the pass line controller 5 selects and outputs the reproduced digital video signal of the same interval one track scanning period ago, which is read from the memory 6, the reproduced composite color video signal of the output terminal 14 is usually the signal that is currently being scanned on the magnetic tape. This is the reproduced composite color video signal of the current field reproduced by the rotating head of In this case, the reproduction composite color video signal is replaced with the corresponding section of the odd field). This makes it possible to prevent deterioration of the S/N ratio during reverse track scanning.

Here, the present invention is characterized in that a memory and a control circuit 4 are provided, and the details of this circuit 4 will be explained next. FIG. 2 shows a circuit diagram of one embodiment of the memory and control circuit 4. As shown in FIG. In the figure, the input terminal 15 receives a digital video signal of the composite color video signal currently being reproduced taken out from the AD converter 3, and the input terminal 16 receives a digital video signal from the pass line controller 5. be done. The digital video signal a shown in FIG.
is supplied to The memory 17 is a charge coupled denorth (COD) or a packet brigade device (
BBD) or other charge transfer devices, or shift registers, etc.
In a circuit whose delay time is variably controlled by a clock pulse, for example a shift register is used here, each bit output terminal of the plurality of bits is sequentially delayed by one period of the D clock pulse from the input terminal 18. The signals are taken out in parallel and supplied to the multiplexer 19.

The up/down counter 20 counts clock pulses from the input terminal 18 and sends the counted value signal to the multiplexer 1.
9 control terminal. As a result, the multiplexer 19 outputs a negative output signal (here, a signal b to which a delay time tx has been added) according to the count value of the up/down counter 20 among the parallel output signals from the memory 17 to which different delay times have been added. ) is selected and output. Multiplexer 1
The digital video signal shown in FIG. 3(B) taken out from 9 is supplied to the path line controller 5 via the output terminal 31, while the horizontal sync pulse is detected and separated by the horizontal sync pulse detection circuit 21. Waveform shaping circuit 2
2kl: is supplied, its falling edge is detected and converted into a pulse f as shown in FIG. 3(F), and further J
- is supplied to the J terminal of the flip-flop 70 and the T terminal of the T-flip-flop 24, respectively.

On the other hand, the digital video signal from the pass line controller 5 is supplied to the input terminal 16 as described above.
Time (1 or earlier, the timing control circuit 1 shown in FIG. 1
The memory 6 is performing a read operation based on the WE multiplied signal from 0, and a high level signal e as shown in FIGS. 3(E) and 5(C) is sent from the timing control circuit 10 to the pass line controller 5. When the pass line controller 5 is in the state of selectively outputting the readout output digital video signal of the memory 6, the input terminal 1
A digital video signal of a composite video signal read out from the memory 6 and reproduced one track scanning period ago passes through the pass line controller 5 and enters the path line controller 6 . Now, the readout output digital video signal of this memory 6 is the third one.
As shown in Figure (C), it is assumed that for some reason, the digital video signal C is delayed by the width of the horizontal synchronizing pulse with respect to the digital video signal a of the composite video signal currently being reproduced.

This digital video signal C is detected and separated by a horizontal synchronizing pulse detection circuit 25, and is supplied to a waveform shaping circuit 26, where the falling edge of the horizontal synchronizing pulse is detected and is shown in FIG. 3(G). After being converted into a pulse g as shown in FIG.
7 and the T terminal of the flip-flop 27, respectively. J
-, the flip-flop 23 receives the clock pulse from the input terminal 28 to the clock input terminal, and the pulses f and 9 from the Q output terminal by supplying the pulses f and 9 to the J terminal. A pulse h as shown in FIG. 3(H) is generated and outputted at a high level for a period corresponding to the phase difference, and the counting direction control terminal tJ of the up/down counter 20 is output.
/D. The up/down counter 20 is configured to perform addition counting when the input pulse at the control terminal U/D is at a high level, and perform subtraction counting when it is at a low level.

Furthermore, the Q output signals of the T-flip-flops 24 and 27 are respectively supplied to an exclusive NOR (EX-NOR) circuit 29, which corresponds to the phase difference between pulses f and g as shown in FIG. 3 (1). After the pulse i is converted into a low level pulse i for the period of time, the pulse i is supplied to one input terminal of the OR circuit 30. On the other hand,
Output terminal 9d of timing control circuit 7 shown in FIG.
3 (D), the signal becomes low level only for a preset period of time immediately before the time t1 at which the readout output digital video signal of the memory 6 is restored to the digital video signal currently being reproduced from the AD converter 3. > and Figure 5 (B
) is generated and output and applied to the other input terminal of the OR circuit 30.

That is, the 0-level period of the pulse d corresponds to the timing adjustment time. As a result, as shown in FIG. 3 (J) extracted from the OR circuit 30, when there is a phase difference between the pulses f and Q within the timing adjustment time, the pulse j remains at a low level for a period corresponding to the phase difference. is applied to the enable terminal E of the up/down counter 20.

When a high level signal is input to the enable terminal E, the up/down counter 20 is inhibited regardless of the status of other terminals U/D and CK, and stops counting operation while holding the count value. , when a low level signal enters the enable terminal E, the control terminal U/D
The clock pulses input to the clock terminal CK are counted in the counting direction according to the level of the clock terminal CK. Therefore, although the up/down counter 20 normally stops counting, the input terminal 15.
16 meat input digital video signals a.

The counting operation is performed only when there is a phase difference between the horizontal synchronizing pulses in C, and the digital video signal C read out from the memory 6 as shown in FIG. When the digital video signal A currently being played is delayed compared to the digital video signal A obtained by delaying the digital video signal A that is about to be switched to the digital video signal A, addition and counting are performed for a period approximately equal to the delay R. As a result, up-down The count value of the counter 20 increases in accordance with the delay time, and the multiplexer 19 outputs the parallel output signals of the memory 17 so that the delay time is approximately equal to the delay time compared to the normal - selected output signal. The output signal of is selectively output.

As a result, the horizontal synchronizing signal in the digital video signal taken out from the multiplexer 19 to the output terminal 31, etc., is the same as the horizontal synchronizing signal in the digital video signal C, as shown in FIGS. It substantially matches the synchronization signal c1.

On the other hand, if the digital video signal S lags behind the digital video signal C, the waveform shaping circuit 22.2
The output signal of No. 6 is shown in FIG. 4 (A).

(B) as shown by r' and g', and this results in J-
The Q output signal of the flip-flop 23 is
, g' at low level for a period corresponding to the phase difference (
C) The pulse h′ shown in FIG. Also, EX-NOR circuit 2
The output signal of 9 becomes a pulse i' shown in FIG. 9(D). Further, the output signal of the OR circuit 3o becomes a pulse j' as shown in FIG. 4(E), which is obtained by extracting only the low level period within the timing adjustment period from the low level period of the pulse i'. As a result, the up/down counter 19 is caused to perform subtraction counting during the O-level period of the pulse j', and the multiplexer 19 is used to cause the delay time of the pulse to be longer than that of the normal - selected output signal among the parallel 1 output signals of the memory 17. An output signal that is smaller than the 0-level period of j' is selectively output. As a result, the phase of the horizontal synchronizing signal in the digital video signal taken out from the multiplexer 19 is made substantially coincident with the horizontal synchronizing signal in the digital video signal read out from the memory 6.

Effects As described above, according to the present invention, the horizontal synchronization signal in the digital video signal of the composite video signal currently being played back is read out from the first memory within the timing adjustment time.
Since the phase is controlled so as not to match the horizontal synchronizing signal in the digital video signal that is more than one field in front, as soon as the read period of the first memory ends and the write period begins,
When switching to selectively output the digital video signal currently being played from the output terminal of the control ti11 circuit having the second memory, signal connections can be made without time lag, thereby improving the image quality at the signal connection point. Can be improved, S
It has features such as being able to reproduce good images (image signals) without deterioration of /N ratio.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the device of the present invention;
FIG. 2 is a circuit system diagram showing one embodiment of the main part of the device of the present invention, FIGS. 3(A) to (J), FIGS. 4(A) to (E), and FIGS. 5(A) to ( C) is a signal waveform diagram for explaining the operation of FIGS. 1 and 2, respectively. 1... Reproduction composite color video signal input terminal, 3...A
D converter, 4... memory and control circuit, 5... pass line controller, 6... memory (main memory)
, 7.10... Timing control circuit, 8... Control signal input terminal, 11... Address signal generation circuit, 12.
...DΔ converter, 14... Reproduction composite color video output terminal, 15.16... Digital video signal input terminal,
17...Memory (sub memory>, 18.28...Clock pulse input terminal, 19...Multiplexer, 2
0...Up/down counter, 21.25...Horizontal synchronizing pulse detection circuit, 23...Flip-flop in J-, 24.27...T-flip-flop, 31...
・Digital video signal output terminal.

Claims (1)

[Claims] If the reproduction FM signal level is at a speed different from that during recording and is smaller than a certain value in any one track scanning period, then the level is higher than the certain value in the corresponding section one track scanning period before. A composite video signal that is reproduced in a signal form having at least an FM signal and then demodulated from a recording medium that is run at a speed such that a reproduced FM signal of a certain level is obtained or whose running is stopped is converted into a digital video signal. an AD converter to convert, a first memory having a capacity capable of storing at least one field of digital video signals, and a designated delay time given to the output digital video signal of the AD converter for selective output. delay circuit means having a second memory; switch means for selectively outputting either the output signal of the delay circuit means or the read output signal of the first memory; During a period smaller than a certain value and a certain period around it, the switch means uses a digital video signal of a corresponding section one track scanning period ago read from the first memory instead of the output signal of the delay circuit means. a first control means for causing the switch means to selectively output the output signal of the delay circuit means and to write the output signal of the delay circuit means into the first memory during a period other than the above-mentioned period; , the relative phase difference between the synchronization signals in the power signals of the switch means and the delay circuit means is detected within the above-mentioned certain period, and a delay time is provided such that the phase difference becomes zero or extremely small. a second digital video signal for selectively outputting the digital video signal from the delay circuit means;
1. A video signal processing device comprising: a control means; and an output means for obtaining a reproduced composite video signal from the output signal of the switch means.