JPS6052496B2 - Signal recording and reproducing device using PCM method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal recording and reproducing apparatus using the PCM method.

When the PCM system is used, a normal audio tape recorder is unsuitable as a recording/playback device because the signal spans a wide band. Therefore, a VTR (video tape recorder)
It is possible to use A VTR originally has the function of recording and reproducing television signals, and it is preferable to be able to record and reproduce PCM digital signals rather than impairing this function. Taking these points into consideration, the present invention is applied to a device that changes a PCM digital signal into a waveform similar to a television signal, thereby making it possible to record and reproduce PCM signals without making any changes to the VTR itself. It's something.

Fig. 1 shows an outline of a device for recording and reproducing acoustic signals in PCM format using a VTR, in which 1 indicates a helical scan rotary two-head VTR, 2i its recording signal input terminal, and 20 its reproduction signal output terminal. It is.

Further, 3L indicates an input terminal for the left signal of an acoustic signal, for example, a 2-channel stereo signal, and this signal is passed through a low-pass filter 4L, so that the high frequency range is somewhat limited, and is sampled by a sampling and holding circuit 5L. 6L converts the sampling output into parallel code,
Furthermore, it is converted into a serial code by a parallel-to-serial converter 7 and written into a memory device 8. On the other hand, the right signal 1 is supplied from the input terminal 3R, is converted into a parallel code by passing through a low-pass filter 4R), a sampling hold circuit 5R, and an AD converter 6R, and is further converted into a serial code by a parallel-serial converter 7. is written to the memory device 8. The readout output of the memorif device 8 is supplied to a mixer 9, where an equalization pulse and a synchronization signal are added, and then supplied to the recording signal input terminal 2 of the VTR 1. The data are sequentially recorded as inclined tracks on a magnetic tape by two rotating magnetic heads through the recording system of the VTR 1. Note that 10 is a pulse generator that generates gate pulses supplied to sampling and hold circuits 5L and 5R, clock pulses for AD converters 6L and 6R and parallel-serial converter 7, clock pulses for memory device 8, equalization pulses, and synchronization signals. , and 11 indicates a fixed reference clock generator. During playback, output terminal 2.

A reproduced signal having a waveform similar to the above-mentioned recording signal waveform appears from , and is supplied to the synchronization separation circuit 29 , from which only data is obtained, and this is written into the memory device 28 .
The memory device 28 expands the data along the time axis, contrary to the time of recording, and removes time axis fluctuations such as jitter, so that the read output of the memory device 28 has no missing data and no time axis fluctuations. This is converted into a parallel code by the serial/parallel converter 27, and the DA
Converters 26L, 26R and low pass filters 24L, 2
4R, a continuous stereo left signal and stereo right signal are demodulated and obtained at terminals 23L and 23R, respectively. The synchronization signals separated by the synchronization separation circuit 29 are supplied to the pulse generator 20, and based on these synchronization signals, clock pulses and control pulses for the memory device 28, serial/parallel converter 27, and DA converter 26L are generated.
, 26R are formed. As mentioned above, when audio signals are recorded and reproduced using the PCM method using a VTR1, the recorded signal waveform containing digital information is formally the same as the television signal. has been done.

This has a signal processing circuit for recording and reproducing audio signals using the PCM system in the form of an adapter, and in addition to the original function of recording and reproducing television signals, by attaching the above adapter, you can perform the following functions without making any changes to the VTR itself. Re-record high-quality audio signals! This is so that we can live our lives. Second
Figure A shows a recording signal waveform considered based on such considerations, in which the horizontal synchronizing signal HD, the vertical synchronizing signal VD, and data are arranged in series in units of one field of the television signal.

As an example, based on the frequency characteristics of a VTR, the maximum transmission bit rate is 1.4 MD/Sec, and the number of bits required to encode an audio signal is 26 per word.
The number of bits allocated to the horizontal synchronization signal inserted in each word (hereinafter referred to as one block) is 2.
The transmission rate F, per block, which satisfies the conditions that the sampling rate is 40 kHz or more, and the transmission rate Ft of the block unit is an integral multiple of the horizontal frequency (15.75 kHz), is 47.25.
It becomes kHz. In addition to the above-mentioned conditions, the sampling frequency Fs is determined by selecting the sampling rate Fs of the analog signal and the transmission rate F, in an integer ratio relationship in order to compress and expand the time axis of data within one field. By adding , the sampling rate Fs becomes 44.1k
Selected as Hz. At this time, it becomes (F, :15:14). Therefore, the data sampled during one field (116(g)Ec) is 735 samples. Telegraph this. The transmission rate F, which is three times the horizontal frequency of the video signal,
Therefore, the data in one field is 735 blocks (245H in time) as shown in FIG. 2A.
Therefore, the data deletion period IRG in one field is (2
62.5H-245H=17.5H). In this period 1RG, as shown in FIG. 2C, an equalizing pulse is inserted over a targeted period similar to the geometric pulse of the television signal, and a vertical synchronizing signal VD is inserted in the targeted period following this equalizing pulse. is inserted. The equalization pulse is a negative pulse with a pulse width equivalent to 1 bit and a period of 14 bits, and the vertical synchronization signal VD includes a positive pulse with a pulse width equivalent to 2 bits and a period of 14 bits. Note that the equalization pulse following the vertical synchronization signal D in the television signal is not particularly required and is therefore not inserted. Also, from the trailing edge of the vertical synchronization signal D, there are 3 blocks for even fields and 2.5 blocks for odd fields.
Data is input from a remote location, and period 1
RG is set to be 17.5H on average. Furthermore, no data is inserted in the approximately 10H period before the equalization pulse, and only the horizontal synchronization signal HD is inserted, so that it is not affected by noise caused by head switching, etc. that occurs near the vertical synchronization signal D. has been done. Further, the number N of bits allocated to one block of data is selected to be 28 bits from the highest transmission bit of VTR1.

FIG. 2B shows this one block, in which one word of 26-bit data is inserted after the horizontal synchronizing signal D having a pulse width equivalent to 2 bits. In this case, the left and right signal data of the two-channel stereo signal are each 13 bits, and the left signal data is inserted in the first half of one block.
The right signal data is inserted in the latter half. Note that the horizontal synchronizing signal HD has a level more negative than the data ゜゜0゛, and the amplitude ratio of the two is (3:7).
In the above PCM recording and reproducing apparatus for audio signals, the memory devices 8 and 28 are required to be able to perform writing and reading asynchronously in order to convert the time axis of data.

For this reason, first-in-first-out (FirstInFirstO) that can write and read simultaneously.
ut) type shift register can be applied. However, this shift register is disadvantageous compared to RAM in terms of cost when applied when a capacity of several kilobits or more is required. On the other hand, when operating a RAM, it is impossible to perform writing and reading asynchronously because there is a risk that writing and reading will overlap for the same address. However, by devising control over the RAM, writing and reading can be performed asynchronously.
In addition, in the acoustic signal recording and reproducing apparatus shown in FIG. 1, the recording system and the reproducing system are configured separately, but the memory devices 8 and 2
8 etc. can be shared during recording and playback.

FIG. 3 shows the memory device and its peripheral circuits in this case. In Fig. 3, 30 is an input amplifier, 31 is a RAM
l32 is a memory control circuit including an address counter, etc.
37 is a serial/parallel converter. 41, 42, 43, 44,
Reference numeral 45 indicates a switching circuit which is switched depending on the operating state of the VTRl, that is, whether the VTRl is in a recording state or a reproducing state. In the playback state, it is connected to the PLB side.

The switching circuits 41 to 45 switch between the modes based on the operation of the recording switch 46. Mode signal RE generated by mode signal generator 47
C. ．． In pregnancy, it is controlled by PLB. At the time of recording, the recording switch 46 is turned on, and the parallel data from the AD converter is converted into a serial code by the serial/parallel converter 37, written to the RAM 3l via the switching circuit 41, and the RA
The time-base compressed data from M3l is supplied to the mixer 9 via the switching circuit 42, a synchronizing signal is not added thereto, and the data is supplied to TRl as a recording signal. The synchronization signal is transmitted from the output of the reference clock generator 11 to the synchronization signal generator 33.
is formed. In addition, since the conversion of the time axis of data is done in conjunction (synchronization) with a synchronization signal, the synchronization signal is
5 and is supplied to the memory control circuit 32. At the same time, a start/stop signal from the start/stop signal generator 35 is supplied to the memory control circuit 32 and the serial/parallel converter 37, thereby defining the timing of data processing for one field. For this purpose, mode signals REC and PLB are supplied to the start/stop signal generator 35, as well as a synchronization signal via the switching circuit 43 and the synchronization separation circuit 36. Further, a clock pulse generator 34 generates clock pulses for the RAM 31 and the serial/parallel converter 37. Next, during playback, record switch 46
is turned off, and the switching circuits 41 to 45 are in a state where they are connected to the PLB side or the shingle side, which is different from the state shown in the figure.

Then, the reproduced signal from TRl is written to the RAM 3l via the input amplifier 30 and the switching circuit 41, and
A synchronization signal is separated from the reproduced signal by a synchronization separation circuit 36. In conjunction with this synchronization signal, a clock pulse generator 34
A clock pulse is generated from the start/stop signal generator 35, and a start/stop signal is generated by the start/stop signal generator 35. Then, the time axis of the data is expanded by the RAM 3l, and the data is supplied to the serial/parallel converter 37 via the switching circuit 42, where it is converted into a parallel code and then supplied to the DA converter. In the signal recording and reproducing device using the PCM method described above, the RA
Compression or expansion of the time axis of data by M3l is performed in units of one field, so that the capacity of R and AM3l does not become too large.

Therefore, the memory control circuit 32 also controls the RAM 3l on a field-by-field basis. The present invention is based on this R.
When controlling AM3l, during recording, a standby signal is formed in relation to the start point of the recording state, and during playback, a standby signal is formed in synchronization with the first of the reproduction vertical synchronization signals, and data processing is performed. It is designed so that it can be done correctly. In one embodiment of the present invention, a standby signal STBY is generated by a mode signal generator 47, which clears the address counter of the memory control circuit 32 and also clears the serial/parallel converter 37. FIG. 4 shows the configuration of the mode signal generator 47. When the recording switch 46 is turned on, its output becomes the fifth
As shown in FIG.

The signal is supplied to the NAND circuit 25 via the inverter 51, delayed by the integrating circuit 53, and then sent to the inverter 5.
4. The output of this inverter 54 is shown in FIG.
Since this is supplied to the NAND circuit 52, the output of the NAND circuit 52 is as shown in C of the figure. Further, the output of the inverter 54 is supplied to the inverter 58 via the integrating circuit 55, and the output of the inverter 56 is supplied to the fifth inverter 58.
The result is shown in Figure D, and this becomes the signal REC. In addition, when the output of the inverter 51 is "0", the reproduced vertical synchronizing signal PSVD is separated from the reproduced signal shown in FIG. 5E.
A monostable multivibrator (referred to as monomulti) MMIO is provided which is triggered by the rising edge of . The time constant of the monomulti MMlO is selected so that it has a metastable period longer than one field (1160 sec), and the structure is such that it can be retriggered. Therefore, the monomulti MMlO is triggered by the first reproduced vertical synchronization signal PSVD, and thereafter is retriggered, so its output Q
maintains the state of ``1'' as shown in FIG. 5F. This output Q is supplied to a NAND circuit 57, and an integration circuit 58
and is supplied to the NAND circuit 57 via the inverter 59. The output of the inverter 59 is as shown in FIG. 5G, and therefore the output of the NAND circuit 57 is as shown in FIG. Further, the output of the inverter 59 is supplied to the inverter 61 via the integrating circuit 60, and its output (FIG. 5 1) becomes the mode signal PLB. In addition, NAND circuits 52 and 5
7 is supplied to the NAND circuit 62, and the NAND circuit 62
The output of is invar. - is supplied to the inverter 63, and the inverter 63
The output shown in FIG. 5J becomes the standby signal STBY. With the above configuration of the mode signal generator 47, the mode signal REC. In addition to forming the PLB, the standby signal STBY is generated when the recording switch 46 is turned on, when it is turned off, and when the first reproduction vertical synchronization signal PSVD is generated. FIG. 6 shows an example of the clock pulse generator 34 for forming clock pulses from the mode signal from the mode signal generator 47 mentioned above and the reference clock pulse from the reference clock generator 11.
The reference clock generator 11 is configured as a stable oscillator such as a crystal oscillator, and has a transmission lock frequency (28f,=1.
323MHz) signal. During recording, the mode signal REC is supplied to the frequency divider 94 via the NAND circuits 91 and 92, and the frequency is divided into 1130 to produce the sampling signal RSM of the sampling frequency Fs (44.1kHz).
PL is formed. Furthermore, a clock pulse (26 fs) for converting one parallel 26-bit signal into a serial code is connected to a phase comparator 95 and a low-pass filter 96.
, VCO (voltage controlled variable frequency oscillator) 97 and 11
It is formed by a PLL circuit 107 consisting of a frequency divider 98 with a frequency division ratio of 26. This clock KWC is the RAM during recording.
This also serves as the write clock for 3L, and is taken out via a NAND circuit 99. The PLL circuit 107 is used for sampling signal RSMPL and clock KW.
This is to synchronize C. The read clock m of the RAM 3l during recording is formed by the output of the reference clock generator 11 passing through the gate circuit 100. During playback, the horizontal synchronizing signal PlID separated from the playback signal is sent to the phase comparator 101, the low-pass filter 102, and the VCO1O3.
and a frequency divider 104, and the transmission lock frequency (
28f. ) is formed, and this signal is taken out via the NAND circuit 105 only during reproduction, and the write clock for the RAM 3l is obtained.

Along with this, the output of the PLL circuit 108 is transmitted to the NAND circuit 93.
and 92 to the frequency divider 94, so that
Sampling signal PSMP during playback in the same way as during recording
Furthermore, the output of the PLL circuit 107 is supplied to the NAND circuit 106, and the readout clock for the RAM 3l and a clock signal for converting serial data into parallel data are obtained at its output. Here, the PLL circuit 108 is designed to sufficiently respond to relatively fast time axis fluctuations such as jitter included in the reproduced signal, and even if the horizontal synchronizing signal PHD is lost due to dropout or the like, the VCO remains unchanged.
The lock range is designed to be narrow so that the oscillation frequency of O3 does not deviate significantly.

On the other hand, the PLL circuit 107 is designed not to respond to time axis fluctuations in the reproduced signal, and generates a clock mark C of a constant period even during reproduction. As an example, if correction for time axis fluctuations is performed on components of 0.2 Hz or more, it is designed to respond only to components slower than that. Therefore, although the clock may have slow time axis fluctuations of 0.2 Hz or less during reproduction, there is no adverse effect when the demodulated signal is reproduced by a speaker or the like. With the above configuration, the clock pulse generator 34 can be used both during recording and during reproduction. FIG. 7 shows a start/stop signal generator 35 that generates a start/stop signal for controlling the start and stop of writing and reading of the RAM 3l.
09, 110, 111 are binary counters connected in series. During recording, the horizontal synchronizing signal generated by the synchronizing signal generator 33 is counted via NAND circuits 112, 113 by counters 109, 110, 111, and during playback, the horizontal synchronizing signal generated by the synchronizing signal generator 33 is counted via NAND circuits 114, 113. The synchronizing signal PSYNC is counted by counters 109, 110, and 111. The reproduced composite synchronization signal PSYNC is a synchronization signal obtained by supplying a signal reproduced from the VTRl to the synchronization separation circuit 36 and separating it, and includes a horizontal synchronization signal and a vertical synchronization signal. Figure 8A shows the mode signal (REC or PLB
), and B in the figure shows the horizontal synchronization signal (RHD or PSYNC) to be counted. Counter 109, 110, 11
A predetermined output of 1 is supplied to the NAND circuit 115, and when 7 horizontal synchronizing signals are counted, the output becomes "0", and is further passed through the waveform shaping circuit 116, as shown in FIG. 8D. A pulse is obtained and this pulse is supplied to a NAND circuit 117. Also, NAND circuits 118, 119,
120, the vertical synchronization signal (RSVD or PS) shown in FIG.
VD) is supplied to the NAND circuit 117. nand circuit 1
The output of 17 is used as a clear input for counters 109, 110, 111, and therefore the vertical synchronizing signal RSVD or PSV
The counters 109, 110, and 111 are cleared at the rising edge of D or the rising edge of the output of the waveform shaping circuit 116. At the same time, the RS type flip-flop FFl is set by the falling edge of the vertical synchronizing signal obtained from the output of the NAND circuit 119, which is inverted by the inverter.
When the counting power of 11 reaches 512, the flip-flop FFl is set by the fall of the output shown in FIG.
It becomes ND. The window signal WND defines the period of one field as shown in the enlarged view in Figure 9A, and the period of the horizontal synchronizing signal is 70 from the beginning of the field. The period is “0”
, and the length of data to be processed in one field (
735 block). During recording, the wind signal WND is generally not phase synchronized with the sampling signal RSMPL that samples the analog signal.
The window signal WND cannot be used directly as a RAM write start/stop signal, and the D-type flip-flop DF
The signal RWND shown in FIG. 9B synchronized with the signal RSMPL is formed by the signal RSMPL, and the signal RWND is supplied to the D-type flip-flop DF2, so that the writing becomes "1" from the trailing edge (rising edge) of the signal RWND. A start/stop signal RWG is generated.

The read start/stop signal RRG during recording is shown in Figure 9D.
As shown in FIG. 2, the signal RWND is delayed by γ1 from the rising edge of the signal RWND. This is because, as shown in FIG. 2, data is inserted from 3 blocks away for even fields and 2.5 blocks away for odd fields. However, the vertical synchronization signal RSVD from the synchronization separation circuit 36 is one block from the trailing edge of the actual vertical synchronization signal in the case of an even field, and "1 block in the case of an odd field".
Since it is assumed that there is a delay of 0.5 blocks, γ1 may be 2 blocks. The signal RWND for this purpose is passed through NAND circuits 121 and 122 to a D-type flip-flop D.
F3 and its output Q is supplied to the D-type flip-flop D.
F4, while these D flip-flops DF
NAND circuit 124,
A horizontal synchronizing signal is supplied through 125, and a read start/stop signal RRG at the time of recording is obtained at the output of the D-type flip-flop DF4.

During playback, the window signal WND is sent to the NAND circuit 123,
122 to D-type flip-flops DF3 and DF4, and the reproduced composite synchronization signal is supplied to NAND circuits 126 and 12.
5 through these D-type flip-flops DF3 and DF
4 clock input, a write start/stop signal PWG similar to that during recording is generated.

The read start/stop signal PRG during reproduction is set to 66r at the same timing as the write start/stop signal PWG.
' However, considering that the reproduced signal includes time axis fluctuations due to jitter, etc., the monomulti MMll is generated at the falling edge of the window signal WND passed through the NAND circuit 123. delayed by triggering,
The output thereof is supplied to a D-type flip-flop DF5 so as to be synchronized with the sampling signal PSMPL. FIG. 9E shows the read start/stop signal PRG. The start/stop signal RWG. generated as described above. ．． RRG. ．． P.W.G. ．． PRG is supplied to the memory control circuit 32, and RAr! The start and stop of write and read operations of 131 are controlled.

That is, during recording, writing is performed continuously by gating the write clock RWC with the write start/stop signal RWG, while the read start/stop signal RRG
The time required for data compression from the start of writing by gating the read clock RRC and γ1
The readout is started after a delay of . The timing at which writing of data for one field (735 blocks) ends coincides with the timing at which reading thereof ends. During playback, writing is started by gating the write clock PWC with the write start/stop signal PWG, and after a time delay necessary to compensate for time axis fluctuations, the read clock PRC is gated with the read start/stop signal PRG. Readout is initiated by gating . FIG. 10 shows data writing and reading based on the start/stop signals and clock pulses described above. 131 indicates a RAM and its peripheral circuit (indicated by 31 in FIG. 3) that performs
32 x 32 = 1024 bits) static MOS
It is RAM.

Here, the capacity CA (proc) required for compressing or expanding the time axis of data processed in units of one field, and the capacity required for correction of time axis fluctuations CB (proc).
, if the total capacity is CM=CA+CB, then the capacity CM is RA
This is nothing but what M requires.

As mentioned above, the writing rate to the memory device during recording is Fs (44.1kHz), which is equal to the sampling rate, and the reading rate is Fs (44.1kHz), which is equal to the transmission rate.
．． 25kHz). However, frequencies L and F are in block units. The memory device is configured so that writing and reading can be performed independently, and reading is started after CJfs (Sec) has elapsed after writing is started by the start/stop signals RWG and RRG mentioned above.
Since the timing at which writing of the 35 PRO) data ends coincides with the timing at which reading thereof ends, the minimum capacity CA required for time axis compression and expansion can be found from the following equation. CA=49 proc=1274
When reproducing the bit next time, the start/stop signals PWG and PR
G allows the compensation range for time axis fluctuation to be ±. ! If it is a block, the start of reading is delayed by Sec in advance.

As an example, approximately 12 blocks of CI3 are required to compensate for time axis fluctuations, so the capacity CM is CM=CA
+CB=61 blocks=1586 bits.

In one embodiment of the present invention, from the viewpoint of cost, a RAM with a long cycle time is used, and one package has 1024 bits of RAI! 4 are operated in parallel and intersected. Therefore, serial data is converted to 2-bit parallel data and RA
It is necessary to write to M and convert the 2-bit parallel read output of the RAM into serial data. However, since this consideration is not an essential problem for the present invention, the following description will be made for one RAM 13l. 10th
In the figure, 132 is an X address decoder, 133 is a Y address decoder, and 133 is a Y address decoder.
An address decoder, 134 is a write circuit, and 135 is a read circuit. Data inputs D and N are passed through an input buffer register 136 to become data BR synchronized with the write clock WC, and are supplied to the write circuit 134. The readout output via the readout circuit 135 is supplied to the output buffer register 137, from which the output BRO is taken out in synchronization with the address selection signal ADSLCT, and further supplied to the D flip-flop DF6, where it is clocked at a constant level by the readout clock RC. Output data DOUT converted to a rate is obtained. Note that the write/read control signal W days is supplied to the write circuit 134. RAMl mentioned above
The memory control circuit 32 for 3l and its peripheral circuits receives address selection signals ADSLCT and A from the write clock WC and read clock RC as shown in FIG.
A memory control signal generation circuit 138 that generates a DS country T and a write/read control signal W, and an address code A.

-A9. Here, the write clock WC is the write clock KW during recording generated by the clock pulse generator shown in FIG.
The read clock RC is obtained by supplying the write clock C during recording and the write clock C during playback to the NAND circuit 139, and the read clock RC is obtained by supplying the read clock during recording and the read clock H during playback to the NAND circuit 141. It is something that can be done. In addition, in FIG. 11, 143 is the 10-bit output WAO
-Write address counter that generates WA9, 1
44 is a read address counter that generates a 10-bit output RAO-R. During recording, a write clock WC gated by a write start/stop signal RWG is supplied to the write address counter 143 via NAND circuits 145 and 147, and a read start signal is supplied to the read address counter 144 via NAND circuits 148 and 150. A read clock RC gated by a stop signal RRG and a horizontal synchronization signal 2 is provided. The purpose of gating using the horizontal synchronizing signal is to form a period in which the horizontal synchronizing signal is inserted between each block, as is clear from the recording signal waveform in FIG. During reproduction, the write address counter 143 is supplied with a write clock WC gated by the write start/stop signal PWG and the composite synchronization signal PSYNC separated from the reproduction signal via NAND circuits 146 and 147, and the read address counter 144 A read clock RC gated by a read start/stop signal PRG is supplied via NAND circuits 149 and 150 to the read clock RC. Composite synchronization signal PSYNC
The reason for this is that there is no data between the blocks of data written to the RAM. The output WAO-WA9 of the write address counter 143 and the output RAO-RA9 of the read address counter 144 are supplied to the address selector 151.
O-WA, are supplied to address decoders 132 and 133 as address codes AO-A, and R, AO-RA9 are supplied to address decoders 132 and 133 as address codes AO-A during reading. Therefore, the address selector 151 receives an address selection signal AD.
SLCT and ADSLCT are provided. The write address counter 143 and the read address counter 144 are cleared by a standby signal STBY generated by the mode signal generator 47 described above.

In other words, the standby signal STBY is the first vertical synchronization signal PSVD when the recording switch 46 is turned on and during playback.
The write address counter 143 and the read address counter 144 are cleared at each point in time. Furthermore, a memory device consisting of a RAM and a memory control circuit can be written and read independently.

This will be explained with reference to the time charts of FIGS. 12 and 13. FIG. 12 shows a time chart during recording, in which the period Tw of the write clock RWC is in the relationship (Tw>TR) with the period TR of the read clock RRC, and the time axis of the data is compressed. The figure shows a time chart during playback, where the period Tw of the write clock PWC is (
This is a case where the time axis is expanded based on the relationship Tw<TR). However, the cycle Tw of the write clock PWC during reproduction has a time axis variation, but the time axis variation is corrected by reading data with the read clock PRC having a constant cycle TR. There is. The operation of the memory control circuit 32 and PAMl3l will be explained using the time charts shown in FIGS.
Data BR synchronized with (Figure 12B or Figure 13B),
(Figure 1J2A or Figure 13A).

The write address is sequentially determined by the address code WAO-WA formed by the write address counter 143 as shown in FIG. 12C or FIG. 13C. A mark signal MARK (FIG. 12D or FIG. 13D) having a pulse width approximately half the period Tw is generated by the write clock WC. Also, read clock RC (RRC or PRC)
Address code RAO-RA formed by read address counter 144 according to (FIG. 12E or FIG. 13E)
9, the read address is sequentially changed as shown in FIG. 12F or FIG. 13F.

The write/read control signal WV shown in FIG. 12G or FIG. 13G is the sum of the address set-up time (TsA), address hold time (THA), and writable pulse width (Tpw) determined by the specifications of the RAMl3l. A write cycle TwoO is defined. Further, the address selection signal ADSLCT (FIG. 12H or FIG. 13H) is “
The write address code is supplied to the address decoders 132, 133 when the value is "1", and the read address code is supplied to the address decoders 132, 133 when the value is "0".
3, and this period of ゜゜0゛ is the read cycle T
Becomes an RO. Then, the data is changed bit by bit by the write/read control signal WV and the address selection signal ADSLCT.
Data is written to AMl3l, and data is read bit by bit from RAMl3l. Read is an address selection signal. Data is taken into the output buffer register 137 in synchronization with the rising edge of ADSLCT, and therefore the output BRO has an irregular cycle as shown in FIG. 12 or FIG. 13. If left as is, later data processing will be troublesome, so the data is supplied to the D flip-flop DF6 and output data D of a constant period shown in FIG. 12J or FIG. Convert to UT. Ru. In this way, writing and reading of the RAM 13l can be performed independently (asynchronously).

Then, the start/stop signal RWG. ．． RRG. ．． P
Data is processed in units of one field using WGlPRG. By doing so, is it possible for the correction range specialist to estimate the accumulated amount of time axis fluctuation in advance? If this value is exceeded, an overflow occurs in which the next data is written before the RAM data is read, or an underflow occurs in which the previous data is read before the RAM data is written, but as long as the correction range is not exceeded, there will be no overflow or underflow. can compress and expand the generated time axis. As is clear from FIG. 12 or 13, the write cycle or read cycle is determined as follows.

First, when the read clock RC comes while the mark signal MARK is "1", the write cycle starts with the write clock WC, and in this case, the read clock RC does not immediately enter the read cycle but yields to the write cycle. do.

Next, when the read clock (RC) comes when the mark signal MARK is 660'', the effective read cycle starts from this point.In other words, in this case, the write cycle is performed as many times as necessary (maximum 112Tw), and the read In this case, the write cycle Twc is R
The time necessary for the AM write operation to be performed reliably is the sum of the address setup time t$, the address hold time THAl, and the write enable pulse width Tpw. Further, the read cycle is set to be longer than the time required for the read operation and less than 1/w. A write/read control signal W'' and an address selection signal ADSLCT for performing such an operation are generated by a memory control signal generation circuit 138.

FIG. 14 shows an example of the structure of the memory control signal generating circuit 138, where MM1 to MM5 each represent a monomulti, and the monomulti MM1 is triggered at the rising edge of the write clock WC to form a mark signal MARK. The monomulti MM3 is triggered by the falling edge of the output Q of the monomulti MM2, and defines the writable pulse width (Tpw), and its output O is taken as the signal W.
M4 defines address hold time (THA).
The monomulti MM5 defines a read cycle TRO after the end of the write cycle Twc, and is configured to be retriggerable. The output 6- of the monomulti MM5 becomes the signal ADSLCT, and the output Q becomes the signal ADSLCT. 15 and 16 are time charts of the above-mentioned control circuit. FIG. 15 shows the time of recording, and FIG. 16 shows the time of playback. The timing is right.

FIG. 15A or FIG. 16A is the write clock WC (RW).
C or PWC), FIG. 15C or FIG. 16C shows the read clock RC (RRC or PRC), and the monomultiple MMl is triggered by the write clock WC as shown in FIG. 15B or FIG. 16B. Mark signal MAR
K is formed. Since the control circuit shown in FIG. 14 has a loop configuration, first start from the monomulti MM3 to the control circuit shown in FIG.
It is assumed that the signal WC shown in FIG. 6D is obtained. At this time, the output Q of the monomulti MM3 is
The output MM3Q and the output delayed by passing through the integrating circuit and the inverter 152 are supplied to the NOR circuit 153, and the NOR circuit 1
53, as shown in FIG. 15F or FIG. 16F, a pulse WE such as a differential pulse of the rising edge of the signal
Δ appears. Since this pulse WEΔ and signal MARK are supplied to the NAND circuit 154, its output becomes as shown in FIG. 15G or FIG. The output Q is as shown in FIG. 15H or FIG. 16H. The output Q of the monomulti MM4 is supplied as it is to the OR circuit 155, and is also supplied to the OR circuit 155 via the integrating circuit and inverter 156. As shown in the figure, a pulse M is obtained by differentiating the falling edge of the output Q of the monomulti MM4.
M4QΔ appears. Also, read clock RC and signal M
ARK is supplied to the NAND circuit 157, and as shown in FIG. 15J or FIG. 16J, a pulse that becomes negative when the read clock RC comes when the signal MARK is "0" is generated at its output. The outputs of the OR circuit 155 and the NAND circuit 157 are supplied to the NAND circuit 158, and the NAND circuit 158 generates a pulse shown in FIG. 15K or FIG. In this case, since the monomulti MM5 is capable of retriggering, its output Q, that is, the signal ADSL
CT and its output O, ie signal ADSLCT, are shown in FIG.
1M or as shown in FIG. 16 L and M. The signal AD separate °CT is supplied to the NAND circuit 159 together with the signal MARK, so the output of the NAND circuit 159 becomes as shown in FIG. 15N or FIG. ) is supplied to the NAND circuit 160, and this output and the output of the NAND circuit 159 are supplied to the NAND circuit 161, and the monomulti MM2 is triggered at the falling edge of the output. By doing this, the write cycle is started by the signal Nχ cross CT which is RHJ at the start of the write cycle and by the write clock WC. The output Q of the mono-multi MM2 becomes as shown in FIG. 15 0 or 16 0, and since the mono-multi MM 3 is triggered at its falling edge, the write/read control signal shown in FIG. 15 D or 16 D is obtained. A WR will be formed. As is clear from the above, according to the present invention, the write address counter 143 and read address counter 144 of the RAM are cleared at the start of the recording state and at the time when the first reproduction vertical synchronization signal is obtained during reproduction. Therefore, data can be compressed or expanded on the time axis without overflow or underflow occurring when RAM writing and reading are controlled by the start/stop signal.

[Brief Description of the Drawings] Fig. 1 is a system diagram of a signal recording/reproducing device using the PCM method to which the present invention can be applied, Fig. 2 is a diagram showing the recording signal waveform, and Fig. 3 is a diagram showing a signal recording/reproducing device using the PCM method to which the present invention can be applied. A system diagram of the main parts of the signal recording and reproducing device, FIGS. 4 and 5 are a system diagram of the mode signal generator and its time chart, FIG. 6 is a system diagram of the clock pulse generator, and FIGS. 7, 8, and Fig. 9 is a system diagram of the start-stop signal generator and its time chart, Fig. 10 is a system diagram of the RAM and its peripheral circuits, and Fig. 11 is a system diagram of the start-stop signal generator and its time chart.
1 is a system diagram of the memory control circuit, FIGS. 12 and 13 are time charts of the memory device, and FIGS. 14, 15, and 16 are system diagrams of the memory control signal generation circuit and their time charts. 1 is the VTR, 2i is the VTR recording signal input terminal, 2・o
31 is a RAM, 32 is a memory control circuit, 33 is a synchronizing signal generator, 34 is a clock pulse generator, 35 is a start/stop signal generator,
36 is a synchronous separation circuit, 37 is a serial/parallel converter, 46 is a recording switch, 47 is a mode signal generator, 143 is a write address counter, 144 is a read address counter,
151 is an address selector.

Claims (1)

[Claims] 1. Convert the analog signal into a serial format digital signal using the PCM method, compress the time axis of this digital signal using a memory device, form a data missing period at regular intervals, and use the first standard in this data missing period. At the same time as inserting the signal, a second reference signal is inserted for each predetermined unit of the digital signal to obtain a recording signal, this recording signal is recorded on a recording medium by a wideband signal recording and reproducing device, and is reproduced from this recording medium. In a signal recording and reproducing device using the PCM system, the time axis of the signal is expanded by a memory device to fill in the data missing period, and the output of the memory device is converted from analog to analog to obtain the analog signal. During recording, a standby signal is formed based on the start point of the recording operation setting signal, and during playback, a standby signal synchronized with the first one of the first reference signals separated from the playback signal is formed, and the standby signal is formed in synchronization with the first one of the first reference signals separated from the playback signal, and the write operation of the memory device is performed. and a counter that generates a read address signal; and a signal recording/reproducing device using the PCM system, which is cleared by the standby signal.