JPS57191885A - Address controller for memory - Google Patents

Address controller for memory

Info

Publication number
JPS57191885A
JPS57191885A JP56075982A JP7598281A JPS57191885A JP S57191885 A JPS57191885 A JP S57191885A JP 56075982 A JP56075982 A JP 56075982A JP 7598281 A JP7598281 A JP 7598281A JP S57191885 A JPS57191885 A JP S57191885A
Authority
JP
Japan
Prior art keywords
write
address
output
approach
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56075982A
Other languages
Japanese (ja)
Inventor
Takaaki Ashinuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Akai Electric Co Ltd
Original Assignee
Akai Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Akai Electric Co Ltd filed Critical Akai Electric Co Ltd
Priority to JP56075982A priority Critical patent/JPS57191885A/en
Publication of JPS57191885A publication Critical patent/JPS57191885A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To shorten an abnormal section as much as possible, by providing an adress approach detecting circuit to set automatically addresses to initial values when write and read addresses coincide whith each other or approach each other abnormally. CONSTITUTION:When high-order 5 bits of write and read addresses coincide with each other, namely, write and read addresses approach each other up to the distance of a maximum address of lower 6 bits, the output of an address approach detecting circuit 14 becomes as shown in a figure (2), and an output Q of a D-FF15 becomes as shown in a figure (3). OR between the output Q of the FF15 and a vertical synchronizing signal, which is supplied from a terminal T3 and is as shown in a figure (1), is operated in an OR gate 16, and counters 11A, 11B, and 11C for write address are set to initial values by the output of this gate 16. This operation is repeated to lock addresses at a distance of the address of low-order 6 bits or more.
JP56075982A 1981-05-19 1981-05-19 Address controller for memory Pending JPS57191885A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56075982A JPS57191885A (en) 1981-05-19 1981-05-19 Address controller for memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56075982A JPS57191885A (en) 1981-05-19 1981-05-19 Address controller for memory

Publications (1)

Publication Number Publication Date
JPS57191885A true JPS57191885A (en) 1982-11-25

Family

ID=13591971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56075982A Pending JPS57191885A (en) 1981-05-19 1981-05-19 Address controller for memory

Country Status (1)

Country Link
JP (1) JPS57191885A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62202359A (en) * 1986-02-28 1987-09-07 Sony Corp Decoder

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52102013A (en) * 1976-02-24 1977-08-26 Sony Corp Memory unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52102013A (en) * 1976-02-24 1977-08-26 Sony Corp Memory unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62202359A (en) * 1986-02-28 1987-09-07 Sony Corp Decoder

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