JPS5522244A - Memory system - Google Patents
Memory systemInfo
- Publication number
- JPS5522244A JPS5522244A JP9385778A JP9385778A JPS5522244A JP S5522244 A JPS5522244 A JP S5522244A JP 9385778 A JP9385778 A JP 9385778A JP 9385778 A JP9385778 A JP 9385778A JP S5522244 A JPS5522244 A JP S5522244A
- Authority
- JP
- Japan
- Prior art keywords
- data
- real time
- address number
- vtr5
- memory circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Error Detection And Correction (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
Abstract
PURPOSE: To ensure a high-fidelity sound record and reproduction by writing the data in sequence into the reproduction memory circuit by separating the address number necessary to return the interleaved data to the original real time data by the number equivalent to the address number necessary to absorb the jitter.
CONSTITUTION: The anglog signal sent from sound source 1 is converted into the digital signal through A/D converter circiut 3 and then memorized temporarily in sound record memory circuit 4. And the data received the data compression and interleaving is recorded to VTR5. The data reproduced at VTR5 is returned to the real time data through reproduction memory circuit 6 to be written in sequence there by separating the interleaved data for the address number necessary to return it to the original real time data by the number equivalent to the address number necessary to absorb the jitter at VTR5. At the same time, the data are read out sequentially from the higher rank addresses to each writing adress of circuit 6 by the multiple of the interleave interval. Thus the real time digital data is obtained.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9385778A JPS5522244A (en) | 1978-07-28 | 1978-07-28 | Memory system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9385778A JPS5522244A (en) | 1978-07-28 | 1978-07-28 | Memory system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5522244A true JPS5522244A (en) | 1980-02-16 |
JPS6226105B2 JPS6226105B2 (en) | 1987-06-06 |
Family
ID=14094087
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9385778A Granted JPS5522244A (en) | 1978-07-28 | 1978-07-28 | Memory system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5522244A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5570920A (en) * | 1978-11-20 | 1980-05-28 | Victor Co Of Japan Ltd | Memory control system |
JPS5570919A (en) * | 1978-11-20 | 1980-05-28 | Victor Co Of Japan Ltd | Memory control system |
US4903148A (en) * | 1986-04-02 | 1990-02-20 | Matsushita Electric Industrial Co., Ltd. | Digital signal editing apparatus |
-
1978
- 1978-07-28 JP JP9385778A patent/JPS5522244A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5570920A (en) * | 1978-11-20 | 1980-05-28 | Victor Co Of Japan Ltd | Memory control system |
JPS5570919A (en) * | 1978-11-20 | 1980-05-28 | Victor Co Of Japan Ltd | Memory control system |
JPH0142069B2 (en) * | 1978-11-20 | 1989-09-08 | Victor Company Of Japan | |
US4903148A (en) * | 1986-04-02 | 1990-02-20 | Matsushita Electric Industrial Co., Ltd. | Digital signal editing apparatus |
Also Published As
Publication number | Publication date |
---|---|
JPS6226105B2 (en) | 1987-06-06 |
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