JPS54107327A - Pcm system recorder-peproducer - Google Patents

Pcm system recorder-peproducer

Info

Publication number
JPS54107327A
JPS54107327A JP1440178A JP1440178A JPS54107327A JP S54107327 A JPS54107327 A JP S54107327A JP 1440178 A JP1440178 A JP 1440178A JP 1440178 A JP1440178 A JP 1440178A JP S54107327 A JPS54107327 A JP S54107327A
Authority
JP
Japan
Prior art keywords
signals
counter
address
data
reference signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1440178A
Other languages
Japanese (ja)
Inventor
Koji Fukuhara
Taizo Sasada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP1440178A priority Critical patent/JPS54107327A/en
Publication of JPS54107327A publication Critical patent/JPS54107327A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To achieve the improvement of drop-out resistance characteristics by recording and reproducing the PCM signals having been given data numbers for each specified unit.
CONSTITUTION: PCM signals are written in a memory 31 according to the wirte address signals of an address counter 25 via multiplexer 26, the reference signal of a counter 27 or the read-out address signal at each specified number of horizontal synchronizing signals and the PCM signals of the specified units are applied from the memory 31 to a data selector 32. On the other hand, the address signals of the counter 27 are made to data number marks by a data converter 28 and shift register 29 and are applied to the selector 32 and the PCM signals containing the data number marks at each specified unit are recorded with a VTR, etc. This recording is similarly reproduced and an address counter 40 is controlled according to the data number marks by way of a shift register 36 and a data converter 37. The write address signals in synchronization with the reference signal outputted by the counter 40 may thus be well generated even at the missing of the reference signal owing to drop-out.
COPYRIGHT: (C)1979,JPO&Japio
JP1440178A 1978-02-09 1978-02-09 Pcm system recorder-peproducer Pending JPS54107327A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1440178A JPS54107327A (en) 1978-02-09 1978-02-09 Pcm system recorder-peproducer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1440178A JPS54107327A (en) 1978-02-09 1978-02-09 Pcm system recorder-peproducer

Publications (1)

Publication Number Publication Date
JPS54107327A true JPS54107327A (en) 1979-08-23

Family

ID=11860017

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1440178A Pending JPS54107327A (en) 1978-02-09 1978-02-09 Pcm system recorder-peproducer

Country Status (1)

Country Link
JP (1) JPS54107327A (en)

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