JPS5570919A - Memory control system - Google Patents
Memory control systemInfo
- Publication number
- JPS5570919A JPS5570919A JP14318078A JP14318078A JPS5570919A JP S5570919 A JPS5570919 A JP S5570919A JP 14318078 A JP14318078 A JP 14318078A JP 14318078 A JP14318078 A JP 14318078A JP S5570919 A JPS5570919 A JP S5570919A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- divided
- capacity
- keeping
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Error Detection And Correction (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
Abstract
PURPOSE: To enable the effective use of memory, by sectioning the capacity of memory to a given length and performing circulating memory for each part while keeping a given relation.
CONSTITUTION: The memory storage capacity is divided into the capacities M0W M3 different in lenght as 1, 3, 5, 7, for interleaving the data at the locations of h0Wh3, and the data is written to the memory while keeping the relation of length constant and the divided points aWd circulating in the memory, and also read out. In this case, the counters 18 and 20 equal to the total memory capacity 2N of the memory 5 are provided, the clock pulses fW and fR for write-in and readout are counted 18 and 20, and 0, 3, 8, 15 and 0, 1, 4, 9 are added 19, 21 in circulation manner to each count output to enable desired interleaving for each divided point while being circulated in the memory 5.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14318078A JPS5570919A (en) | 1978-11-20 | 1978-11-20 | Memory control system |
US06/095,553 US4333160A (en) | 1978-11-20 | 1979-11-19 | Memory control system |
GB7940028A GB2039193B (en) | 1978-11-20 | 1979-11-20 | Memory control system for interleaving digital signals |
DE19792946702 DE2946702A1 (en) | 1978-11-20 | 1979-11-20 | MEMORY CONTROL DEVICE |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14318078A JPS5570919A (en) | 1978-11-20 | 1978-11-20 | Memory control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5570919A true JPS5570919A (en) | 1980-05-28 |
Family
ID=15332745
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14318078A Pending JPS5570919A (en) | 1978-11-20 | 1978-11-20 | Memory control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5570919A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61107576A (en) * | 1984-10-31 | 1986-05-26 | Toshiba Corp | Control method for deinterleave processing memory in digital reproducing device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5522244A (en) * | 1978-07-28 | 1980-02-16 | Sanyo Electric Co Ltd | Memory system |
-
1978
- 1978-11-20 JP JP14318078A patent/JPS5570919A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5522244A (en) * | 1978-07-28 | 1980-02-16 | Sanyo Electric Co Ltd | Memory system |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61107576A (en) * | 1984-10-31 | 1986-05-26 | Toshiba Corp | Control method for deinterleave processing memory in digital reproducing device |
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