JPS5447541A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5447541A
JPS5447541A JP11330577A JP11330577A JPS5447541A JP S5447541 A JPS5447541 A JP S5447541A JP 11330577 A JP11330577 A JP 11330577A JP 11330577 A JP11330577 A JP 11330577A JP S5447541 A JPS5447541 A JP S5447541A
Authority
JP
Japan
Prior art keywords
sar
main memory
address
access
literal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11330577A
Other languages
Japanese (ja)
Inventor
Motonori Nagafuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11330577A priority Critical patent/JPS5447541A/en
Publication of JPS5447541A publication Critical patent/JPS5447541A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To shorten the time of the information access to the fixed address within the main memory with a small amount of the control storage capacity, by securing the setting of the literal constant address to the storage address register SAR.
CONSTITUTION: The data read out from control storage CS301 is ratched by control storage data register CSDR302 to give control to various areas. Decorder DEC303 functions when the specified pattern emerges at SAR setting field 31. The output of DEC303 is supplied to gate 304 an functions to ratch the contents of literal field 32 to SAR305. Thus, the literal constant is set to SAR with one cycle, and an access is given to the main memory at the next cycle. As a result, an access is ensured to the fixed address within the main memory in a high speed and with a small amount of the CS capacity
COPYRIGHT: (C)1979,JPO&Japio
JP11330577A 1977-09-22 1977-09-22 Information processor Pending JPS5447541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11330577A JPS5447541A (en) 1977-09-22 1977-09-22 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11330577A JPS5447541A (en) 1977-09-22 1977-09-22 Information processor

Publications (1)

Publication Number Publication Date
JPS5447541A true JPS5447541A (en) 1979-04-14

Family

ID=14608852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11330577A Pending JPS5447541A (en) 1977-09-22 1977-09-22 Information processor

Country Status (1)

Country Link
JP (1) JPS5447541A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5728605U (en) * 1980-07-25 1982-02-15

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5728605U (en) * 1980-07-25 1982-02-15

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