JPS55135762A - Ic test unit - Google Patents

Ic test unit

Info

Publication number
JPS55135762A
JPS55135762A JP4377479A JP4377479A JPS55135762A JP S55135762 A JPS55135762 A JP S55135762A JP 4377479 A JP4377479 A JP 4377479A JP 4377479 A JP4377479 A JP 4377479A JP S55135762 A JPS55135762 A JP S55135762A
Authority
JP
Japan
Prior art keywords
pattern
read out
control data
input
expected value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4377479A
Other languages
Japanese (ja)
Other versions
JPS6228874B2 (en
Inventor
Junji Nishiura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Takeda Riken Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp, Takeda Riken Industries Co Ltd filed Critical Advantest Corp
Priority to JP4377479A priority Critical patent/JPS55135762A/en
Priority to US06/069,345 priority patent/US4313200A/en
Publication of JPS55135762A publication Critical patent/JPS55135762A/en
Publication of JPS6228874B2 publication Critical patent/JPS6228874B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To enable test without dummy cycle, by reading out a control data such as input and output control data and mask data from the auxiliary memory at the same time when a test pattern or expected value pattern is read out.
CONSTITUTION: An address signal to access the auxiliary memories 7, 8 is stored at the part of a test pattern or expected value pattern, and as soon as the test pattern or the expected value pattern is read out, the auxiliary memories 7 and 8 access the address containing the control data required for the address signal read out from the input and output control data file section 1b and the mask data file section 1c, and contain a read out output to the input and output control register 4 and the mask register 6. When the test pattern or expected value pattern is read out from the pattern file section 1a, the input and output control data required for this pattern and the mask data are obtained from the auxiliary memories 7 and 8.
COPYRIGHT: (C)1980,JPO&Japio
JP4377479A 1978-08-28 1979-04-11 Ic test unit Granted JPS55135762A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP4377479A JPS55135762A (en) 1979-04-11 1979-04-11 Ic test unit
US06/069,345 US4313200A (en) 1978-08-28 1979-08-24 Logic test system permitting test pattern changes without dummy cycles

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4377479A JPS55135762A (en) 1979-04-11 1979-04-11 Ic test unit

Publications (2)

Publication Number Publication Date
JPS55135762A true JPS55135762A (en) 1980-10-22
JPS6228874B2 JPS6228874B2 (en) 1987-06-23

Family

ID=12673091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4377479A Granted JPS55135762A (en) 1978-08-28 1979-04-11 Ic test unit

Country Status (1)

Country Link
JP (1) JPS55135762A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58208859A (en) * 1982-05-17 1983-12-05 フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン Test system memory device for testing dynamic component while passing parameter

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5585265A (en) * 1978-12-23 1980-06-27 Toshiba Corp Function test evaluation device for integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5585265A (en) * 1978-12-23 1980-06-27 Toshiba Corp Function test evaluation device for integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58208859A (en) * 1982-05-17 1983-12-05 フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン Test system memory device for testing dynamic component while passing parameter
JPH0354370B2 (en) * 1982-05-17 1991-08-20

Also Published As

Publication number Publication date
JPS6228874B2 (en) 1987-06-23

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