JPS55122216A - Magnetic card read/write control unit - Google Patents

Magnetic card read/write control unit

Info

Publication number
JPS55122216A
JPS55122216A JP2824079A JP2824079A JPS55122216A JP S55122216 A JPS55122216 A JP S55122216A JP 2824079 A JP2824079 A JP 2824079A JP 2824079 A JP2824079 A JP 2824079A JP S55122216 A JPS55122216 A JP S55122216A
Authority
JP
Japan
Prior art keywords
cpu
data
write
read
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2824079A
Other languages
Japanese (ja)
Inventor
Tsutomu Takenaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2824079A priority Critical patent/JPS55122216A/en
Publication of JPS55122216A publication Critical patent/JPS55122216A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To shorten the processing time by using effectively going and returning pathes of cards.
CONSTITUTION: When command 1 is set from a CPU to FF21, gates 9W12 and 13W16 are opened. Next, when a write signal is set from the CPU to timing control circuit 3, write data WD1 to WD8 pass through gates 9W12 and are written from shift register 4 to magnetic card read/write unit 1. Then, read data is converted to parallel data by shift register 2 in the operation of the returning path and has bit arrangement reversed by gates 13W16 and is transmitted to the CPU as read data RD1WRD8. In case that data read and write are performed in the going path and the returning path resectively, command 2 is given from the CPU to FF21.
COPYRIGHT: (C)1980,JPO&Japio
JP2824079A 1979-03-13 1979-03-13 Magnetic card read/write control unit Pending JPS55122216A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2824079A JPS55122216A (en) 1979-03-13 1979-03-13 Magnetic card read/write control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2824079A JPS55122216A (en) 1979-03-13 1979-03-13 Magnetic card read/write control unit

Publications (1)

Publication Number Publication Date
JPS55122216A true JPS55122216A (en) 1980-09-19

Family

ID=12243058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2824079A Pending JPS55122216A (en) 1979-03-13 1979-03-13 Magnetic card read/write control unit

Country Status (1)

Country Link
JP (1) JPS55122216A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61240408A (en) * 1985-04-17 1986-10-25 Canon Inc Recognising method for record information
JPS6246469A (en) * 1985-08-24 1987-02-28 Tohoku Metal Ind Ltd Magnetic card and its information recording system
US5909418A (en) * 1994-08-26 1999-06-01 Nippon Conlux Co., Ltd. Optical information recording device and method for detecting and verifying recorded information

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61240408A (en) * 1985-04-17 1986-10-25 Canon Inc Recognising method for record information
JPS6246469A (en) * 1985-08-24 1987-02-28 Tohoku Metal Ind Ltd Magnetic card and its information recording system
US5909418A (en) * 1994-08-26 1999-06-01 Nippon Conlux Co., Ltd. Optical information recording device and method for detecting and verifying recorded information

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