JPS5566042A - Memory control circuit - Google Patents

Abstract

PURPOSE: To make it possible that the memory unit side has a TEST&SET instruction by setting a read operation state and a write operation state in the first half and the latter of one operation cycle respectively in respect to memory access.

CONSTITUTION: AND between memory access signal 10 and the result obtained by decoding 6 the signal on address bus 9 is operated in 8C, and memory unit 4 is accessed. Read of read/write command R/W to memory 4 is performed in a low level, and a write command is delayed by a fixed time by delay line 7a and is given to memory 4 through AND gate 8a. Consequently, the read/write command can be defined as a read command in the first half of memory access and can be changed to a write command in the latter at the end of read. In respect to write data, all "1" or "0" data is written in the memory according to presence or absence of signals on command line 11 sent from a processing unit. Read data from memory 4 is transmitted to data bus 12. The response signal for memory access is transmitted to response signal line 13 after delayed by a fixed time in 7b, so that the TEST& SET function can be realized by memory control circuit 5.

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